- Jan 27, 2020
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Yifan Zhao authored
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- Jan 24, 2020
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Yifan Zhao authored
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- Jan 23, 2020
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Yifan Zhao authored
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Yifan Zhao authored
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- Jan 22, 2020
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Adel Ejjeh authored
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Akash Kothari authored
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Adel Ejjeh authored
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Yifan Zhao authored
This reverts merge request !9
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Yifan Zhao authored
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- Jan 21, 2020
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Yifan Zhao authored
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Yifan Zhao authored
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Yifan Zhao authored
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- Jan 20, 2020
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Akash Kothari authored
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- Jan 17, 2020
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Akash Kothari authored
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- Jan 09, 2020
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Akash Kothari authored
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- Jan 08, 2020
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Akash Kothari authored
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Akash Kothari authored
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Akash Kothari authored
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- Jan 07, 2020
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Akash Kothari authored
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- Dec 27, 2019
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Hashim Sharif authored
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- Dec 26, 2019
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Hashim Sharif authored
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Hashim Sharif authored
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- Oct 29, 2018
- Oct 23, 2018
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kotsifa2 authored
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- Aug 19, 2017
- Aug 11, 2017
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kotsifa2 authored
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- Aug 10, 2017
- Aug 09, 2017
- Aug 07, 2017
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kotsifa2 authored
(CPU/GPU/SPIR) based on policy. Support for scheduling per iteration included. Further testing required.
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- Jun 14, 2017
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Prakalp Srivastava authored
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- Apr 06, 2017
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kotsifa2 authored
The SymVT stuff has not been moved yet, I removed it for now. The test/VISC tests also have not been moved yet, so they may not work.
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- May 01, 2016
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Prakalp Srivastava authored
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- Mar 15, 2016
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Prakalp Srivastava authored
get_global_size (2) Code gen for nvvm intrinsics in GenVISC pass (3) Commented out code added to GenVISC and DFG2LLVM_X86 to allow wait instruction in a different BB than launch (with phi nodes as uses of launch)
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- Dec 03, 2015
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Prakalp Srivastava authored
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