not). Code generation uses it.
- Added a policy that uses it.

Tested on pipeline benchmark.

(benchmark not updated)

Bug fix in nvptx and spir backends related to adding arguments to
node functions.

(CPU/GPU/SPIR) based on policy.
Support for scheduling per iteration included.
Further testing required.

Made visc-rt threadsafe by implementing locks across all ocl functions. Very crude. Fine grained locking possible if performance deteriotes

    - IntrinsicsVISC.td, visc.h, GenVISC.cpp
(2) Simplified GenVISC to easily add support for new intrinsics which have a 1
to 1 mapping instruction during code gen
(3) Added runtime api call to set ocl shared memory argument

request_mem failure
(2) modified visc_sh version of sgemm

(2) EdgeDetection pipeline example working

Added singleNodeStream.ll and twoNodeStream.ll test cases

(1) Changes to DFGraph.h for identifying streaming graphs and edges
(2) Added/modified launch, wait, push, pop intrinsics for streaming graphs
(3) Changes to DFG2LLVM_X86.cpp and DFG2LLVM.h pass to support code gen for streaming
(4) BuildDFG.cpp modified to create streaming edges
(5) Modified visc-rt.cpp and visc-rt.h to add runtime support for streaming

Choose device in init context than in execute node
(Might want to expand to multiple devices in future)
Modifications also include code for choosing sub devices for x86 target,
although that code is inside an always false if condition

code enquires about its ancestor. Enables to run visc parboil benchmarks on x86
alone

(2) Modified unittests to have llvm.visc.init and cleanup intrinsics. Now they
all pass

(3) Modified visc.mk to easily compile visc version for just x86. Pass
TARGET=x86 as option to make command

(2) Added dummy function calls for visc initialization and visc clean up to
benchmarks and added support for it to all the passes.
(3) Timers are now only printed once
(4) Added extra timers to parboil header file