- Apr 01, 2021
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Yifan Zhao authored
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- Dec 21, 2020
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Akash Kothari authored
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Akash Kothari authored
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- Dec 20, 2020
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Akash Kothari authored
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- Feb 17, 2020
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Akash Kothari authored
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- Dec 26, 2019
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Hashim Sharif authored
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- Dec 18, 2019
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Adel Ejjeh authored
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- Sep 20, 2018
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Prakalp Srivastava authored
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- Aug 10, 2017
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kotsifa2 authored
Compiles correcctly for all targets and target combinations, pending fix in python script for llvm 4.0 -> llvm 3.4
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- Aug 09, 2017
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kotsifa2 authored
Bug fix in nvptx and spir backends related to adding arguments to node functions.
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- Aug 07, 2017
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kotsifa2 authored
(CPU/GPU/SPIR) based on policy. Support for scheduling per iteration included. Further testing required.
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- Jul 26, 2017
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Prakalp Srivastava authored
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- Jun 14, 2017
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Prakalp Srivastava authored
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- Jun 07, 2017
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Prakalp Srivastava authored
Added parsing support for visc in,out,inout attributes. Commit ef703216 in previous llvm 3.4 based repo
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- Apr 06, 2017
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kotsifa2 authored
The SymVT stuff has not been moved yet, I removed it for now. The test/VISC tests also have not been moved yet, so they may not work.
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- Dec 03, 2016
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Prakalp Srivastava authored
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- May 01, 2016
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Prakalp Srivastava authored
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- Mar 20, 2016
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Prakalp Srivastava authored
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Prakalp Srivastava authored
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- Mar 19, 2016
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Prakalp Srivastava authored
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- Mar 16, 2016
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Prakalp Srivastava authored
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Prakalp Srivastava authored
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Prakalp Srivastava authored
Fixed a bug introduced by commit bfe38be9 in ptx backend. declarations were not being copied to kernel module. Fixed those
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Prakalp Srivastava authored
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- Mar 15, 2016
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Prakalp Srivastava authored
get_global_size (2) Code gen for nvvm intrinsics in GenVISC pass (3) Commented out code added to GenVISC and DFG2LLVM_X86 to allow wait instruction in a different BB than launch (with phi nodes as uses of launch)
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- Mar 12, 2016
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Prakalp Srivastava authored
the target dependent attributes are not required and break the compilation through PTX backend. This fixed tpacf compilation bug
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- Mar 11, 2016
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Prakalp Srivastava authored
- IntrinsicsVISC.td, visc.h, GenVISC.cpp (2) Simplified GenVISC to easily add support for new intrinsics which have a 1 to 1 mapping instruction during code gen (3) Added runtime api call to set ocl shared memory argument
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- Mar 08, 2016
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Prakalp Srivastava authored
(2) Fixed a bug in sgemm visc_sh version. Wrong grid size was used earlier, resulting in the bug
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- Mar 07, 2016
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Maria Kotsifakou authored
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- Mar 05, 2016
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Prakalp Srivastava authored
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Prakalp Srivastava authored
edge to be from parent node, whereas an edge from parent node has Entry node as its source. Hence the check SrcDFNode != PNode was always true. Changed to !SrcDFNode->isDummyNode()
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- Mar 04, 2016
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Maria Kotsifakou authored
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- Mar 03, 2016
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Prakalp Srivastava authored
This one identifies allocation node and add s the property to the node. Can be used by passes later
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- Dec 03, 2015
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Prakalp Srivastava authored
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- Aug 05, 2015
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Prakalp Srivastava authored
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- Aug 02, 2015
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Prakalp Srivastava authored
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- Aug 01, 2015
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Prakalp Srivastava authored
Created Abstract class DFG2LLVM. The two passes DFG2LLVM_NVPTX and DFG2LLVM_X86 inherit from this class. Common features/functions have been put in the abstract class DFG2LLVM
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- Jul 14, 2015
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Prakalp Srivastava authored
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- Jun 18, 2015
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Prakalp Srivastava authored
code enquires about its ancestor. Enables to run visc parboil benchmarks on x86 alone (2) Modified unittests to have llvm.visc.init and cleanup intrinsics. Now they all pass (3) Modified visc.mk to easily compile visc version for just x86. Pass TARGET=x86 as option to make command
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- Jun 05, 2015
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Prakalp Srivastava authored
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