Compiles correcctly for all targets and target combinations,
pending fix in python script for llvm 4.0 -> llvm 3.4

Bug fix in nvptx and spir backends related to adding arguments to
node functions.

(CPU/GPU/SPIR) based on policy.
Support for scheduling per iteration included.
Further testing required.

Added parsing support for visc in,out,inout attributes. Commit ef703216 in previous llvm 3.4 based repo

The SymVT stuff has not been moved yet, I removed it for now.
The test/VISC tests also have not been moved yet, so they may not
work.

Fixed a bug introduced by commit bfe38be9 in ptx backend. declarations were not being copied to kernel module. Fixed those

get_global_size
(2) Code gen for nvvm intrinsics in GenVISC pass
(3) Commented out code added to GenVISC and DFG2LLVM_X86 to allow wait
instruction in a different BB than launch (with phi nodes as uses of launch)

the target dependent attributes are not required and break the compilation
through PTX backend. This fixed tpacf compilation bug

    - IntrinsicsVISC.td, visc.h, GenVISC.cpp
(2) Simplified GenVISC to easily add support for new intrinsics which have a 1
to 1 mapping instruction during code gen
(3) Added runtime api call to set ocl shared memory argument

(2) Fixed a bug in sgemm visc_sh version. Wrong grid size was used earlier,
resulting in the bug

edge to be from parent node, whereas an edge from parent node has Entry node as
its source. Hence the check SrcDFNode != PNode was always true. Changed to
!SrcDFNode->isDummyNode()

This one identifies allocation node and add s the property to the node. Can be
used by passes later