Added old text to Related work

paper/Abstract.tex

@@ -7,14 +7,14 @@ However, programming such systems can be extremely complex as a single
 SoC combines multiple different
 parallelism models, instruction sets, and memory hierarchies, and different 
 SoCs use \emph{different combinations} of these features.
-We propose a new Virtual Instruction Set Architecture (ISA) that aims to 
+We propose \NAME{}, a new Virtual Instruction Set Architecture (ISA) that aims to 
 address both functional portability and performance portability across
 mobile heterogeneous SoCs by capturing the wide range of different 
 parallelism models expected to be available on future SoCs.
 Our virtual ISA design uses only two parallelism models to achieve this goal:
 \emph{a hierarchical dataflow graph with side effects} and
 \emph{parametric vector instructions}.
-Our virtual ISA is more general than existing ones that focus heavily on GPUs,
+\NAME{} is more general than existing ones that focus heavily on GPUs,
 such as PTX, HSAIL and SPIR, e.g., it can capture both streaming pipelined
 parallelism and general dataflow parallelism found in many custom and 
 semi-custom (programmable) accelerators.

paper/Compilation.tex

@@ -98,7 +98,7 @@ Algorithm~\ref{algo:traversal} to traverse the graph of any internal node $N$.
         \State $L \gets$ list of all nodes of $G$ in topological order
         \While {$L$ is non-empty}
           \State remove a node $n$ from $L$
-          \State $\textsc{CodeGen}(n)$
+          \State $\textsc{Visit}(n)$
         \EndWhile
       \EndIf
     \EndProcedure

paper/RelatedWork.tex

 \section{Related Work}
 \label{sec:related}
-\todo[inline]{Source level programming languages}
-\todo[inline]{Object code representation}
-\todo[inline]{Compiler techniques - Tangram, Samar}
+\todo[inline]{Source level programming languages OpenCL, CUDA, Renderscript,
+Delite, ispc, halide}
+There are currently a few projects aiming to address the programmability and
+portability challenges of SoC applications, but the ones focused at the source
+level such as OpenCL~\cite{OpenCL}, Lime~\ref{Lime} and
+Renderscript~\cite{Renderscript}, are inadequate because they usually do not
+provide adequately general parallelism models, which makes them unsuitable for
+general purpose computation, and none of them provides object code portability,
+with the exception of Renderscript. Renderscript, however, is tailored for image
+filtering applications and uses LLVM scalar and vector code as its portable
+object code format. Thus, it does not provide appropriate abstractions for the
+different classes of parallel hardware.
+
+\todo[inline]{Object code representation HSAIL, SPIR, PTX}
+The ones focused on the object level
+such as nVidia’s PTX~\cite{PTX2.3Manual:URL}, OpenCL SPIR~\cite{SPIRKhronosSpec}, HSAIL~\cite{HSAIL} are either limited in scope of
+supported hardware (for instance, PTX is designed specifically for nVidia
+GPUs) or expose a restrictive throughput-oriented data parallelism and no other
+models like dataflow-style or task parallelsim required across different
+hardware.
+
+\todo[inline]{Compiler techniques - Tangram, Samar Amarasinghe's work}