Add more LLVM attributes

• Add more LLVM attributes in the CPU backend.

hercules_cg/src/cpu.rs

@@ -68,7 +68,7 @@ impl<'a> CPUContext<'a> {
             if self.types[return_type.idx()].is_primitive() {
                 write!(
                     w,
-                    "define dso_local nounwind nosync willreturn norecurse {} @{}_{}(",
+                    "define dso_local {} @{}_{}(",
                     self.get_type(return_type),
                     self.module_name,
                     self.function.name,
@@ -76,7 +76,7 @@ impl<'a> CPUContext<'a> {
             } else {
                 write!(
                     w,
-                    "define dso_local nonnull noundef nounwind nosync willreturn norecurse {} @{}_{}(",
+                    "define dso_local nonnull noundef {} @{}_{}(",
                     self.get_type(return_type),
                     self.module_name,
                     self.function.name,
@@ -96,7 +96,7 @@ impl<'a> CPUContext<'a> {
             )?;
             write!(
                 w,
-                "define dso_local nounwind nosync willreturn norecurse void @{}_{}(",
+                "define dso_local void @{}_{}(",
                 self.module_name, self.function.name,
             )?;
         }
@@ -146,7 +146,7 @@ impl<'a> CPUContext<'a> {
                 self.function.name,
             )?;
         }
-        write!(w, ") {{\n")?;
+        write!(w, ") nounwind nosync willreturn norecurse {{\n")?;
 
         let mut blocks: BTreeMap<_, _> = (0..self.function.nodes.len())
             .filter(|idx| self.function.nodes[*idx].is_control())