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Fang Lu / osu-fpga
OtherECE 385 Final Project by Fang Lu and Xutao Jiang. See docs/final-report.md for detailed descriptions.
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Finding out the smaller IP module from OpenSPARC T2 that can be synthesized avoiding all the black boxes
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paulrr2 / fpga-network-stack
BSD 3-Clause "New" or "Revised" LicenseScalable Network Stack for FPGAs (TCP/IP, RoCEv2)
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haiyang3 / Verilog Ethernet
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