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Finding out the smaller IP module from OpenSPARC T2 that can be synthesized avoiding all the black boxes

ECE 385 Final Project by Fang Lu and Xutao Jiang. See docs/final-report.md for detailed descriptions.

ECE527 Final Project: Babel SoC

100 Gbps TCP/IP stack for Vitis shells

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)