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Fang Lu / osu-fpga
Other

ECE 385 Final Project by Fang Lu and Xutao Jiang. See docs/final-report.md for detailed descriptions.

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Updated Dec 14, 2017

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Updated Dec 14, 2017
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rnai2 / Urchin

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Updated Oct 20, 2019

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Updated Oct 20, 2019
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rnai2 / 385-final-project-attempt2

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Updated Dec 04, 2020

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Updated Dec 04, 2020
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paulrr2 / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

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Updated Dec 12, 2020

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Updated Dec 12, 2020
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paulrr2 / fpga-network-stack
BSD 3-Clause "New" or "Revised" License

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

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Updated Dec 18, 2020

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Updated Dec 18, 2020
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Jack Stender / ECE385 Final Project

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Updated Mar 13, 2022

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Updated Mar 13, 2022
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Senior Design / Musical Hand Fpga Test

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Updated Apr 05, 2022

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Updated Apr 05, 2022
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haiyang3 / Verilog Ethernet
MIT License

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Updated Apr 29, 2022

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Updated Apr 29, 2022
Andy Popovich / ECE385-Final-Project

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Updated May 06, 2022

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Updated May 06, 2022
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zdm3 / ECE385FinalProject

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Updated May 05, 2023

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Updated May 05, 2023
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nuoyanw2 / FPGA Synthesizer

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Updated Jun 08, 2023

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Updated Jun 08, 2023
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ie421_high_frequency_trading_fall_2023 / ie421_hft_fall_2023_group_06 / group_06_project

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Updated May 04, 2024

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Updated May 04, 2024
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fin556_algo_market_micro_fall_2023 / fin556_algo_fall_2023_group_04 / group_04_project

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Updated May 04, 2024

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Updated May 04, 2024