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OUTDATED Verse-library
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AutonomyCourse_ECEIllinois
OUTDATED Verse-library
Commits
14a04b7d
Commit
14a04b7d
authored
2 years ago
by
crides
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expr
parent
9840ebf0
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1 merge request
!9
Tutorial
Changes
3
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3 changed files
demo/vehicle/controller/inc-expr-fsw4.py
+2
-2
2 additions, 2 deletions
demo/vehicle/controller/inc-expr-fsw4.py
demo/vehicle/inc-expr.py
+2
-1
2 additions, 1 deletion
demo/vehicle/inc-expr.py
inc-expr.py
+7
-4
7 additions, 4 deletions
inc-expr.py
with
11 additions
and
7 deletions
demo/vehicle/controller/inc-expr-fsw4.py
+
2
−
2
View file @
14a04b7d
...
...
@@ -52,13 +52,13 @@ def controller(ego:State, others:List[State], lane_map):
output
=
copy
.
deepcopy
(
ego
)
if
ego
.
vehicle_mode
==
VehicleMode
.
Normal
:
# Switch left if left lane is empty
if
car_front
(
ego
,
others
,
lane_map
,
4
,
3
):
if
car_front
(
ego
,
others
,
lane_map
,
4
.5
,
3
):
if
lane_map
.
has_left
(
ego
.
lane_mode
)
and
\
not
car_left
(
ego
,
others
,
lane_map
):
output
.
vehicle_mode
=
VehicleMode
.
SwitchLeft
# Switch right if right lane is empty
if
car_front
(
ego
,
others
,
lane_map
,
4
,
3
):
if
car_front
(
ego
,
others
,
lane_map
,
4
.5
,
3
):
if
lane_map
.
has_right
(
ego
.
lane_mode
)
and
\
not
car_right
(
ego
,
others
,
lane_map
):
output
.
vehicle_mode
=
VehicleMode
.
SwitchRight
...
...
This diff is collapsed.
Click to expand it.
demo/vehicle/inc-expr.py
+
2
−
1
View file @
14a04b7d
...
...
@@ -52,7 +52,7 @@ if 'p' in arg:
def
run
(
sim
,
meas
=
False
):
time
=
timeit
.
default_timer
()
if
sim
:
traces
=
scenario
.
simulate
(
60
,
0.
05
)
traces
=
scenario
.
simulate
(
60
,
0.
1
)
else
:
traces
=
scenario
.
verify
(
60
,
0.1
)
...
...
@@ -78,6 +78,7 @@ def run(sim, meas=False):
"
dur
"
:
timeit
.
default_timer
()
-
time
,
"
cache_size
"
:
cache_size
,
"
node_count
"
:
len
(
traces
.
nodes
),
"
hits
"
:
scenario
.
simulator
.
cache_hits
if
sim
else
(
scenario
.
verifier
.
tube_cache_hits
,
scenario
.
verifier
.
trans_cache_hits
),
})
if
__name__
==
"
__main__
"
:
...
...
This diff is collapsed.
Click to expand it.
inc-expr.py
+
7
−
4
View file @
14a04b7d
...
...
@@ -3,6 +3,7 @@ from itertools import product
from
pprint
import
pp
import
re
from
subprocess
import
PIPE
,
Popen
from
typing
import
Tuple
,
Union
@dataclass
class
ExperimentResult
:
...
...
@@ -12,10 +13,11 @@ class ExperimentResult:
cache_size
:
float
node_count
:
int
ret_code
:
int
cache_hits
:
Union
[
Tuple
[
int
,
int
],
Tuple
[
Tuple
[
int
,
int
],
Tuple
[
int
,
int
]]]
xprms
=
[
"
v
"
+
""
.
join
(
l
)
for
l
in
product
(
"
n8
"
,
(
""
,
"
i
"
))]
#
"v" +
""
.
join
(
l
)
for
l
in
product
(
"
br
n8
"
,
(
""
,
"
i
"
))]
rslts
=
[]
for
xprm
in
xprms
:
cmd
=
Popen
(
f
"
/usr/bin/time -v -- python3.8 demo/vehicle/inc-expr.py
{
xprm
}
"
,
stdout
=
PIPE
,
stderr
=
PIPE
,
shell
=
True
)
...
...
@@ -30,7 +32,7 @@ for xprm in xprms:
print
(
b
""
.
join
(
stderr
))
exit
(
2
)
info
=
eval
(
filtered_info
[
0
])
rslt
=
ExperimentResult
(
xprm
,
max_mem
,
info
[
"
dur
"
],
info
[
"
cache_size
"
]
/
1_000_000
,
info
[
"
node_count
"
],
ret
)
rslt
=
ExperimentResult
(
xprm
,
max_mem
,
info
[
"
dur
"
],
info
[
"
cache_size
"
]
/
1_000_000
,
info
[
"
node_count
"
],
ret
,
info
[
"
hits
"
]
)
pp
(
rslt
)
if
rslt
.
ret_code
!=
0
:
print
(
f
"
uh oh, var=
{
xprm
}
ret=
{
rslt
.
ret_code
}
"
)
...
...
@@ -50,4 +52,5 @@ for i in range(0, len(rslts), 2):
elif
"
8
"
in
var
:
name
=
"
change ctlr
"
print
(
"
&
"
+
"
&
"
.
join
([
name
]
+
[
str
(
i
)
for
i
in
[
inc
.
node_count
,
round
(
no
.
duration
,
2
),
round
(
no
.
max_mem
),
round
(
inc
.
duration
,
2
),
round
(
inc
.
max_mem
),
round
(
inc
.
cache_size
,
2
)]])
+
"
\\\\
"
)
cache_hit_rate
=
inc
.
cache_hits
[
0
]
/
(
inc
.
cache_hits
[
0
]
+
inc
.
cache_hits
[
1
])
if
"
v
"
not
in
var
else
(
inc
.
cache_hits
[
0
][
0
]
+
inc
.
cache_hits
[
1
][
0
])
/
(
inc
.
cache_hits
[
0
][
0
]
+
inc
.
cache_hits
[
0
][
1
]
+
inc
.
cache_hits
[
1
][
0
]
+
inc
.
cache_hits
[
1
][
1
])
print
(
"
&
"
+
"
&
"
.
join
([
name
]
+
[
str
(
i
)
for
i
in
[
inc
.
node_count
,
round
(
no
.
duration
,
2
),
round
(
no
.
max_mem
),
round
(
inc
.
duration
,
2
),
round
(
inc
.
max_mem
),
round
(
inc
.
cache_size
,
2
),
round
(
cache_hit_rate
*
100
,
2
)]])
+
"
\\\\
"
)
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Click to expand it.
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