diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/alexnet_dsoc/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/alexnet_dsoc/Makefile
deleted file mode 100644
index bb0fc4fa9abb2e92da01ca90c6cabae5fabb280b..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/alexnet_dsoc/Makefile
+++ /dev/null
@@ -1,74 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-# NOTE: can configure build directory
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_dsoc/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = alexnet
-
-define \n
-
-
-endef
-
-COMMON_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-DNN_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/dnn_sources/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_RT_SRC_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/src
-
-# -std=c++11 -D_GLIBCXX_USE_CXX11_ABI=0
-# -I $(TENSOR_INCLUDE_DIR)
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(DNN_INCLUDE_DIR) -I $(COMMON_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-LINKER_FLAGS = -lpthread -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-OPTFLAGS1 = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/ReplaceIntrinsics.so -load $(HPVM_LIB_DIR)/DFG2LLVM_X86_dsoc.so -load $(HPVM_LIB_DIR)/ExtractHPVMLeafNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -replace-intrinsics -dfg2llvm-x86-dsoc -hpvm-extract-leaf-gen -clearDFG
-
-OPTFLAGS2 = -load $(HPVM_LIB_DIR)/InlineTensorCalls.so -inline-tensor-calls
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/projects/visc-cpu-rt/visc-rt.ll
-#VISC_RT_PATH = $(HPVM_BUILD_DIR)/projects/visc-cpu-rt/visc-rt.ll
-
-
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm -S -o $@ $<
-
-#-visc-timers-gen
-$(BUILD_DIR)/%.visc.ll: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $< -S -o $@
-
-
-expanded_modules:= $(wildcard *_module.ll)
-
-
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.visc.ll
- $(OPT) $(OPTFLAGS1) $< -o $@
- $(CC) -emit-llvm -c $(TENSOR_RT_SRC_DIR)/tensor_cpu_runtime.cc -o $(BUILD_DIR)/tensor_cpu_runtime.bc
- $(OPT) -always-inline $(BUILD_DIR)/tensor_cpu_runtime.bc -o $(BUILD_DIR)/tensor_cpu_runtime.bc
- $(LLVM_LINK) $@ $(shell find ./build -name "*module.ll") $(BUILD_DIR)/tensor_cpu_runtime.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_tensor_rt.bc
- $(OPT) $(OPTFLAGS2) $(BUILD_DIR)/$(APP)_tensor_rt.bc -o $(BUILD_DIR)/$(APP)_inline.bc
- $(CC) $(BUILD_DIR)/$(APP)_inline.bc -o $(BUILD_DIR)/$(APP)_final $(LINKER_FLAGS)
- $(foreach module, $(expanded_modules), $(LLVM_LINK) $(module) $(BUILD_DIR)/tensor_cpu_runtime.bc -o $(BUILD_DIR)/$(module)_linked ${\n} $(OPT) $(OPTFLAGS2) $(BUILD_DIR)/$(module)_linked -o $(BUILD_DIR)/$(module)_inline ${\n} )
-
-
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/alexnet_dsoc/src/alexnet.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/alexnet_dsoc/src/alexnet.cpp
deleted file mode 100644
index ab7c3c344e92a50cb3a43d49de1e49544588691a..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/alexnet_dsoc/src/alexnet.cpp
+++ /dev/null
@@ -1,449 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-
-#include <utils_cpu.h>
-
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 5, 5, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(13, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 10, 2, 0);
- __visc__bindIn(var_8, 11, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 12, 2, 0);
- __visc__bindIn(var_9, 13, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 14, 2, 0);
- __visc__bindIn(var_11, 15, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 16, 2, 0);
- __visc__bindIn(var_12, 17, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 22, 2, 0);
- __visc__bindIn(var_18, 23, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
- __visc__bindIn(var_19, 24, 2, 0);
- __visc__bindIn(var_19, 25, 3, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- __visc__bindOut(var_20, 0, 0, 0);
- __visc__bindOut(var_20, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/alexnet_cifar10_test/");
-
- int input_size = 50;
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0, input_size,3,32,32);
-
- std::string labels_path = dir_prefix + std::string("labels.bin");
- uint8_t* labels = readLabels(labels_path.c_str(), input_size);
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,64,3,11,11);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,192,64,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,192,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,384,192,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,384,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,256,384,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,256,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,4096,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
-
-
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, input_size, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/Makefile
deleted file mode 100644
index 16a940154d111cce78d76650a2916cb8538d21ea..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/Makefile
+++ /dev/null
@@ -1,64 +0,0 @@
-# NOTE: $LLVM_SRC_ROOT and $CUDA_TOOLKIT_ROOT_DIR have to be set
-# HPVM_BUILD_DIR can be optionally set
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-HPVM_BUILD_DIR ?= $(LLVM_SRC_ROOT)/../build
-
-CCLANG ?= $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-# NOTE: Change to the name of your benchmark
-APP = blend
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-CUSTOM_LIB_PATHS = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a \
- $(LLVM_SRC_ROOT)/projects/gpu_profiler/lib/libgpu_profiler.a \
- $(LLVM_SRC_ROOT)/projects/soc_simulator/lib/libpromise_profiler.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_TOOLKIT_ROOT_DIR)/include -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -L $(CUDA_TOOLKIT_ROOT_DIR)/lib64 -lstdc++fs -lpthread -lcudart -lcurand -lcudnn -lcublas -lcufft
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-CONF_FILE_PATH=$(realpath data/tuner_confs.txt)
-# NOTE: Needs proper handling in the WRAPPER backend because Quant range not needed for IMAGE Benchmarks
-WRAPPER_API_QUANT_FILE_PATH=
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_WrapperAPI.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMFuseHPVMTensorNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -hpvm-fuse -dfg2llvm-wrapperapi -quantization-levels-filename=$(WRAPPER_API_QUANT_FILE_PATH) -configuration-inputs-filename=$(CONF_FILE_PATH) -dfg2llvm-x86 -clearDFG
-
-
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc direct
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CCLANG) $(CC_FLAGS) -emit-llvm src/$(APP).cpp -S -o $(BUILD_DIR)/$(APP).ll
-
-direct: $(SRC_DIR)/$(APP)_direct_call.cpp $(BUILD_DIR)
- $(CCLANG) $(CC_FLAGS) src/$(APP)_direct_call.cpp $(CUSTOM_LIB_PATHS) -o $(BUILD_DIR)/$(APP)_direct_call $(LINKER_FLAGS)
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP).ll -S -o $(BUILD_DIR)/$(APP).visc.ll
- $(OPT) $(VISC_OPTFLAGS) $(BUILD_DIR)/$(APP).visc.ll -o $(BUILD_DIR)/$(APP)_wrapper.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_wrapper.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_wrapper_linked.bc
- $(CCLANG) $(BUILD_DIR)/$(APP)_wrapper_linked.bc $(CUSTOM_LIB_PATHS) $(PROMISE_PROFILER_LIB_PATH) -o $(BUILD_DIR)/$(APP)_final $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/autotuner_data/tuner_confs_25.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/autotuner_data/tuner_confs_25.txt
deleted file mode 100644
index 559248efcee30dc99cbec272f909623edcf684ea..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/autotuner_data/tuner_confs_25.txt
+++ /dev/null
@@ -1,1020 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu conv fp32 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp32 1
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf1 1.5201 1.0000 45.9782 154.0218
-1 gpu conv perf 23
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce fp32 44
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf2 1.4742 1.0000 47.4863 152.5137
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf3 1.4684 1.0000 46.7024 153.2976
-1 gpu conv samp 35
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf4 1.5207 1.0000 46.5771 153.4229
-1 gpu conv samp 32
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf5 1.5541 1.0000 45.4949 154.5051
-1 gpu conv samp 32
-2 gpu reduce fp32 42
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf6 1.5413 1.0000 45.6881 154.319
-1 gpu conv perf 21
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf7 1.4310 1.0000 47.8623 152.1377
-1 gpu conv fp16 1
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf8 1.4999 1.0000 46.1501 153.8499
-1 gpu conv samp 32
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 33
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf9 1.4737 1.0000 46.6856 153.3144
-1 gpu conv samp 35
-2 gpu reduce fp32 44
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf10 1.3950 1.0000 48.4016 151.5984
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf11 1.5060 1.0000 45.8831 154.169
-1 gpu conv samp 35
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf12 1.5820 1.0000 45.7022 154.2978
-1 gpu conv perf 21
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf13 1.4843 1.0000 46.4198 153.5802
-1 gpu conv samp 31
-2 gpu reduce fp32 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf14 1.2734 1.0000 51.501 148.4988
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf15 1.5472 1.0000 45.7376 154.2624
-1 gpu conv samp 32
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf16 1.4259 1.0000 47.1001 152.8999
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf17 1.5897 1.0000 45.6305 154.3695
-1 gpu conv samp 31
-2 gpu reduce fp32 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf18 1.3780 1.0000 48.391 151.6088
-1 gpu conv perf 24
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce fp32 44
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf19 1.4994 1.0000 46.1997 153.8003
-1 gpu conv samp 36
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf20 1.5384 1.0000 45.9064 154.0936
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf21 1.5899 1.0000 45.4947 154.5053
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf22 1.5174 1.0000 46.3973 153.6027
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf23 1.4220 1.0000 47.1609 152.8391
-1 gpu conv perf 25
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 29
-10 gpu reduce fp32 1
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf24 1.4426 1.0000 47.6050 152.3950
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 29
-10 gpu reduce fp32 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf25 1.5521 1.0000 45.4865 154.5135
-1 gpu conv samp 31
-2 gpu reduce fp32 42
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf26 1.5222 1.0000 45.7529 154.2471
-1 gpu conv perf 28
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 44
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf27 1.4648 1.0000 47.1608 152.8392
-1 gpu conv samp 35
-2 gpu reduce fp32 44
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf28 1.5414 1.0000 45.6762 154.3238
-1 gpu conv samp 31
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf29 1.3965 1.0000 48.0457 151.9543
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf30 1.4899 1.0000 45.9532 154.0468
-1 gpu conv perf 24
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 42
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf31 1.5130 1.0000 45.8968 154.1032
-1 gpu conv samp 35
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 42
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf32 1.5932 1.0000 45.3590 154.6410
-1 gpu conv samp 31
-2 gpu reduce fp32 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf33 1.4659 1.0000 46.8296 153.1704
-1 gpu conv samp 35
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf34 1.5802 1.0000 46.3079 153.6921
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf35 1.3996 1.0000 47.8630 152.1370
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf36 1.5422 1.0000 46.2722 153.7278
-1 gpu conv samp 32
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf37 1.2735 1.0000 50.6836 149.3164
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf38 1.5820 1.0000 45.7747 154.2253
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf39 1.3270 1.0000 47.8583 152.1417
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 36
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf40 1.3304 1.0000 48.1907 151.8093
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 36
-10 gpu reduce fp32 44
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf41 1.4680 1.0000 46.8870 153.130
-1 gpu conv samp 35
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf42 1.4071 1.0000 48.4561 151.5439
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 29
-10 gpu reduce fp32 1
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf43 1.4344 1.0000 47.5974 152.4026
-1 gpu conv fp16 1
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 44
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf44 1.4222 1.0000 47.0943 152.9057
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf45 1.5907 1.0000 45.3727 154.6273
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 f6
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf46 1.5916 1.0000 46.1524 153.8476
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 f6
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf47 1.5950 1.0000 45.3702 154.6298
-1 gpu conv samp 32
-2 gpu reduce fp32 42
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 f6
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 f6
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf48 1.5197 1.0000 46.0872 153.918
-1 gpu conv perf 23
-2 gpu reduce fp32 f6
-3 gpu reduce fp32 f6
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce fp32 44
-11 gpu reduce fp32 f6
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf49 1.4471 1.0000 47.0337 152.9663
-1 gpu conv perf 24
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 36
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf50 1.5777 1.0000 45.4910 154.5090
-1 gpu conv samp 32
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 f6
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/autotuner_data/tuner_confs_30.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/autotuner_data/tuner_confs_30.txt
deleted file mode 100644
index c2f6e37f16e6e8894a4125a972e663bb343a87ed..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/autotuner_data/tuner_confs_30.txt
+++ /dev/null
@@ -1,1020 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu conv fp32 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp32 1
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf1 1.5173 1.0000 46.5994 153.4006
-1 gpu conv perf 24
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf2 1.5396 1.0000 45.2507 154.7493
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf3 1.3442 1.0000 50.5525 149.4475
-1 gpu conv fp16 1
-2 gpu reduce fp32 46
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf4 1.4819 1.0000 46.3713 153.6287
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 42
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf5 1.5964 1.0000 44.6798 155.3202
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf6 1.5927 1.0000 45.4965 154.5035
-1 gpu conv perf 26
-2 gpu reduce fp32 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 42
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf7 1.4097 1.0000 47.8913 152.1087
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 42
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf8 1.5964 1.0000 44.7281 155.2719
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf9 1.51 1.0000 46.0555 153.9445
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 35
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf10 1.4832 1.0000 47.0986 152.9014
-1 gpu conv perf 24
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf11 1.5959 1.0000 45.0248 154.9752
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf12 1.2985 1.0000 50.9488 149.051
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf13 1.5215 1.0000 46.0964 153.9036
-1 gpu conv perf 24
-2 gpu reduce fp32 46
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 44
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf14 1.5414 1.0000 45.3425 154.6575
-1 gpu conv perf 22
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf15 1.4864 1.0000 47.1646 152.8354
-1 gpu conv perf 24
-2 gpu reduce fp32 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf16 1.5295 1.0000 45.6257 154.3743
-1 gpu conv perf 24
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf17 1.5491 1.0000 45.3903 154.6097
-1 gpu conv perf 26
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf18 1.5941 1.0000 45.1787 154.8213
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf19 1.5495 1.0000 45.2594 154.7406
-1 gpu conv perf 26
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf20 1.4560 1.0000 46.5437 153.4563
-1 gpu conv perf 23
-2 gpu reduce fp32 1
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf21 1.5261 1.0000 45.9166 154.0834
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 28
-10 gpu reduce fp32 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf22 1.5185 1.0000 46.3647 153.6353
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 42
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf23 1.3948 1.0000 49.6046 150.3954
-1 gpu conv fp16 1
-2 gpu reduce fp32 46
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf24 1.5395 1.0000 45.4391 154.5609
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 44
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf25 1.4334 1.0000 47.2922 152.7078
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 46
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf26 1.4659 1.0000 46.2526 153.7474
-1 gpu conv samp 35
-2 gpu reduce fp32 46
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 27
-10 gpu reduce fp32 1
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf27 1.4652 1.0000 46.5613 153.4387
-1 gpu conv samp 35
-2 gpu reduce fp32 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 27
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf28 1.4614 1.0000 46.3633 153.6367
-1 gpu conv perf 28
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 1
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf29 1.5963 1.0000 44.9079 155.0921
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 44
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf30 1.5865 1.0000 45.6696 154.3304
-1 gpu conv perf 26
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf31 1.5924 1.0000 45.0895 154.9105
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 46
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf32 1.5215 1.0000 46.0251 153.9749
-1 gpu conv perf 29
-2 gpu reduce fp32 46
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 44
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf33 1.4619 1.0000 46.2391 153.7609
-1 gpu conv perf 28
-2 gpu reduce fp32 46
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce fp32 46
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf34 1.4461 1.0000 47.1446 152.8554
-1 gpu conv samp 35
-2 gpu reduce fp32 46
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce fp32 46
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf35 1.5070 1.0000 45.618 154.3882
-1 gpu conv samp 32
-2 gpu reduce fp32 46
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 34
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf36 1.5893 1.0000 45.3846 154.6154
-1 gpu conv perf 26
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf37 1.4357 1.0000 47.5905 152.4095
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 42
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf38 1.4245 1.0000 47.9887 152.013
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 35
-10 gpu reduce fp32 46
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf39 1.4355 1.0000 47.3299 152.6701
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 42
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf40 1.5504 1.0000 45.4929 154.5071
-1 gpu conv samp 32
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce fp32 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf41 1.5239 1.0000 46.4973 153.5027
-1 gpu conv perf 24
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 46
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf42 1.5910 1.0000 45.146 154.8854
-1 gpu conv samp 31
-2 gpu reduce fp32 46
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 46
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf43 1.5546 1.0000 45.0721 154.9279
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 46
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 42
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf44 1.5052 1.0000 45.9996 154.0004
-1 gpu conv samp 34
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf45 1.5231 1.0000 45.8745 154.155
-1 gpu conv perf 29
-2 gpu reduce fp32 44
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf46 1.461 1.0000 46.6356 153.3644
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 46
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf47 1.5858 1.0000 46.0509 153.9491
-1 gpu conv perf 21
-2 gpu reduce fp32 46
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf48 1.4332 1.0000 48.2637 151.7363
-1 gpu conv fp16 1
-2 gpu reduce fp32 44
-3 gpu reduce fp32 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 46
-11 gpu reduce fp32 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 46
-14 gpu reduce fp32 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf49 1.5907 1.0000 45.2134 154.7866
-1 gpu conv samp 31
-2 gpu reduce fp32 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 42
-6 gpu reduce fp32 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 1
-11 gpu reduce fp32 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 44
-14 gpu reduce fp32 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf50 1.4107 1.0000 48.4621 151.5379
-1 gpu conv samp 35
-2 gpu reduce fp32 46
-3 gpu reduce fp32 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/promise_flags b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/promise_flags
deleted file mode 100644
index 4926d750802949bb084400efb5b0ae39a2003d57..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/promise_flags
+++ /dev/null
@@ -1,5 +0,0 @@
-7
-7
-7
-7
-7
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/quant_ranges.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/quant_ranges.txt
deleted file mode 100644
index ad8fa364abaa7bb6f17efd3179d4a9f873cf2547..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/quant_ranges.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/quant_ranges_rt.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/quant_ranges_rt.txt
deleted file mode 100644
index 535066863d6100c48a757af3a4c6a92a7458ec65..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/quant_ranges_rt.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-1 0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-2 0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-3 0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-4 0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-5 0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
-6 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/soc_data/tuner_confs_25.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/soc_data/tuner_confs_25.txt
deleted file mode 100644
index c16cdd009fd0d5082ba96bdeba380ad428015cd0..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/soc_data/tuner_confs_25.txt
+++ /dev/null
@@ -1,1021 +0,0 @@
-57268.607800000005
-+++++
-conf0 1 1 200.0 0.0
-1 gpu conv fp32 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp32 1
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf1 2.612975129885633 2.6377615608365796 45.9782 154.0218
-1 gpu conv perf 23
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf2 2.435596493548905 2.3249068648765068 47.4863 152.5137
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf3 1.7485446431596041 1.8469053118349597 46.7024 153.2976
-1 gpu conv samp 35
-2 gpu reduce red_samp 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf4 1.7650928158264012 1.8540189331578711 46.5771 153.4229
-1 gpu conv samp 32
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf5 2.424329266884608 2.3287196212931085 45.4949 154.5051
-1 gpu conv samp 32
-2 gpu reduce red_samp 42
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf6 2.5328957964601613 2.449818441702798 45.6881 154.319
-1 gpu conv perf 21
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf7 2.1726140130060383 2.167101747317036 47.8623 152.1377
-1 gpu conv fp16 1
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf8 1.6341476728549378 1.6105548719207432 46.1501 153.8499
-1 gpu conv samp 32
-2 gpu reduce red_samp 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 33
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf9 2.267404242255327 2.158139895853351 46.6856 153.3144
-1 gpu conv samp 35
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf10 2.160034718602642 2.1532261294706068 48.4016 151.5984
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf11 1.7626793241630228 1.864878140608174 45.8831 154.169
-1 gpu conv samp 35
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf12 1.8205542224121374 1.874902423405314 45.7022 154.2978
-1 gpu conv perf 21
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf13 2.36342045527526 2.324017483034245 46.4198 153.5802
-1 gpu conv samp 31
-2 gpu reduce red_samp 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf14 1.7917690598513756 1.6075067474749098 51.501 148.4988
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf15 2.53063461582506 2.5434241841337775 45.7376 154.2624
-1 gpu conv samp 32
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf16 1.6423800388875263 1.735270229289105 47.1001 152.8999
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf17 2.51785819277533 2.524385983109205 45.6305 154.3695
-1 gpu conv samp 31
-2 gpu reduce red_samp 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf18 2.0956906002485933 1.8658727723460775 48.391 151.6088
-1 gpu conv perf 24
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf19 2.3923493106731337 2.3776374439340784 46.1997 153.8003
-1 gpu conv samp 36
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf20 1.8301891520425262 1.9572906943894952 45.9064 154.0936
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf21 2.525595954033636 2.5400184288080907 45.4947 154.5053
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf22 2.3693803593717075 2.3304405536949875 46.3973 153.6027
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf23 1.7962799289443767 1.8976647523028618 47.1609 152.8391
-1 gpu conv perf 25
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 29
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf24 2.225256655323747 2.1775340979760576 47.605 152.395
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 29
-10 gpu reduce red_samp 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf25 2.52566004428855 2.5366094280507574 45.4865 154.5135
-1 gpu conv samp 31
-2 gpu reduce red_samp 42
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf26 2.6057821313248843 2.6382020518681335 45.7529 154.2471
-1 gpu conv perf 28
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf27 1.754271117628515 1.8552854598389168 47.1608 152.8392
-1 gpu conv samp 35
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf28 2.3537899061601673 2.2330498118465747 45.6762 154.3238
-1 gpu conv samp 31
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf29 1.6381079229354658 1.7294327203948543 48.0457 151.9543
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf30 2.445478710230263 2.3355494082637507 45.9532 154.0468
-1 gpu conv perf 24
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf31 2.2399355931089806 2.1163320368612926 45.8968 154.1032
-1 gpu conv samp 35
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf32 2.5384252909224894 2.5535278593582103 45.359 154.641
-1 gpu conv samp 31
-2 gpu reduce red_samp 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf33 2.2525453151686636 2.1449256180739487 46.8296 153.1704
-1 gpu conv samp 35
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf34 2.3985206978626037 2.299271378119305 46.3079 153.6921
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf35 2.1662911784156234 2.160152355766743 47.863 152.137
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf36 2.4124901954659546 2.317040480253678 46.2722 153.7278
-1 gpu conv samp 32
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf37 1.7918206302583646 1.6076862656788198 50.6836 149.3164
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf38 2.5244745113763445 2.5375574966140206 45.7747 154.2253
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf39 1.467604847821412 1.4427624775213617 47.8583 152.1417
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 36
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf40 1.87229166973778 1.726019539422995 48.1907 151.8093
-1 gpu conv fp16 1
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 36
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf41 1.7487959566243845 1.8483222588427728 46.887 153.13
-1 gpu conv samp 35
-2 gpu reduce red_samp 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf42 1.6736220538425217 1.7414219543623024 48.4561 151.5439
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 29
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf43 2.1720980108734675 2.167035914877195 47.5974 152.4026
-1 gpu conv fp16 1
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf44 2.4504181245768093 2.424262919212702 47.0943 152.9057
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf45 2.365030956022025 2.2466376740563736 45.3727 154.6273
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf46 2.4076329866568655 2.3104124693725163 46.1524 153.8476
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf47 2.437080621348533 2.3414699346409362 45.3702 154.6298
-1 gpu conv samp 32
-2 gpu reduce red_samp 42
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf48 2.6135363894045747 2.640652760708004 46.0872 153.918
-1 gpu conv perf 23
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf49 1.6693419091924484 1.653543914868148 47.0337 152.9663
-1 gpu conv perf 24
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 36
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf50 1.8410671746999703 1.9708524125021116 45.491 154.509
-1 gpu conv samp 32
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/soc_data/tuner_confs_30.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/soc_data/tuner_confs_30.txt
deleted file mode 100644
index 4cd301de28e2137d1a31aeb5ed3285213918ae04..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/soc_data/tuner_confs_30.txt
+++ /dev/null
@@ -1,1021 +0,0 @@
-57268.607800000005
-+++++
-conf0 1 1 200.0 0.0
-1 gpu conv fp32 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp32 1
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf1 1.886917926774853 2.031003434351884 46.5994 153.4006
-1 gpu conv perf 24
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf2 1.7456045032241023 1.7801943018007549 45.2507 154.7493
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf3 2.035181991254191 1.994797045528838 50.5525 149.4475
-1 gpu conv fp16 1
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce red_samp 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf4 2.4419275117921173 2.3342430498260613 46.3713 153.6287
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf5 2.376132239807402 2.2565537893355185 44.6798 155.3202
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf6 2.5688862817321354 2.483524143134267 45.4965 154.5035
-1 gpu conv perf 26
-2 gpu reduce red_samp 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf7 2.2255293149110575 2.171511202769374 47.8913 152.1087
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf8 2.3760579559807864 2.2567416235290017 44.7281 155.2719
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf9 2.145596317448284 1.973878580732856 46.0555 153.9445
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 35
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf10 2.480045156886937 2.3893201348782602 47.0986 152.9014
-1 gpu conv perf 24
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf11 2.3760665425002383 2.258285193924957 45.0248 154.9752
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf12 1.4187592838462162 1.3593996260168393 50.9488 149.051
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp16 1
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf13 2.605454219484641 2.632222398923382 46.0964 153.9036
-1 gpu conv perf 24
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf14 1.91836450770423 2.073922444442585 45.3425 154.6575
-1 gpu conv perf 22
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf15 2.4838407118771193 2.3940966570109103 47.1646 152.8354
-1 gpu conv perf 24
-2 gpu reduce red_samp 46
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf16 2.4587756217345835 2.347619142052639 45.6257 154.3743
-1 gpu conv perf 24
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf17 1.8576140633009626 1.9277658588157833 45.3903 154.6097
-1 gpu conv perf 26
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf18 2.3741074484223086 2.2557501006150247 45.1787 154.8213
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf19 1.8573305035581182 1.926224539998911 45.2594 154.7406
-1 gpu conv perf 26
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf20 2.443475789415361 2.4157992280669114 46.5437 153.4563
-1 gpu conv perf 23
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf21 2.373673091427908 2.3446423673851524 45.9166 154.0834
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 28
-10 gpu reduce red_samp 44
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf22 2.4504703299428634 2.342645623433509 46.3647 153.6353
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf23 1.5859678780110424 1.6183148792491933 49.6046 150.3954
-1 gpu conv fp16 1
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf24 2.3493816836651935 2.230478174783121 45.4391 154.5609
-1 gpu conv samp 31
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf25 2.176142965466808 2.1708003259188704 47.2922 152.7078
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf26 1.7567254780936332 1.855986372260687 46.2526 153.7474
-1 gpu conv samp 35
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 27
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf27 1.7530720886307698 1.8543199208442147 46.5613 153.4387
-1 gpu conv samp 35
-2 gpu reduce red_samp 42
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 27
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf28 1.803131791445948 1.905838770472839 46.3633 153.6367
-1 gpu conv perf 28
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf29 2.5172393240370763 2.52603750716311 44.9079 155.0921
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf30 1.861331398481007 1.9315868629776745 45.6696 154.3304
-1 gpu conv perf 26
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf31 2.3771358568119014 2.258184755916675 45.0895 154.9105
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf32 2.6128135115388775 2.641915097061659 46.0251 153.9749
-1 gpu conv perf 29
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce red_samp 44
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf33 2.4603806701402973 2.4329070438652187 46.2391 153.7609
-1 gpu conv perf 28
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf34 2.2416802089310837 2.180651711604129 47.1446 152.8554
-1 gpu conv samp 35
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 25
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf35 1.6328018635070136 1.6181207101852786 45.618 154.3882
-1 gpu conv samp 32
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 34
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf36 1.8625535657750667 1.9334932467244081 45.3846 154.6154
-1 gpu conv perf 26
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf37 2.0838796163513114 1.998917639104764 47.5905 152.4095
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf38 2.0283040471858103 1.858964441276641 47.9887 152.013
-1 gpu conv samp 35
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 35
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf39 2.175132107829986 2.1721673418387573 47.3299 152.6701
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 26
-10 gpu reduce red_samp 42
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf40 2.53969142837164 2.5573131737437755 45.4929 154.5071
-1 gpu conv samp 32
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 22
-10 gpu reduce red_samp 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf41 2.5025802854875954 2.4116561629783257 46.4973 153.5027
-1 gpu conv perf 24
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf42 2.5204436206560303 2.5259648040069114 45.146 154.8854
-1 gpu conv samp 31
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 21
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf43 2.405140783090627 2.3035908134147434 45.0721 154.9279
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 42
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 42
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
-+++++
-conf44 1.6977770897303235 1.7305708523826309 45.9996 154.0004
-1 gpu conv samp 34
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 42
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf45 1.8279014979910009 1.8925897573445607 45.8745 154.155
-1 gpu conv perf 29
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 42
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf46 2.4666409093764337 2.4419852851798387 46.6356 153.3644
-1 gpu conv perf 29
-2 gpu reduce fp32 1
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 46
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 42
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf47 1.8468405950358693 1.9176883393619115 46.0509 153.9491
-1 gpu conv perf 21
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 44
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf48 2.0866043850457783 2.001246104150543 48.2637 151.7363
-1 gpu conv fp16 1
-2 gpu reduce red_samp 44
-3 gpu reduce red_samp 44
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 32
-10 gpu reduce red_samp 46
-11 gpu reduce red_samp 44
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 46
-14 gpu reduce red_samp 44
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf49 1.7548903966012046 1.7906532154451158 45.2134 154.7866
-1 gpu conv samp 31
-2 gpu reduce red_samp 44
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 42
-6 gpu reduce red_samp 44
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv samp 31
-10 gpu reduce fp32 1
-11 gpu reduce red_samp 46
-12 gpu map2 fp32 1
-13 gpu reduce red_samp 44
-14 gpu reduce red_samp 46
-15 gpu map2 fp32 1
-16 gpu map2 fp16 1
-17 gpu map2 fp32 1
------
-+++++
-conf50 2.2184928366254915 2.16307006194596 48.4621 151.5379
-1 gpu conv samp 35
-2 gpu reduce red_samp 46
-3 gpu reduce red_samp 46
-4 gpu map2 fp32 1
-5 gpu reduce red_samp 46
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv perf 24
-10 gpu reduce red_samp 42
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/tuner_confs.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/tuner_confs.txt
deleted file mode 100644
index 4cd90c098b42e33b2af46593ac760775c5c92e85..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/data/tuner_confs.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-+++++
-conf1 1.5 90 1.0 2.0
-1 gpu conv fp32 1
-2 gpu reduce fp32 1
-3 gpu reduce fp32 1
-4 gpu map2 fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu map2 fp32 1
-8 gpu map2 fp32 1
-9 gpu conv fp32 1
-10 gpu reduce fp32 1
-11 gpu reduce fp32 1
-12 gpu map2 fp32 1
-13 gpu reduce fp32 1
-14 gpu reduce fp32 1
-15 gpu map2 fp32 1
-16 gpu map2 fp32 1
-17 gpu map2 fp32 1
------
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/src/blend_direct_call.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/src/blend_direct_call.cpp
deleted file mode 100644
index 373451812f1589e80865040e78a9b18eea55ccbf..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/blending/src/blend_direct_call.cpp
+++ /dev/null
@@ -1,127 +0,0 @@
-#include "tensor_runtime.h"
-#include "visc.h"
-#include <iostream>
-#include <cassert>
-
-const size_t n_channels = 3;
-
-Tensor *gaussianFilter_(float div) {
- std::vector<float> gauss_data = {1, 4, 6, 4, 1, 4, 16, 24, 16,
- 4, 6, 24, 36, 24, 6, 4, 16, 24,
- 16, 4, 1, 4, 6, 4, 1};
- for (float &f : gauss_data)
- f /= div;
- return (Tensor *)createFilterFromData(
- CUDNN_DATA_FLOAT, gauss_data.data(), 5, 5, 1);
-}
-
-Tensor *gaussianFilter() { return gaussianFilter_(16.0); }
-
-void *normalize(size_t &id, void *image) {
- auto *max_1D = wrapper_tensorReduce(
- std::to_string(id++).c_str(), image, 2, (int)MathOp::Max);
- auto *max = wrapper_tensorReduce(
- std::to_string(id++).c_str(), max_1D, 3, (int)MathOp::Max);
- auto *img_norm = wrapper_tensorMap2(
- std::to_string(id++).c_str(), (int)MathOp::Div, image, max);
- freeTensor(max_1D);
- freeTensor(max);
- return img_norm;
-}
-
-extern std::vector<size_t> sizes(Tensor *t);
-
-void forward_reshape(void *t) {
- auto *tensor = (Tensor *)t;
- std::vector<size_t> sz = sizes(tensor);
- assert(sz[1] == 3);
- sz[0] = sz[0] * sz[1];
- sz[1] = 1;
- reshape(tensor, sz);
-}
-
-void backward_reshape(void *t) {
- auto *tensor = (Tensor *)t;
- std::vector<size_t> sz = sizes(tensor);
- assert(sz[0] % 3 == 0);
- sz[0] = sz[0] / 3;
- sz[1] = 3;
- reshape(tensor, sz);
-}
-
-void *sharpen(size_t &id, void *image) {
- void *gaussian = gaussianFilter();
- forward_reshape(image);
- void *blurred = wrapper_ConvLayer(
- std::to_string(id++).c_str(), image, gaussian, nullptr, 2, 2, 1, 1, 0, 0, -1, 0.0, 0.0);
- backward_reshape(image);
- backward_reshape(blurred);
- void *blurred_norm = normalize(id, blurred);
- void *image_norm = normalize(id, image);
- void *ret = wrapper_tensorMap2(
- std::to_string(id++).c_str(), (int)MathOp::AddWeighted, blurred_norm,
- image_norm);
- freeTensor(gaussian);
- freeTensor(blurred);
- freeTensor(blurred_norm);
- freeTensor(image_norm);
- return ret;
-}
-
-void *main_procedure(void *fg, void *bg) {
- size_t id = 1;
- void *g_bg = sharpen(id, bg);
- void *g_fg = sharpen(id, fg);
- void *ret = wrapper_tensorMap2(
- std::to_string(id++).c_str(), (int)MathOp::Blend2, g_bg, g_fg);
- std::cout << "**********************" << id << '\n';
- freeTensor(g_bg);
- freeTensor(g_fg);
- return ret;
-}
-
-extern void llvm_hpvm_initializeRuntimeController(
- const char *ConfigFile, const char *QRangeFile);
-
-extern void llvm_hpvm_clearRuntimeController();
-
-extern void llvm_hpvm_initTensorRt(int gpuid);
-
-extern void llvm_hpvm_nextIter();
-
-const size_t batch_size = 250;
-
-int main(int argc, char *argv[]) {
- if (argc < 4)
- return 0;
- llvm_hpvm_initTensorRt(0);
- llvm_hpvm_initializeRuntimeController("data/tuner_confs.txt", "");
-
- startMemTracking();
- startProfiling();
- size_t bstart = 0;
- while (true) {
- auto *background = readDataSet(argv[1], bstart, batch_size, n_channels),
- *foreground = readDataSet(argv[2], bstart, batch_size, n_channels);
- if (!background || !foreground)
- break;
-
- auto *result = main_procedure(foreground, background);
-
- if (argc == 4) {
- saveDataSet(argv[3], (Tensor *)result, bstart);
- llvm_hpvm_imgInvokeRtControl(result, nullptr, bstart, bstart + batch_size);
- }
- else {
- saveDataSet(argv[3], (Tensor *)result, bstart, 10);
- auto *gold_output = readDataSet(argv[4], bstart, batch_size, n_channels);
- llvm_hpvm_imgInvokeRtControl(result, gold_output, bstart, bstart + batch_size);
- }
-
- bstart += batch_size;
- freeBatchMemory();
- clearTensorMap();
- }
- stopProfiling();
- llvm_hpvm_clearRuntimeController();
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/Makefile
deleted file mode 100644
index a4693e8a039a62cdcf89609d2e6bdf86c2eff8e5..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/Makefile
+++ /dev/null
@@ -1,67 +0,0 @@
-# NOTE: $LLVM_SRC_ROOT and $CUDA_TOOLKIT_ROOT_DIR have to be set
-# HPVM_BUILD_DIR can be optionally set
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-HPVM_BUILD_DIR ?= $(LLVM_SRC_ROOT)/../build
-
-CCLANG ?= $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-# NOTE: Change to the name of your benchmark
-APP = canny
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-CUSTOM_LIB_PATHS = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a \
- $(LLVM_SRC_ROOT)/projects/gpu_profiler/lib/libgpu_profiler.a \
- $(LLVM_SRC_ROOT)/projects/soc_simulator/lib/libpromise_profiler.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_TOOLKIT_ROOT_DIR)/include -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -L $(CUDA_TOOLKIT_ROOT_DIR)/lib64 -lstdc++fs -lpthread -lcudart -lcurand -lcudnn -lcublas -lcufft
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-CONF_FILE_PATH=$(realpath data/tuner_confs.txt)
-# NOTE: Needs proper handling in the WRAPPER backend because Quant range not needed for IMAGE Benchmarks
-WRAPPER_API_QUANT_FILE_PATH=
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_WrapperAPI.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMFuseHPVMTensorNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -hpvm-fuse -dfg2llvm-wrapperapi -quantization-levels-filename=$(WRAPPER_API_QUANT_FILE_PATH) -configuration-inputs-filename=$(CONF_FILE_PATH) -dfg2llvm-x86 -clearDFG
-
-
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc direct
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CCLANG) $(CC_FLAGS) -emit-llvm src/$(APP).cpp -S -o $(BUILD_DIR)/$(APP).ll
-
-direct: $(SRC_DIR)/$(APP)_direct_call.cpp
- $(CCLANG) $(CC_FLAGS) src/$(APP)_direct_call.cpp $(CUSTOM_LIB_PATHS) -o $(BUILD_DIR)/$(APP)_direct_call $(LINKER_FLAGS)
-
-autotuner: $(SRC_DIR)/$(APP)_autotuner.cpp
- $(CCLANG) $(CC_FLAGS) src/$(APP)_autotuner.cpp $(CUSTOM_LIB_PATHS) -o $(BUILD_DIR)/$(APP)_autotuner $(LINKER_FLAGS)
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP).ll -S -o $(BUILD_DIR)/$(APP).visc.ll
- $(OPT) $(VISC_OPTFLAGS) $(BUILD_DIR)/$(APP).visc.ll -o $(BUILD_DIR)/$(APP)_wrapper.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_wrapper.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_wrapper_linked.bc
- $(CCLANG) $(BUILD_DIR)/$(APP)_wrapper_linked.bc $(CUSTOM_LIB_PATHS) $(PROMISE_PROFILER_LIB_PATH) -o $(BUILD_DIR)/$(APP)_final $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25.txt
deleted file mode 100644
index 25f4cbc44a2e8de7f734d0b7764be8a2b806c229..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25.txt
+++ /dev/null
@@ -1,552 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp32 11
-4 gpu conv fp32 11
-5 gpu conv fp32 11
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf1 2.0831 1.0000 34.5229 165.4771
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf2 2.0764 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf3 1.9357 1.0000 40.0291 159.9709
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf4 2.0831 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf5 1.9009 1.0000 38.2530 161.7470
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf6 2.0410 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf7 2.0814 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf8 1.9715 1.0000 40.1928 159.8072
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf9 2.0410 1.0000 38.6431 161.3569
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf10 1.9011 1.0000 38.2697 161.7303
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 29
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf11 2.0315 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf12 1.8994 1.0000 37.8973 162.1027
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf13 2.0793 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf14 1.8994 1.0000 38.5623 161.4377
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf15 2.0824 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf16 2.0397 1.0000 37.7069 162.2931
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf17 2.0842 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf18 1.8994 1.0000 38.9044 161.0956
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 24
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf19 2.0380 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf20 1.8985 1.0000 37.8973 162.1027
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf21 2.0407 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf22 1.9689 1.0000 40.2171 159.7829
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf23 1.9987 1.0000 37.4580 162.5420
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf24 1.8700 1.0000 45.9385 154.0615
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf25 1.7188 1.0000 46.7352 153.2648
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp16 12
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf26 2.0400 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf27 2.0315 1.0000 40.0403 159.9597
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf28 2.0831 1.0000 35.5821 164.4179
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf29 2.1142 1.0000 37.2159 162.7841
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf30 1.6422 1.0000 46.2281 153.7719
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp16 12
-4 gpu conv perf 28
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf31 2.0845 1.0000 34.8408 165.1592
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf32 2.0410 1.0000 37.7069 162.2931
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf33 2.0842 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf34 2.1125 1.0000 37.1189 162.8811
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf35 2.0845 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf36 2.0837 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf37 2.1124 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf38 1.8994 1.0000 38.4384 161.5616
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv perf 24
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf39 1.9717 1.0000 39.0153 160.9847
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf40 2.0845 1.0000 34.8448 165.1552
-1 gpu reduce red_samp 45
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf41 2.1145 1.0000 37.1189 162.8811
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf42 2.1134 1.0000 37.1189 162.8811
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf43 2.0335 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf44 1.9357 1.0000 40.0384 159.9616
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 28
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf45 2.0402 1.0000 37.2027 162.7973
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25_ported.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25_ported.txt
deleted file mode 100644
index ac76f9ce4695ea8ee37a7e28c36950041b6e2b18..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25_ported.txt
+++ /dev/null
@@ -1,552 +0,0 @@
-+++++
-conf0 1.0000 1.0000 10.0000 0.0000
-1 gpu reduce fp32 1
-2 gpu map1 fp32 1
-3 gpu conv fp32 1
-4 gpu conv fp32 1
-5 gpu conv fp32 1
-6 gpu map2 fp32 1
-7 gpu reduce fp32 1
-8 gpu reduce fp32 1
-9 gpu map2 fp32 1
------
-+++++
-conf1 2.1894 1.0000 34.5229 165.4771
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf2 2.1851 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf3 2.0462 1.0000 40.0291 159.9709
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf4 2.1894 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf5 2.0074 1.0000 38.2530 161.7470
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf6 2.1643 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf7 2.1884 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf8 2.0862 1.0000 40.1928 159.8072
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf9 2.1643 1.0000 38.6431 161.3569
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf10 2.0077 1.0000 38.2697 161.7303
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 29
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf11 2.1572 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf12 2.0064 1.0000 37.8973 162.1027
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf13 2.1868 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf14 2.0064 1.0000 38.5623 161.4377
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf15 2.1897 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf16 2.1626 1.0000 37.7069 162.2931
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf17 2.1909 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf18 2.0064 1.0000 38.9044 161.0956
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf19 2.1615 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf20 2.0052 1.0000 37.8973 162.1027
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf21 2.1640 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf22 2.0839 1.0000 40.2171 159.7829
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf23 2.0922 1.0000 37.4580 162.541
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf24 1.9736 1.0000 45.9385 154.0615
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf25 1.8053 1.0000 46.7352 153.2648
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf26 2.1629 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf27 2.1572 1.0000 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf28 2.1894 1.0000 35.5821 164.4179
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf29 2.2185 1.0000 37.2159 162.7841
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf30 1.7214 1.0000 46.2281 153.7719
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv perf 28
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf31 2.1913 1.0000 34.8408 165.1592
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf32 2.1643 1.0000 37.7069 162.2931
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf33 2.1909 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf34 2.2166 1.0000 37.189 162.881
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf35 2.1913 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf36 2.1905 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf37 2.2173 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf38 2.0064 1.0000 38.4384 161.5616
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf39 2.0866 1.0000 39.0153 160.9847
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf40 2.1913 1.0000 34.8448 165.1552
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf41 2.2189 1.0000 37.189 162.881
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf42 2.2174 1.0000 37.189 162.881
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf43 2.1587 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf44 2.0462 1.0000 40.0384 159.9616
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 28
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf45 2.1636 1.0000 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25_remap.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25_remap.txt
deleted file mode 100644
index 49e0c2f973a37cd3ee6f1ad6da78095d363dd19e..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_25_remap.txt
+++ /dev/null
@@ -1,552 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp32 11
-4 gpu conv fp32 11
-5 gpu conv fp32 11
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf1 2.1894 1.0000 34.5229 165.4771
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf2 2.1851 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf3 2.0462 1.0000 40.0291 159.9709
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf4 2.1894 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf5 2.0074 1.0000 38.2530 161.7470
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf6 2.1643 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf7 2.1884 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf8 2.0862 1.0000 40.1928 159.8072
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf9 2.1643 1.0000 38.6431 161.3569
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf10 2.0077 1.0000 38.2697 161.7303
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 29
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf11 2.1572 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf12 2.0064 1.0000 37.8973 162.1027
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf13 2.1868 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf14 2.0064 1.0000 38.5623 161.4377
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf15 2.1897 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf16 2.1626 1.0000 37.7069 162.2931
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf17 2.1909 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf18 2.0064 1.0000 38.9044 161.0956
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 24
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf19 2.1615 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf20 2.0052 1.0000 37.8973 162.1027
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf21 2.1640 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf22 2.0839 1.0000 40.2171 159.7829
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf23 2.0922 1.0000 37.4580 162.5420
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf24 1.9736 1.0000 45.9385 154.0615
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf25 1.8053 1.0000 46.7352 153.2648
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv fp16 12
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf26 2.1629 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf27 2.1572 1.0000 40.0403 159.9597
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf28 2.1894 1.0000 35.5821 164.4179
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf29 2.2185 1.0000 37.2159 162.7841
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf30 1.7214 1.0000 46.2281 153.7719
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv fp16 12
-4 gpu conv perf 28
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf31 2.1913 1.0000 34.8408 165.1592
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf32 2.1643 1.0000 37.7069 162.2931
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf33 2.1909 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf34 2.2166 1.0000 37.1189 162.8811
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf35 2.1913 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf36 2.1905 1.0000 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf37 2.2173 1.0000 34.4474 165.5526
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf38 2.0064 1.0000 38.4384 161.5616
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv perf 24
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf39 2.0866 1.0000 39.0153 160.9847
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf40 2.1913 1.0000 34.8448 165.1552
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf41 2.2189 1.0000 37.1189 162.8811
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf42 2.2174 1.0000 37.1189 162.8811
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf43 2.1587 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf44 2.0462 1.0000 40.0384 159.9616
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 28
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf45 2.1636 1.0000 37.2027 162.7973
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30.txt
deleted file mode 100644
index 5ec64f13962b157d78883f3da576b2f0837a6929..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30.txt
+++ /dev/null
@@ -1,504 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp32 11
-4 gpu conv fp32 11
-5 gpu conv fp32 11
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf1 1.9715 1.0000 40.2171 159.7829
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf2 2.0410 1.0000 37.7402 162.2598
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf3 1.7142 1.0000 46.6616 153.3384
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp16 12
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf4 1.9717 1.0000 40.2171 159.7829
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf5 1.6619 1.0000 49.4408 150.5592
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv fp16 12
-5 gpu conv fp16 12
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf6 1.9349 1.0000 44.6282 155.3718
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf7 1.7782 1.0000 47.2420 152.7580
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv fp16 12
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf8 2.0407 1.0000 40.0403 159.9597
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf9 2.0407 1.0000 37.7402 162.2598
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf10 2.0410 1.0000 38.6705 161.3295
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf11 1.9689 1.0000 40.1628 159.8372
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf12 1.9700 1.0000 40.2682 159.7318
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf13 1.9689 1.0000 40.2164 159.7836
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf14 2.0410 1.0000 40.0366 159.9634
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf15 1.7196 1.0000 46.6616 153.3384
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp16 12
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf16 1.9689 1.0000 40.2682 159.7318
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf17 1.7393 1.0000 47.0637 152.9363
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv fp16 12
-5 gpu conv perf 25
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf18 2.0410 1.0000 38.3011 161.6989
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf19 2.0390 1.0000 40.0403 159.9597
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf20 2.0400 1.0000 40.0403 159.9597
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf21 1.9710 1.0000 40.2164 159.7836
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf22 2.0400 1.0000 38.3011 161.6989
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf23 2.0400 1.0000 40.0366 159.9634
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf24 1.7846 1.0000 46.8674 153.1326
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 30
-5 gpu conv fp16 12
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf25 2.0410 1.0000 40.0403 159.9597
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf26 2.0410 1.0000 38.7613 161.2387
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf27 2.0335 1.0000 37.7069 162.2931
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf28 2.0380 1.0000 40.0403 159.9597
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 45
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf29 1.7190 1.0000 46.6616 153.3384
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp16 12
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf30 2.0400 1.0000 38.7613 161.2387
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 43
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf31 1.9717 1.0000 40.2682 159.7318
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf32 2.0335 1.0000 38.7613 161.2387
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf33 1.9717 1.0000 40.1628 159.8372
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf34 1.7830 1.0000 47.3435 152.6565
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv fp16 12
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf35 1.9717 1.0000 41.9914 158.0086
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf36 1.9710 1.0000 40.1628 159.8372
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 45
-9 gpu map2 fp32 11
------
-+++++
-conf37 1.7196 1.0000 45.2621 154.7379
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp16 12
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf38 1.9715 1.0000 40.2682 159.7318
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf39 2.1061 1.0000 36.1289 163.8711
-1 gpu reduce red_samp 41
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 21
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 43
-9 gpu map2 fp32 11
------
-+++++
-conf40 1.9647 1.0000 40.1628 159.8372
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
-+++++
-conf41 1.9717 1.0000 40.2164 159.7836
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp32 11
-7 gpu reduce red_samp 41
-8 gpu reduce red_samp 41
-9 gpu map2 fp32 11
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30_ported.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30_ported.txt
deleted file mode 100644
index 4236605435ab1a8fb57742748b826d5b3a28d709..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30_ported.txt
+++ /dev/null
@@ -1,504 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu reduce fp32 1
-2 gpu map1 fp32 1
-3 gpu conv fp32 1
-4 gpu conv fp32 1
-5 gpu conv fp32 1
-6 gpu map2 fp32 1
-7 gpu reduce fp32 1
-8 gpu reduce fp32 1
-9 gpu map2 fp32 1
------
-+++++
-conf1 2.0862 1.0000 40.2171 159.7829
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf2 2.1643 1.0000 37.7402 162.2598
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf3 1.8023 1.0000 46.6616 153.3384
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf4 2.0866 1.0000 40.2171 159.7829
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf5 1.7426 1.0000 49.4408 150.5592
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv fp16 1
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf6 2.0455 1.0000 44.6282 155.3718
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf7 1.8733 1.0000 47.2420 152.7580
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf8 2.1640 1.0000 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf9 2.1640 1.0000 37.7402 162.2598
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf10 2.1643 1.0000 38.6705 161.3295
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf11 2.0839 1.0000 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf12 2.0846 1.0000 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf13 2.0840 1.0000 40.2164 159.7836
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf14 2.1643 1.0000 40.0366 159.9634
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf15 1.8063 1.0000 46.6616 153.3384
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf16 2.0840 1.0000 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf17 1.8281 1.0000 47.0637 152.9363
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv fp16 1
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf18 2.1643 1.0000 38.301 161.6989
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf19 2.1628 1.0000 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf20 2.1629 1.0000 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf21 2.0859 1.0000 40.2164 159.7836
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf22 2.1629 1.0000 38.301 161.6989
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf23 2.1629 1.0000 40.0366 159.9634
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf24 1.8781 1.0000 46.8674 153.1326
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 30
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf25 2.1643 1.0000 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf26 2.1643 1.0000 38.7613 161.2387
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf27 2.1587 1.0000 37.7069 162.2931
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf28 2.1615 1.0000 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf29 1.8057 1.0000 46.6616 153.3384
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf30 2.1629 1.0000 38.7613 161.2387
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf31 2.0866 1.0000 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf32 2.1587 1.0000 38.7613 161.2387
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf33 2.0866 1.0000 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf34 1.8770 1.0000 47.3435 152.6565
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf35 2.0866 1.0000 41.9914 158.0086
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf36 2.0859 1.0000 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 1
------
-+++++
-conf37 1.8063 1.0000 45.2621 154.7379
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf38 2.0862 1.0000 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf39 2.215 1.0000 36.189 163.871
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf40 2.0813 1.0000 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
-+++++
-conf41 2.0866 1.0000 40.2164 159.7836
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30_remap.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30_remap.txt
deleted file mode 100644
index 7f77efaa7b720fd69d0c9d53fa4de519488e7782..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/autotuner_data/tuner_confs_30_remap.txt
+++ /dev/null
@@ -1,504 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu reduce fp32 11
-2 gpu map1 fp32 11
-3 gpu conv fp32 11
-4 gpu conv fp32 11
-5 gpu conv fp32 11
-6 gpu map2 fp32 11
-7 gpu reduce fp32 11
-8 gpu reduce fp32 11
-9 gpu map2 fp32 11
------
-+++++
-conf1 2.0862 1.0000 40.2171 159.7829
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf2 2.1643 1.0000 37.7402 162.2598
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf3 1.8023 1.0000 46.6616 153.3384
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv fp16 12
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf4 2.0866 1.0000 40.2171 159.7829
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf5 1.7426 1.0000 49.4408 150.5592
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv fp16 12
-5 gpu conv fp16 12
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf6 2.0455 1.0000 44.6282 155.3718
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf7 1.8733 1.0000 47.2420 152.7580
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv fp16 12
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf8 2.1640 1.0000 40.0403 159.9597
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf9 2.1640 1.0000 37.7402 162.2598
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf10 2.1643 1.0000 38.6705 161.3295
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf11 2.0839 1.0000 40.1628 159.8372
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf12 2.0846 1.0000 40.2682 159.7318
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf13 2.0840 1.0000 40.2164 159.7836
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf14 2.1643 1.0000 40.0366 159.9634
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf15 1.8063 1.0000 46.6616 153.3384
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv fp16 12
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf16 2.0840 1.0000 40.2682 159.7318
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf17 1.8281 1.0000 47.0637 152.9363
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv fp16 12
-5 gpu conv perf 25
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf18 2.1643 1.0000 38.3011 161.6989
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf19 2.1628 1.0000 40.0403 159.9597
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf20 2.1629 1.0000 40.0403 159.9597
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf21 2.0859 1.0000 40.2164 159.7836
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf22 2.1629 1.0000 38.3011 161.6989
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf23 2.1629 1.0000 40.0366 159.9634
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf24 1.8781 1.0000 46.8674 153.1326
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 30
-5 gpu conv fp16 12
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf25 2.1643 1.0000 40.0403 159.9597
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf26 2.1643 1.0000 38.7613 161.2387
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf27 2.1587 1.0000 37.7069 162.2931
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf28 2.1615 1.0000 40.0403 159.9597
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 46
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf29 1.8057 1.0000 46.6616 153.3384
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv fp16 12
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf30 2.1629 1.0000 38.7613 161.2387
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf31 2.0866 1.0000 40.2682 159.7318
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf32 2.1587 1.0000 38.7613 161.2387
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf33 2.0866 1.0000 40.1628 159.8372
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf34 1.8770 1.0000 47.3435 152.6565
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv fp16 12
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 12
-9 gpu map2 fp16 12
------
-+++++
-conf35 2.0866 1.0000 41.9914 158.0086
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf36 2.0859 1.0000 40.1628 159.8372
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 46
-9 gpu map2 fp16 12
------
-+++++
-conf37 1.8063 1.0000 45.2621 154.7379
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv fp16 12
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf38 2.0862 1.0000 40.2682 159.7318
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf39 2.2125 1.0000 36.1289 163.8711
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 21
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 12
------
-+++++
-conf40 2.0813 1.0000 40.1628 159.8372
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 12
-7 gpu reduce fp16 12
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
-+++++
-conf41 2.0866 1.0000 40.2164 159.7836
-1 gpu reduce fp16 12
-2 gpu map1 fp16 12
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 12
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 42
-9 gpu map2 fp16 12
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/promise_flags b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/promise_flags
deleted file mode 100644
index 4926d750802949bb084400efb5b0ae39a2003d57..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/promise_flags
+++ /dev/null
@@ -1,5 +0,0 @@
-7
-7
-7
-7
-7
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/quant_ranges.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/quant_ranges.txt
deleted file mode 100644
index ad8fa364abaa7bb6f17efd3179d4a9f873cf2547..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/quant_ranges.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/quant_ranges_rt.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/quant_ranges_rt.txt
deleted file mode 100644
index 535066863d6100c48a757af3a4c6a92a7458ec65..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/quant_ranges_rt.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-1 0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-2 0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-3 0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-4 0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-5 0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
-6 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/soc_data/tuner_confs_25_ported.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/soc_data/tuner_confs_25_ported.txt
deleted file mode 100644
index 3e1580f090b188040026aaccb04cd45e0924cdf3..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/soc_data/tuner_confs_25_ported.txt
+++ /dev/null
@@ -1,553 +0,0 @@
-11087.2797
-+++++
-conf0 1 1 10.0 0.0
-1 gpu reduce fp32 1
-2 gpu map1 fp32 1
-3 gpu conv fp32 1
-4 gpu conv fp32 1
-5 gpu conv fp32 1
-6 gpu map2 fp32 1
-7 gpu reduce fp32 1
-8 gpu reduce fp32 1
-9 gpu map2 fp32 1
------
-+++++
-conf1 2.309947917790846 2.3045758635581324 34.5229 165.4771
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf2 2.3095031271137447 2.2809932000089446 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf3 2.367863480726607 2.4273798590956748 40.0291 159.9709
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf4 2.3657272318527456 2.3609353063917107 34.4474 165.5526
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf5 2.7215424892464717 3.008694861629896 38.253 161.747
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf6 2.28591488471379 2.275204474230622 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf7 2.3127090240309576 2.284917673666628 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf8 2.389581562215002 2.4475550229318888 40.1928 159.8072
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf9 2.4165637831200595 2.5048069037382437 38.6431 161.3569
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf10 2.365705627356844 2.3723290679104134 38.2697 161.7303
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 29
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf11 2.279386178658292 2.2655971757928484 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf12 2.7385653885584653 3.0303549678758115 37.8973 162.1027
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf13 2.3127090240309576 2.284917673666628 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf14 2.5028396253244045 2.5828841258038464 38.5623 161.4377
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf15 2.316178315703079 2.2907237705368613 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf16 2.3341639508072456 2.344453508613453 37.7069 162.2931
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf17 2.3162057508431726 2.2907317968821688 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf18 2.3063465970191275 2.2793534149189996 38.9044 161.0956
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf19 2.282535594881254 2.2694766833154927 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf20 2.7337166982308836 3.0202025246874635 37.8973 162.1027
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 29
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf21 2.2859416075926724 2.275212392189663 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf22 2.3397311805957837 2.3935958584385872 40.2171 159.7829
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf23 2.5401499903890494 2.7035720819182414 37.458 162.541
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf24 2.4209276458508238 2.530155856488655 45.9385 154.0615
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf25 1.807263480419983 1.792086866899229 46.7352 153.2648
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf26 2.285752345774828 2.2745622939397503 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf27 2.4026781590102866 2.510357238592847 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf28 2.50593836130276 2.6091104902173528 35.5821 164.4179
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf29 2.601917630862043 2.8159029585430266 37.2159 162.7841
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf30 1.8260615578199806 1.8293264703618586 46.2281 153.7719
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv perf 28
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf31 2.4495783791398305 2.5216373908777148 34.8408 165.1592
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf32 2.334305581715035 2.3451273539975896 37.7069 162.2931
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf33 2.3659013441680785 2.3616271917361504 34.4474 165.5526
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf34 2.672646627923147 2.8994489637508205 37.189 162.881
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf35 2.316178315703079 2.2907237705368613 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf36 2.316178315703079 2.2907237705368613 34.0403 165.9597
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf37 2.366229193149219 2.3629684712854067 34.4474 165.5526
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf38 2.5483217838528773 2.6967006590177585 38.4384 161.5616
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv perf 24
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf39 2.3388688682657905 2.3714811937919915 39.0153 160.9847
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf40 2.450411027459912 2.5236294646181583 34.8448 165.1552
-1 gpu reduce red_samp 46
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf41 2.6728688500917364 2.9004925441803366 37.189 162.881
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf42 2.672646627923147 2.8994489637508205 37.189 162.881
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 26
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf43 2.279386178658292 2.2655971757928484 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf44 2.3665347556573413 2.4250692882584017 40.0384 159.9616
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 28
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf45 2.28591488471379 2.275204474230622 37.127 162.7973
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 31
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/soc_data/tuner_confs_30_ported.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/soc_data/tuner_confs_30_ported.txt
deleted file mode 100644
index 4c5fe2e3eab8bff32a35f629a7ee4cdb1114b93c..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/soc_data/tuner_confs_30_ported.txt
+++ /dev/null
@@ -1,505 +0,0 @@
-11087.2797
-+++++
-conf0 1 1 200.0 0.0
-1 gpu reduce fp32 1
-2 gpu map1 fp32 1
-3 gpu conv fp32 1
-4 gpu conv fp32 1
-5 gpu conv fp32 1
-6 gpu map2 fp32 1
-7 gpu reduce fp32 1
-8 gpu reduce fp32 1
-9 gpu map2 fp32 1
------
-+++++
-conf1 2.339929487316802 2.394315790427995 40.2171 159.7829
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf2 2.2799811395801437 2.289511219137654 37.7402 162.2598
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf3 1.8048386100374785 1.7810691331776216 46.6616 153.3384
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf4 2.3399014872930954 2.3943070217899765 40.2171 159.7829
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf5 1.8301258684480868 1.6717012501120017 49.4408 150.5592
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv fp16 1
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf6 2.4434715885659957 2.6127247037485644 44.6282 155.3718
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf7 2.180088139249199 2.100597155028442 47.242 152.758
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv perf 29
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf8 2.40996306678594 2.522167619316515 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf9 2.280007723904548 2.2895192369880064 37.7402 162.2598
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf10 2.3576196335789708 2.439596900339052 38.6705 161.3295
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 31
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf11 2.3969759690790764 2.454450929481668 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf12 2.332488144150568 2.3863216446255753 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf13 2.3291107126306576 2.3800151243076377 40.2164 159.7836
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf14 2.4091279941520085 2.520168137118327 40.0366 159.9634
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf15 1.808929418487017 1.787001169037626 46.6616 153.3384
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf16 2.3291386017832254 2.380724613943903 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf17 1.9945842117323922 1.9300320437006613 47.0637 152.9363
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv fp16 1
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf18 2.368043015920912 2.4213951384116346 38.301 161.6989
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf19 2.4099333656214665 2.522157889221319 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf20 2.4097527124030838 2.521368761423534 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf21 2.3326294245310426 2.386315240073515 40.2164 159.7836
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf22 2.367868588253075 2.4206677949111173 38.301 161.6989
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf23 2.4089474616533018 2.5193802537343783 40.0366 159.9634
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf24 2.138251181842383 2.062493656209471 46.8674 153.1326
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 30
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf25 2.4099333656214665 2.522157889221319 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf26 2.3684391010779526 2.4204898710514957 38.7613 161.2387
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf27 2.3274979482448632 2.334921792011782 37.7069 162.2931
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv samp 32
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf28 2.4061777549085366 2.5151211383494685 40.0403 159.9597
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 22
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 46
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf29 1.808929418487017 1.787001169037626 46.6616 153.3384
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 32
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf30 2.3682646150569164 2.419763071219725 38.7613 161.2387
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 44
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf31 2.332657398015033 2.3870284914108226 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf32 2.361431220817641 2.4096193623544604 38.7613 161.2387
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 26
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf33 2.3971547116230982 2.4551987195740685 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf34 2.1372619394691483 2.062101419298601 47.3435 152.6565
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 28
-5 gpu conv fp16 1
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf35 2.4846713071425803 2.6381676016919005 41.9914 158.0086
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf36 2.3971547116230982 2.4551987195740685 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf37 1.7797335947117672 1.746110059775473 45.2621 154.7379
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv fp16 1
-4 gpu conv samp 31
-5 gpu conv samp 31
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf38 2.3326852249358114 2.3870372068176513 40.2682 159.7318
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 24
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf39 2.5929875383512524 2.8024140158154105 36.189 163.871
-1 gpu reduce red_samp 42
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv perf 27
-5 gpu conv perf 21
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce red_samp 44
-9 gpu map2 fp16 1
------
-+++++
-conf40 2.389976127786668 2.4440149384499534 40.1628 159.8372
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 32
-4 gpu conv samp 32
-5 gpu conv perf 23
-6 gpu map2 fp16 1
-7 gpu reduce fp16 1
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
-+++++
-conf41 2.3326294245310426 2.386315240073515 40.2164 159.7836
-1 gpu reduce fp16 1
-2 gpu map1 fp16 1
-3 gpu conv samp 31
-4 gpu conv samp 32
-5 gpu conv perf 25
-6 gpu map2 fp16 1
-7 gpu reduce red_samp 42
-8 gpu reduce fp16 1
-9 gpu map2 fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/tuner_confs.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/tuner_confs.txt
deleted file mode 100644
index da5cd1b431aa20325fa1735425cf62a82be97145..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/data/tuner_confs.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-0.0
-+++++
-conf1 1.5 90 1.0 2.0
-1 gpu reduce fp32 1
-2 gpu map1 fp32 1
-3 gpu conv fp32 1
-4 gpu conv fp32 1
-5 gpu conv fp32 1
-6 gpu map2 fp32 1
-7 gpu reduce fp32 1
-8 gpu reduce fp32 1
-9 gpu map2 fp32 1
------
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/src/canny.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/src/canny.cpp
deleted file mode 100644
index 84df96e2458058d4849f0164fc20d9a443700624..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/src/canny.cpp
+++ /dev/null
@@ -1,227 +0,0 @@
-
-#include <cstring>
-#include <fcntl.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/stat.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-#include <unistd.h>
-#include <visc.h>
-
-/* 0. Grayscale */
-
-void var_0_node(void *t1, size_t bytes_t1) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void *r = __visc__tensor_reduce(t1, 1, device::fadd_ptrptr);
- __visc__return(2, r, (size_t)0);
-}
-
-void var_1_node(void *t1, size_t bytes_t1) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void *r = __visc__tensor_map1(device::favg3_ptrptr, t1);
- __visc__return(2, r, (size_t)0);
-}
-
-/* 1. Denoise */
-
-void var_2_node(void *t1, size_t bytes_t1, void *t2, size_t bytes_t2) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t)0);
-}
-
-/* 2. Get edge gradient / direction */
-
-void var_3_node(void *t1, size_t bytes_t1, void *t2, size_t bytes_t2) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t)0);
-}
-
-void var_4_node(void *t1, size_t bytes_t1, void *t2, size_t bytes_t2) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t)0);
-}
-
-void var_5_node(void *t1, size_t bytes_t1, void *t2, size_t bytes_t2) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_map2(device::fhypot_ptrptr, t1, t2);
- __visc__return(2, r, (size_t)0);
-}
-
-/* 3. Normalize grad magnitude */
-
-void var_6_node(void *t1, size_t bytes_t1) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void *r = __visc__tensor_reduce(t1, 2, device::fmax_ptrptr);
- __visc__return(2, r, (size_t)0);
-}
-
-void var_7_node(void *t1, size_t bytes_t1) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void *r = __visc__tensor_reduce(t1, 3, device::fmax_ptrptr);
- __visc__return(2, r, (size_t)0);
-}
-
-void var_8_node(void *t1, size_t bytes_t1, void *t2, size_t bytes_t2) {
- __visc__hint(visc::GPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_map2(device::fdiv_ptrptr, t1, t2);
- __visc__return(2, r, (size_t)0);
-}
-
-void root(
- void *input, size_t input_bytes, void *gaussian, size_t gaussian_bytes,
- void *sobel_x, size_t sobel_x_bytes, void *sobel_y, size_t sobel_y_bytes) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(
- 8, input, input_bytes, gaussian, gaussian_bytes, sobel_x, sobel_x_bytes,
- sobel_y, sobel_y_bytes, 0);
-
- void *var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
-
- void *var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
-
- void *var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
- __visc__bindIn(var_2, 2, 2, 0);
- __visc__bindIn(var_2, 3, 3, 0);
-
- void *var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 4, 2, 0);
- __visc__bindIn(var_3, 5, 3, 0);
-
- void *var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_2, var_4, 1, 0, 0, 0);
- __visc__edge(var_2, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void *var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_3, var_5, 1, 0, 0, 0);
- __visc__edge(var_3, var_5, 1, 1, 1, 0);
- __visc__edge(var_4, var_5, 1, 0, 2, 0);
- __visc__edge(var_4, var_5, 1, 1, 3, 0);
-
- void *var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void *var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
-
- void *var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_5, var_8, 1, 0, 0, 0);
- __visc__edge(var_5, var_8, 1, 1, 1, 0);
- __visc__edge(var_7, var_8, 1, 0, 2, 0);
- __visc__edge(var_7, var_8, 1, 1, 3, 0);
-
- __visc__bindOut(var_8, 0, 0, 0);
- __visc__bindOut(var_8, 1, 1, 0);
-}
-
-struct ret_t {
- void *tensor;
- size_t bytes;
-};
-
-struct __attribute__((__packed__)) RootIn {
- void *input;
- size_t input_bytes;
- void *gaussian;
- size_t gaussian_bytes;
- void *sobel_x;
- size_t sobel_x_bytes;
- void *sobel_y;
- size_t sobel_y_bytes;
- struct ret_t r;
-};
-
-Tensor *gaussianFilter(float sigma, size_t w, size_t h, size_t n_chan) {
- int64_t m = (w - 1) / 2, n = (h - 1) / 2;
- auto *data = new float[w * h];
- float sum = 0.0f;
- for (int64_t i = -m; i <= m; i++)
- for (int64_t j = -n; j <= n; j++) {
- size_t idx = (i + m) * h + (j + n);
- float exponent = -(i * i + j * j) / (2.0 * sigma * sigma);
- data[idx] = exp(exponent);
- sum += data[idx];
- }
- if (sum != 0.0f)
- for (size_t i = 0; i < w * h; i++)
- data[i] /= sum;
- return (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, data, w, h, n_chan);
-}
-
-std::pair<Tensor *, Tensor *> getSobelKernels() {
- std::vector<float> k1({-1, 0, 1, -2, 0, 2, -1, 0, 1});
- std::vector<float> k2({1, 2, 1, 0, 0, 0, -1, -2, -1});
- auto *t1 =
- (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, k1.data(), 3, 3, 1);
- auto *t2 =
- (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, k2.data(), 3, 3, 1);
- return std::make_pair(t1, t2);
-}
-
-int main(int argc, char *argv[]) {
- if (argc < 3)
- return 0;
- Tensor *image = readDataSet(argv[1]);
- Tensor *gaussian = gaussianFilter(1.4, 5, 5, 1);
- Tensor *sobel_x = nullptr, *sobel_y = nullptr;
- std::tie(sobel_x, sobel_y) = getSobelKernels();
-
- __visc__init();
- RootIn *args = static_cast<RootIn *>(malloc(sizeof(RootIn)));
- *args = RootIn{image, 0, gaussian, 0, sobel_x, 0, sobel_y, 0};
-
- void *dfg = __visc__launch(0, root, (void *)args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn *>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- saveDataSet(argv[2], "", (Tensor *)result);
-
- // computeAccuracy2(labels, 10000, result);
- return 0;
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/src/canny_direct_call.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/src/canny_direct_call.cpp
deleted file mode 100644
index 50dc1034dd4c614c72d7e7e180fcc44faad6f293..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/canny_test/src/canny_direct_call.cpp
+++ /dev/null
@@ -1,101 +0,0 @@
-#include "tensor_runtime.h"
-#include "visc.h"
-
-Tensor *gaussianFilter(float sigma, size_t w, size_t h, size_t n_chan) {
- int64_t m = (w - 1) / 2, n = (h - 1) / 2;
- auto *data = new float[w * h];
- float sum = 0.0f;
- for (int64_t i = -m; i <= m; i++)
- for (int64_t j = -n; j <= n; j++) {
- size_t idx = (i + m) * h + (j + n);
- float exponent = -(i * i + j * j) / (2.0 * sigma * sigma);
- data[idx] = exp(exponent);
- sum += data[idx];
- }
- if (sum != 0.0f)
- for (size_t i = 0; i < w * h; i++)
- data[i] /= sum;
- return (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, data, w, h, n_chan);
-}
-
-std::pair<Tensor *, Tensor *> getSobelKernels() {
- std::vector<float> k1({-1, 0, 1, -2, 0, 2, -1, 0, 1});
- std::vector<float> k2({1, 2, 1, 0, 0, 0, -1, -2, -1});
- auto *t1 =
- (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, k1.data(), 3, 3, 1);
- auto *t2 =
- (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, k2.data(), 3, 3, 1);
- return std::make_pair(t1, t2);
-}
-
-void *main_procedure(void *dataset) {
- Tensor *gaussian = gaussianFilter(1.4, 5, 5, 1);
- Tensor *kernel_x, *kernel_y;
- std::tie(kernel_x, kernel_y) = getSobelKernels();
-
- // 0. Grayscale
- auto *summed_image = wrapper_tensorReduce("1", dataset, 1, (int)MathOp::Add);
- auto *grayscale_image =
- wrapper_tensorMap1("2", (int)MathOp::Avg3, summed_image);
- // 1. Denoise
- auto *image2 = wrapper_ConvLayer(
- "3", grayscale_image, gaussian, nullptr, 2, 2, 1, 1, 0, 0, -1, 0.0, 0.0);
- // 2. Get edge gradient / direction
- auto *grad_x = wrapper_ConvLayer(
- "4", image2, kernel_x, nullptr, 1, 1, 1, 1, 0, 0, -1, 0.0, 0.0);
- auto *grad_y = wrapper_ConvLayer(
- "5", image2, kernel_y, nullptr, 1, 1, 1, 1, 0, 0, -1, 0.0, 0.0);
- auto *grad_mag = wrapper_tensorMap2("6", (int)MathOp::Hypot, grad_x, grad_y);
- // 2.5. Normalize grad magnitude
- auto *grad_max_1D = wrapper_tensorReduce("7", grad_mag, 2, (int)MathOp::Max);
- auto *grad_max = wrapper_tensorReduce("8", grad_max_1D, 3, (int)MathOp::Max);
- auto *grad_mag_norm =
- wrapper_tensorMap2("9", (int)MathOp::Div, grad_mag, grad_max);
- return grad_mag_norm;
-}
-
-extern void llvm_hpvm_initializeRuntimeController(
- const char *ConfigFile, const char *QRangeFile);
-
-extern void llvm_hpvm_clearRuntimeController();
-
-extern void llvm_hpvm_initTensorRt(int gpuid);
-
-extern void llvm_hpvm_nextIter();
-
-const size_t batch_size = 500;
-
-int main(int argc, char *argv[]) {
- if (argc < 3)
- return 0;
- llvm_hpvm_initTensorRt(0);
- llvm_hpvm_initializeRuntimeController("data/tuner_confs.txt", "");
-
- size_t bstart = 0;
- startMemTracking();
- startProfiling();
- while (true) {
- Tensor *batch = readDataSet(argv[1], bstart, batch_size);
- if (batch == nullptr)
- break;
-
- auto *result = main_procedure(batch);
- if (argc == 3) {
- saveDataSet(argv[2], (Tensor *)result, bstart);
- llvm_hpvm_imgInvokeRtControl(
- result, nullptr, bstart, bstart + batch_size);
- } else {
- saveDataSet(argv[2], (Tensor *)result, bstart, 10);
- auto *gold_output = readDataSet(argv[3], bstart, batch_size, 1);
- llvm_hpvm_imgInvokeRtControl(
- result, gold_output, bstart, bstart + batch_size);
- }
- bstart += batch_size;
- freeBatchMemory();
- clearTensorMap();
- }
- stopProfiling();
- llvm_hpvm_clearRuntimeController();
-
- // std::vector<float> psnrs = PSNR(result_fp32, result_fp16);
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/Makefile
deleted file mode 100644
index f6a82b3e3d84b98630f45bc1c95961ea6968d4e9..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/Makefile
+++ /dev/null
@@ -1,254 +0,0 @@
-# This Makefile compiles the HPVM-CAVA pilot project.
-# It builds HPVM-related dependencies, then the native camera pipeline ISP code.
-#
-# Paths to some dependencies (e.g., HPVM, LLVM) must exist in Makefile.config,
-# which can be copied from Makefile.config.example for a start.
-
-CONFIG_FILE := Makefile.config
-
-ifeq ($(wildcard $(CONFIG_FILE)),)
- $(error $(CONFIG_FILE) not found. See $(CONFIG_FILE).example)
-endif
-include $(CONFIG_FILE)
-
-# Compiler Flags
-
-DLEVEL ?= 0
-#CAM_CFLAGS?=-O0 \
- #-Wno-psabi \
- #-Wno-unused-label -Wno-unused-but-set-variable \
- #-Wno-maybe-uninitialized -DARCHITECTURE=SMV -DTRANSPOSE_WEIGHTS=1 \
- -DDEBUG_LEVEL=$(DLEVEL)
-LFLAGS += -lm -lrt
-
-# Build dirs
-ifeq ($(VERSION),)
- VERSION = Default
-endif
-SRC_DIR = src/
-CAM_PIPE_SRC_DIR = $(SRC_DIR)
-BUILD_DIR = build/$(TARGET)_$(VERSION)
-CURRENT_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
-
-# Source files for the frontend camera pipeline
-COMMON_SRCS = main.c \
- utility.c
-
-
-CAM_PIPE_SRCS = load_cam_model.c \
- cam_pipe_utility.c \
- dma_interface.c # FIXME: This is a hack until external C++ files can be included in build.
-
-
-# NOTE: We have temporarily removed gem5 and other dependencies for simplicity.
-SRCS = $(COMMON_SRCS) $(CAM_PIPE_SRCS)
-#GEM5_DMA_SRC = gem5/dma_interface.c
-#GEM5_SYS_SRCS = gem5/aladdin_sys_connection.cpp gem5/aladdin_sys_constants.cpp
-#GEM5_UTIL_SRCS = ../../util/m5/m5op_x86.S
-
-# NATIVE_FULL_PATH_SRCS contains all the full path source files for the camera vision pipeline.
-NATIVE_FULL_PATH_SRCS = $(patsubst %, $(SRC_DIR)/%, $(COMMON_SRCS))
-NATIVE_FULL_PATH_SRCS += $(patsubst %, $(CAM_PIPE_SRC_DIR)/%, $(CAM_PIPE_SRCS))
-
-# GEM5_FULL_PATH_SRCS contains all the full path source files for the gem5 files.
-#GEM5_FULL_PATH_SRCS = $(patsubst %, $(ALADDIN_HOME)/%, $(GEM5_DMA_SRC) $(GEM5_SYS_SRCS) $(GEM5_UTIL_SRCS))
-
-#INCLUDES += -I$(ALADDIN_HOME) \
-# -I$(ALADDIN_HOME)/../../include \
-# -I$(ALADDIN_HOME)/gem5
-INCLUDES += -I$(SRC_DIR) \
- -I$(CAM_PIPE_SRC_DIR) \
-
-ifneq ($(CONFUSE_ROOT),)
-INCLUDES += -I$(CONFUSE_ROOT)/include
-LFLAGS += -L$(CONFUSE_ROOT)/lib
-endif
-
-EXE = cava-visc-$(VERSION)-$(TARGET)
-
-CAM_CFLAGS += -mf16c -flax-vector-conversions
-LFLAGS += -pthread
-
-#$(DEBUG): $(NATIVE_FULL_PATH_SRCS) $(GEM5_FULL_PATH_SRCS)
-# @echo Building benchmark for native machine with debug support.
-# #@mkdir -p $(BUILD_DIR)
-# @$(CC) $(CAM_CFLAGS) -ggdb3 $(INCLUDES) -DGEM5 -DDMA_MODE -DDMA_INTERFACE_V3 -o $(DEBUG) $^ $(LFLAGS)
-#
-#clean-native:
-# rm -f $(NATIVE) $(DEBUG)
-
-## BEGIN HPVM MAKEFILE
-LANGUAGE=visc
-SRCDIR_OBJS= load_cam_model.ll cam_pipe_utility.ll dma_interface.ll utility.ll
-OBJS_SRC=src/cam_pipe.c src/pipe_stages.c src/load_cam_model.c src/cam_pipe_utility.c src/dma_interface.c src/utility.c
-VISC_OBJS=main.visc.ll
-APP = $(EXE)
-APP_CUDALDFLAGS=-lm -lstdc++
-APP_CFLAGS= $(INCLUDES) -DDMA_MODE -DDMA_INTERFACE_V3
-APP_CXXFLAGS=-ffast-math -O0 -I/opt/opencv/include
-APP_LDFLAGS=$(LFLAGS)
-OPT_FLAGS = -tti -targetlibinfo -tbaa -scoped-noalias -assumption-cache-tracker -profile-summary-info -forceattrs -inferattrs -ipsccp -globalopt -domtree -mem2reg -deadargelim -domtree -basicaa -aa -simplifycfg -pgo-icall-prom -basiccg -globals-aa -prune-eh -always-inline -functionattrs -domtree -sroa -early-cse -lazy-value-info -jump-threading -correlated-propagation -simplifycfg -domtree -basicaa -aa -libcalls-shrinkwrap -tailcallelim -simplifycfg -reassociate -domtree -loops -loop-simplify -lcssa-verification -lcssa -basicaa -aa -scalar-evolution -loop-rotate -licm -loop-unswitch -simplifycfg -domtree -basicaa -aa -loops -loop-simplify -lcssa-verification -lcssa -scalar-evolution -indvars -loop-idiom -loop-deletion -memdep -memcpyopt -sccp -domtree -demanded-bits -bdce -basicaa -aa -lazy-value-info -jump-threading -correlated-propagation -domtree -basicaa -aa -memdep -dse -loops -loop-simplify -lcssa-verification -lcssa -aa -scalar-evolution -licm -postdomtree -adce -simplifycfg -domtree -basicaa -aa -barrier -basiccg -rpo-functionattrs -globals-aa -float2int -domtree -loops -loop-simplify -lcssa-verification -lcssa -basicaa -aa -scalar-evolution -loop-rotate -loop-accesses -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -loop-distribute -loop-simplify -lcssa-verification -lcssa -branch-prob -block-freq -scalar-evolution -basicaa -aa -loop-accesses -demanded-bits -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -loop-vectorize -loop-simplify -scalar-evolution -aa -loop-accesses -loop-load-elim -basicaa -aa -simplifycfg -domtree -basicaa -aa -loops -scalar-evolution -alignment-from-assumptions -strip-dead-prototypes -domtree -loops -branch-prob -block-freq -loop-simplify -lcssa-verification -lcssa -basicaa -aa -scalar-evolution -branch-prob -block-freq -loop-sink -instsimplify
-
-CFLAGS = -O1 $(APP_CFLAGS) $(PLATFORM_CFLAGS)
-OBJS_CFLAGS = -O1 $(APP_CFLAGS) $(PLATFORM_CFLAGS)
-CXXFLAGS = $(APP_CXXFLAGS) $(PLATFORM_CXXFLAGS)
-LDFLAGS= $(APP_LDFLAGS) $(PLATFORM_LDFLAGS)
-
-LIBCLC_LIB_PATH = $(LLVM_SRC_ROOT)/../libclc/built_libs
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/projects/visc-rt
-
-VISC_RT_LIB = $(VISC_RT_PATH)/visc-rt.ll
-#LIBCLC_NVPTX_LIB = $(LIBCLC_LIB_PATH)/nvptx--nvidiacl.bc
-LIBCLC_NVPTX_LIB = $(LIBCLC_LIB_PATH)/nvptx64--nvidiacl.bc
-#LIBCLC_NVPTX_LIB = nvptx64--nvidiacl.bc
-
-LLVM_34_AS = $(LLVM_34_ROOT)/build/bin/llvm-as
-
-TESTGEN_OPTFLAGS = -load LLVMGenVISC.so -genvisc -globaldce
-KERNEL_GEN_FLAGS = -O3 -target nvptx64-nvidia-nvcl
-
-ifeq ($(TARGET),x86)
- DEVICE = SPIR_TARGET
- VISC_OPTFLAGS = -load LLVMBuildDFG.so -load LLVMLocalMem.so -load LLVMDFG2LLVM_SPIR.so -load LLVMDFG2LLVM_X86.so -load LLVMClearDFG.so -localmem -dfg2llvm-spir -dfg2llvm-x86 -clearDFG
- CFLAGS += -DOPENCL_CPU
- VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-spir
-else ifeq ($(TARGET),seq)
- DEVICE = CPU_TARGET
- VISC_OPTFLAGS = -load LLVMBuildDFG.so -load LLVMDFG2LLVM_X86.so -load LLVMClearDFG.so -dfg2llvm-x86 -clearDFG
- VISC_OPTFLAGS += -visc-timers-x86
-else ifeq ($(TARGET),fpga)
- DEVICE = FPGA_TARGET
- VISC_OPTFLAGS = -load LLVMBuildDFG.so -load LLVMLocalMem.so -load LLVMDFG2LLVM_FPGA.so -load LLVMDFG2LLVM_X86.so -load LLVMClearDFG.so -localmem -dfg2llvm-fpga -dfg2llvm-x86 -clearDFG
- CFLAGS += -DOPENCL_CPU
- VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-fpga
-else
- DEVICE = GPU_TARGET
- VISC_OPTFLAGS = -load LLVMBuildDFG.so -load LLVMLocalMem.so -load LLVMDFG2LLVM_NVPTX.so -load LLVMDFG2LLVM_X86.so -load LLVMClearDFG.so -localmem -dfg2llvm-nvptx -dfg2llvm-x86 -clearDFG
- VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-ptx
-endif
- TESTGEN_OPTFLAGS += -visc-timers-gen
-
-CFLAGS += -DDEVICE=$(DEVICE)
-CXXFLAGS += -DDEVICE=$(DEVICE)
-
-#ifeq ($(TIMER),x86)
-# VISC_OPTFLAGS += -visc-timers-x86
-#else ifeq ($(TIMER),ptx)
-# VISC_OPTFLAGS += -visc-timers-ptx
-#else ifeq ($(TIMER),gen)
-# TESTGEN_OPTFLAGS += -visc-timers-gen
-#else ifeq ($(TIMER),spir)
-# TESTGEN_OPTFLAGS += -visc-timers-spir
-#else ifeq ($(TIMER),fpga)
-# TESTGEN_OPTFLAGS += -visc-timers-fpga
-#else ifeq ($(TIMER),no)
-#else
-# ifeq ($(TARGET),x86)
-# VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-spir
-# else ifeq ($(TARGET),seq)
-# VISC_OPTFLAGS += -visc-timers-x86
-# else ifeq ($(TARGET),fpga)
-# VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-fpga
-# else ifeq ($(TARGET),seqx86)
-# VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-spir
-# else ifeq ($(TARGET),seqgpu)
-# VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-ptx
-# else
-# VISC_OPTFLAGS += -visc-timers-x86 -visc-timers-ptx
-# endif
-# TESTGEN_OPTFLAGS += -visc-timers-gen
-#endif
-
-# Add BUILDDIR as a prefix to each element of $1
-INBUILDDIR=$(addprefix $(BUILD_DIR)/,$(1))
-
-# Add SRCDIR as a prefix to each element of $1
-#INSRCDIR=$(addprefix $(SRCDIR)/,$(1))
-
-PYTHON_LLVM_40_34 = ../llvm-40-34.py
-
-.PRECIOUS: $(BUILD_DIR)/%.ll
-
-OBJS = $(call INBUILDDIR,$(SRCDIR_OBJS))
-TEST_OBJS = $(call INBUILDDIR,$(VISC_OBJS))
-KERNEL = $(TEST_OBJS).kernels.ll
-
-ifeq ($(TARGET),x86)
- SPIR_ASSEMBLY = $(TEST_OBJS).kernels.bc
-else ifeq ($(TARGET),seq)
-else ifeq ($(TARGET),fpga)
- AOC_CL = $(TEST_OBJS).kernels.cl
- AOCL_ASSEMBLY = $(TEST_OBJS).kernels.aocx
- BOARD = a10gx
- ifeq ($(EMULATION),1)
- EXE = cava-visc-emu
- AOC_EMU = -march=emulator
- BUILD_DIR = build/$(TARGET)-emu
- endif
-else
- KERNEL_LINKED = $(BUILD_DIR)/$(APP).kernels.linked.ll
- #KERNEL = $(TEST_OBJS).kernels.ll
- PTX_ASSEMBLY = $(TEST_OBJS).nvptx.s
-endif
-
-HOST_LINKED = $(BUILD_DIR)/$(APP).linked.ll
-HOST = $(BUILD_DIR)/$(APP).host.ll
-
-ifeq ($(OPENCL_PATH),)
-FAILSAFE=no_opencl
-else
-FAILSAFE=
-endif
-
-# Targets
-default: $(FAILSAFE) $(BUILD_DIR) $(EXE)
-#default: $(FAILSAFE) $(BUILD_DIR) $(PTX_ASSEMBLY) $(SPIR_ASSEMBLY) $(AOC_CL) $(AOCL_ASSEMBLY) $(EXE)
-
-$(PTX_ASSEMBLY) : $(KERNEL_LINKED)
- $(CC) $(KERNEL_GEN_FLAGS) -S $< -o $@
-
-$(KERNEL_LINKED) : $(KERNEL)
- $(LLVM_LINK) $(LIBCLC_NVPTX_LIB) -S $< -o $@
-
-$(SPIR_ASSEMBLY) : $(KERNEL)
- python $(PYTHON_LLVM_40_34) $< $(BUILD_DIR)/kernel_34.ll
- $(LLVM_34_AS) $(BUILD_DIR)/kernel_34.ll -o $@
-
-$(AOCL_ASSEMBLY) : $(AOC_CL)
- aoc --report $(AOC_EMU) $(AOC_CL) -o $(AOCL_ASSEMBLY) -board=$(BOARD)
-
-$(AOC_CL) : $(KERNEL)
- llvm-cbe --debug $(KERNEL)
-
-$(EXE) : $(HOST_LINKED)
- $(CXX) -O3 $(LDFLAGS) $< -o $@
-
-$(HOST_LINKED) : $(HOST) $(OBJS) $(VISC_RT_LIB)
- $(LLVM_LINK) $^ -S -o $@
-
-$(VISC_RT_LIB) : $(VISC_RT_PATH)/visc-rt.cpp
- make -C $(LLVM_LIB_PATH)
-
-$(HOST) $(KERNEL): $(BUILD_DIR)/$(VISC_OBJS)
- $(OPT) -debug $(VISC_OPTFLAGS) -S $< -o $(HOST)
-# mv *.ll $(BUILD_DIR)
-# $(OPT) -debug-only=DFG2LLVM_SPIR,DFG2LLVM_X86,DFG2LLVM_FPGA,GENVISC $(VISC_OPTFLAGS) -S $< -o $(HOST)
-#$(OBJS): $(OBJS_SRC)
-# $(CC) $(OBJS_CFLAGS) -emit-llvm -S -o $@ $<
-
-$(BUILD_DIR):
- mkdir -p $(BUILD_DIR)
-
-$(BUILD_DIR)/%.ll : $(SRC_DIR)/%.c
- $(CC) $(OBJS_CFLAGS) -emit-llvm -S -o $@ $<
-
-$(BUILD_DIR)/main.ll : $(SRC_DIR)/main.c
- $(CC) $(CFLAGS) -emit-llvm -S -o $@ $<
-
-#$(BUILD_DIR)/main.opt.ll : $(BUILD_DIR)/main.ll
-# $(OPT) $(OPT_FLAGS) $< -S -o $@
-
-$(BUILD_DIR)/main.visc.ll : $(BUILD_DIR)/main.ll
- $(OPT) -debug-only=genvisc $(TESTGEN_OPTFLAGS) $< -S -o $@
-
-## END HPVM MAKEFILE
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam-vision-native b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam-vision-native
deleted file mode 100755
index 938e1b1a15d86e71b9b044e594472dad10fd9bc2..0000000000000000000000000000000000000000
Binary files a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam-vision-native and /dev/null differ
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe.c
deleted file mode 100644
index 7874ff9d529afebc40d1660637e85b3a1e00f23e..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe.c
+++ /dev/null
@@ -1,139 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include "pipe_stages.h"
-#include "load_cam_model.h"
-#include "cam_pipe_utility.h"
-#include "dma_interface.h"
-#ifdef DMA_MODE
-#include "gem5_harness.h"
-#endif
-
-// FIXME: Include gem5/dma_interface.cc/h separately
-#ifndef DMA_INTERFACE_V3
-#define DMA_INTERFACE_V3
-#endif//DMA_INTERFACE_V3
-
-///////////////////////////////////////////////////////////////
-// Camera Model Parameters
-///////////////////////////////////////////////////////////////
-
-// Path to the camera model to be used
-char cam_model_path[100];
-
-// White balance index (select white balance from transform file)
-// The first white balance in the file has a wb_index of 1
-// For more information on model format see the readme
-int wb_index = 6;
-
-// Number of control points
-int num_ctrl_pts = 3702;
-
-void load_cam_params_hw(float *host_TsTw, float *host_ctrl_pts,
- float *host_weights, float *host_coefs,
- float *host_tone_map, float *acc_TsTw,
- float *acc_ctrl_pts, float *acc_weights,
- float *acc_coefs, float *acc_tone_map) {
- dmaLoad(acc_TsTw, host_TsTw, 9 * sizeof(float));
- dmaLoad(acc_ctrl_pts, host_ctrl_pts,
- num_ctrl_pts * CHAN_SIZE * sizeof(float));
- dmaLoad(acc_weights, host_weights, num_ctrl_pts * CHAN_SIZE * sizeof(float));
- dmaLoad(acc_coefs, host_coefs, 4 * CHAN_SIZE * sizeof(float));
- dmaLoad(acc_tone_map, host_tone_map, 256 * CHAN_SIZE * sizeof(float));
-}
-
-void isp_hw(uint8_t *host_input, uint8_t *host_result, int row_size,
- int col_size, uint8_t *acc_input, uint8_t *acc_result,
- float *acc_input_scaled, float *acc_result_scaled, float *acc_TsTw,
- float *acc_ctrl_pts, float *acc_weights, float *acc_coefs,
- float *acc_tone_map, float *acc_l2_dist) {
- dmaLoad(acc_input, host_input,
- row_size * col_size * CHAN_SIZE * sizeof(uint8_t));
- scale_fxp(acc_input, row_size, col_size, acc_input_scaled);
- demosaic_fxp(acc_input_scaled, row_size, col_size, acc_result_scaled);
- denoise_fxp(acc_result_scaled, row_size, col_size, acc_input_scaled);
- transform_fxp(acc_input_scaled, row_size, col_size, acc_result_scaled,
- acc_TsTw);
- gamut_map_fxp(acc_result_scaled, row_size, col_size, acc_input_scaled,
- acc_ctrl_pts, acc_weights, acc_coefs, acc_l2_dist);
- tone_map_fxp(acc_input_scaled, row_size, col_size, acc_tone_map,
- acc_result_scaled);
- // tone_map_approx_fxp(acc_input_scaled, row_size, col_size,
- // acc_result_scaled);
- descale_fxp(acc_result_scaled, row_size, col_size, acc_result);
- dmaStore(host_result, acc_result,
- row_size * col_size * CHAN_SIZE * sizeof(uint8_t));
-}
-
-void cam_pipe(uint8_t *host_input, uint8_t *host_result, int row_size,
- int col_size) {
- uint8_t *acc_input, *acc_result;
- float *acc_input_scaled, *acc_result_scaled;
- float *host_TsTw, *host_ctrl_pts, *host_weights, *host_coefs, *host_tone_map;
- float *acc_TsTw, *acc_ctrl_pts, *acc_weights, *acc_coefs, *acc_tone_map, *acc_l2_dist;
-
- strcat(cam_model_path, "cam_models/NikonD7000/");
-
- host_TsTw = get_TsTw(cam_model_path, wb_index);
- float *trans = transpose_mat(host_TsTw, CHAN_SIZE, CHAN_SIZE);
- free(host_TsTw);
- host_TsTw = trans;
- host_ctrl_pts = get_ctrl_pts(cam_model_path, num_ctrl_pts);
- host_weights = get_weights(cam_model_path, num_ctrl_pts);
- host_coefs = get_coefs(cam_model_path, num_ctrl_pts);
- host_tone_map = get_tone_map(cam_model_path);
-
- acc_input = (uint8_t*) malloc_aligned(sizeof(uint8_t) * row_size * col_size * CHAN_SIZE);
- acc_result = (uint8_t*) malloc_aligned(sizeof(uint8_t) * row_size * col_size * CHAN_SIZE);
- acc_input_scaled = (float*) malloc_aligned(sizeof(float) * row_size * col_size * CHAN_SIZE);
- acc_result_scaled = (float*) malloc_aligned(sizeof(float) * row_size * col_size * CHAN_SIZE);
- acc_TsTw = (float*) malloc_aligned(sizeof(float) * 9);
- acc_ctrl_pts = (float*) malloc_aligned(sizeof(float) * num_ctrl_pts * CHAN_SIZE);
- acc_weights = (float*) malloc_aligned(sizeof(float) * num_ctrl_pts * CHAN_SIZE);
- acc_coefs = (float*) malloc_aligned(sizeof(float) * 12);
- acc_tone_map = (float*) malloc_aligned(sizeof(float) * 256 * CHAN_SIZE);
- acc_l2_dist = (float*) malloc_aligned(sizeof(float) * num_ctrl_pts);
-
- // Load camera model parameters for the ISP
- MAP_ARRAY_TO_ACCEL(ISP, "host_TsTw", host_TsTw,
- sizeof(float) * 9);
- MAP_ARRAY_TO_ACCEL(ISP, "host_ctrl_pts", host_ctrl_pts,
- sizeof(float) * num_ctrl_pts * CHAN_SIZE);
- MAP_ARRAY_TO_ACCEL(ISP, "host_weights", host_weights,
- sizeof(float) * num_ctrl_pts * CHAN_SIZE);
- MAP_ARRAY_TO_ACCEL(ISP, "host_coefs", host_coefs,
- sizeof(float) * 4 * CHAN_SIZE);
- MAP_ARRAY_TO_ACCEL(ISP, "host_tone_map", host_tone_map,
- sizeof(float) * 256 * CHAN_SIZE);
- INVOKE_KERNEL(ISP, load_cam_params_hw, host_TsTw, host_ctrl_pts, host_weights,
- host_coefs, host_tone_map, acc_TsTw, acc_ctrl_pts, acc_weights,
- acc_coefs, acc_tone_map);
-
- // Invoke the ISP
- MAP_ARRAY_TO_ACCEL(ISP, "host_input", host_input,
- sizeof(uint8_t) * row_size * col_size * CHAN_SIZE);
- MAP_ARRAY_TO_ACCEL(ISP, "host_result", host_result,
- sizeof(uint8_t) * row_size * col_size * CHAN_SIZE);
- INVOKE_KERNEL(ISP, isp_hw, host_input, host_result, row_size, col_size,
- acc_input, acc_result, acc_input_scaled, acc_result_scaled,
- acc_TsTw, acc_ctrl_pts, acc_weights, acc_coefs, acc_tone_map,
- acc_l2_dist);
-
- free(acc_input);
- free(acc_result);
- free(acc_input_scaled);
- free(acc_result_scaled);
- free(host_TsTw);
- free(host_ctrl_pts);
- free(host_weights);
- free(host_coefs);
- free(host_tone_map);
- free(acc_TsTw);
- free(acc_ctrl_pts);
- free(acc_weights);
- free(acc_coefs);
- free(acc_tone_map);
- free(acc_l2_dist);
-}
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe.h
deleted file mode 100644
index 83a77e01a67886af64902eacfd5af69a0a8d48b0..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _CAM_PIPE_H_
-#define _CAM_PIPE_H_
-
-void cam_pipe(uint8_t *host_input, uint8_t *host_result, int row_size,
- int col_size);
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe_utility.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe_utility.c
deleted file mode 100644
index f806e9ee1a2e288fabcb8ad658a47c3919fbb661..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe_utility.c
+++ /dev/null
@@ -1,82 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <assert.h>
-
-#include "cam_pipe_utility.h"
-//#include "pipe_stages.h"
-
-uint8_t *read_image_from_binary(char *file_path, int *row_size, int *col_size) {
- uint8_t *image;
- FILE *fp = fopen(file_path, "r");
- int chan_size;
- if (fread(row_size, sizeof(int), 1, fp) != 1)
- assert("Failed to read row size from binary file!");
- if (fread(col_size, sizeof(int), 1, fp) != 1)
- assert("Failed to read col size from binary file!");
- if (fread(&chan_size, sizeof(int), 1, fp) != 1)
- assert("Failed to read row size from binary file!");
- assert(chan_size == CHAN_SIZE && "Channel size read from the binary file "
- "doesn't equal to the default value!\n");
-
- int size = *row_size * *col_size * CHAN_SIZE;
- image = malloc_aligned(sizeof(uint8_t) * size);
- if (fread(image, sizeof(uint8_t), size, fp) != size)
- assert("Failed to read the image from binary file!");
- fclose(fp);
- return image;
-}
-
-void write_image_to_binary(char *file_path, uint8_t *image, int row_size, int col_size) {
- FILE *fp = fopen(file_path, "w");
-
- int shape[3] = { row_size, col_size, CHAN_SIZE };
- fwrite(shape, sizeof(int), 3, fp);
-
- int size = row_size * col_size * CHAN_SIZE;
- fwrite(image, sizeof(uint8_t), size, fp);
- fclose(fp);
-}
-
-float *transpose_mat(float *inmat, int width, int height) {
- // Define vectors
- float *outmat;
- int err =
- posix_memalign((void **)&outmat, CACHELINE_SIZE, sizeof(float) * height * width);
- assert(err == 0 && "Failed to allocate memory!");
-
- // Transpose the matrix
- for (int i = 0; i < height; i++) {
- for (int j = 0; j < width; j++) {
- outmat[j * height + i] = inmat[i * width + j];
- }
- }
- return outmat;
-}
-
-void convert_hwc_to_chw(uint8_t *input, int row_size, int col_size,
- uint8_t **result) {
- if (*result == NULL) {
- *result = (uint8_t *)malloc_aligned(row_size * col_size * CHAN_SIZE *
- sizeof(uint8_t));
- }
- ARRAY_3D(uint8_t, _input, input, col_size, CHAN_SIZE);
- ARRAY_3D(uint8_t, _result, *result, row_size, col_size);
- for (int h = 0; h < row_size; h++)
- for (int w = 0; w < col_size; w++)
- for (int c = 0; c < CHAN_SIZE; c++)
- _result[c][h][w] = _input[h][w][c];
-}
-
-void convert_chw_to_hwc(uint8_t *input, int row_size, int col_size,
- uint8_t **result) {
- if (*result == NULL) {
- *result = (uint8_t *)malloc_aligned(row_size * col_size * CHAN_SIZE *
- sizeof(uint8_t));
- }
- ARRAY_3D(uint8_t, _input, input, row_size, col_size);
- ARRAY_3D(uint8_t, _result, *result, col_size, CHAN_SIZE);
- for (int c = 0; c < CHAN_SIZE; c++)
- for (int h = 0; h < row_size; h++)
- for (int w = 0; w < col_size; w++)
- _result[h][w][c] = _input[c][h][w];
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe_utility.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe_utility.h
deleted file mode 100644
index b4fb6cde0c438b23c2b596cf0418953aaedca501..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/cam_pipe_utility.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _CAM_PIPE_UTILITY_H_
-#define _CAM_PIPE_UTILITY_H_
-
-#include "utility.h"
-#include "pipe_stages.h"
-
-uint8_t *read_image_from_binary(char *file_path, int *row_size, int *col_size);
-void write_image_to_binary(char *file_path, uint8_t *image, int row_size,
- int col_size);
-float *transpose_mat(float *inmat, int width, int height);
-void convert_hwc_to_chw(uint8_t *input, int row_size, int col_size,
- uint8_t **result);
-void convert_chw_to_hwc(uint8_t *input, int row_size, int col_size,
- uint8_t **result);
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/defs.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/defs.h
deleted file mode 100644
index ccc8acc857c36fd13115670932a38dc3a406dc29..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/defs.h
+++ /dev/null
@@ -1,224 +0,0 @@
-#ifndef _COMMON_DEFS_H_
-#define _COMMON_DEFS_H_
-
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-typedef unsigned int uint32_t;
-typedef unsigned long uint64_t;
-
-#define CACHELINE_SIZE 64
-
-// Debugging message macros.
-#if DEBUG_LEVEL >= 1
- #define INFO_MSG(args...) printf(args)
-
- #if DEBUG_LEVEL >= 2
- #define PRINT_MSG(args...) printf(args)
- #define PRINT_DEBUG(hid, rows, cols, num_cols) \
- print_debug(hid, rows, cols, num_cols)
- #define PRINT_DEBUG4D(hid, rows, cols, height) \
- print_debug4d(hid, rows, cols, height)
- #define PRINT_DEBUG4D_FP16(hid, num, height, rows, cols) \
- print_debug4d_fp16(hid, num, height, rows, cols)
-
- #if DEBUG_LEVEL >= 3
- #define PRINT_DEBUG_V(hid, rows, cols, num_cols) \
- print_debug(hid, rows, cols, num_cols)
- #define PRINT_DEBUG4D_V(hid, rows, cols, height) \
- print_debug4d(hid, rows, cols, height)
- #define PRINT_MSG_V(args...) printf(args)
- #else
- #define PRINT_DEBUG_V(hid, rows, cols, num_cols)
- #define PRINT_DEBUG4D_V(hid, rows, cols, height)
- #define PRINT_MSG_V(args...)
- #endif
- #else
- #define PRINT_MSG(args...)
- #define PRINT_DEBUG(hid, rows, cols, num_cols)
- #define PRINT_DEBUG4D(hid, rows, cols, height)
- #define PRINT_DEBUG4D_FP16(hid, num, height, rows, cols)
- #define PRINT_DEBUG_V(hid, rows, cols, height)
- #define PRINT_DEBUG4D_V(hid, rows, cols, height)
- #define PRINT_MSG_V(args...)
- #endif
-#else
- #define INFO_MSG(args...)
- #define PRINT_DEBUG(hid, rows, cols, num_cols)
- #define PRINT_DEBUG4D(hid, rows, cols, height)
- #define PRINT_DEBUG4D_FP16(hid, num, height, rows, cols)
- #define PRINT_MSG(args...)
- #define PRINT_DEBUG_V(hid, rows, cols, height)
- #define PRINT_DEBUG4D_V(hid, rows, cols, height)
- #define PRINT_MSG_V(args...)
-#endif
-
-#define STRING(arg) #arg
-
-// This is to avoid a ton of spurious unused variable warnings when
-// we're not building for gem5.
-#define UNUSED(x) (void)(x)
-
-// Macros for computing the maximum of a group of elements.
-//
-// Why macros and not functions (or a loop)? A loop takes O(n) cycles to
-// compute the maximum, when it could be done in O(log n) time with a tree
-// based implementation. But Aladdin regards function calls as a hard
-// dependency that it does not optimize across, so we would not get the
-// parallelism we expect from the tree. Thus, these must be macros.
-//
-// I've only implemented a few of these. These are only meant for the pooling
-// layers, and we shouldn't need more than a 3x3 pooling layer anyways.
-#define max2(A, B) (((A) > (B)) ? (A) : (B))
-#define max3(e0, e1, e2) max2(max2(e0, e1), e2)
-#define max4(e0, e1, e2, e3) max2(max2(e0, e1), max2(e2, e3))
-#define max8(e0, e1, e2, e3, e4, e5, e6, e7) \
- max2(max4(e0, e1, e2, e3), max4(e4, e5, e6, e7))
-#define max9(e0, e1, e2, e3, e4, e5, e6, e7, e8) \
- max2(max8(e0, e1, e2, e3, e4, e5, e6, e7), e8)
-
-#define min2(A, B) (((A) < (B)) ? (A) : (B))
-
-#define FRAC_CEIL(A, B) ((A) / (B) + ((A) % (B) != 0))
-// Convenience macros to switch between invoking an accelerator (if building a
-// binary for gem5) or just calling the kernel function in software.
-//
-// Usage:
-//
-// These macros expand differently based on whether the GEM5_HARNESS macro is
-// defined. If so, then this binary is meant to be run under gem5, invoking
-// accelerators; if not, this binary should run the pure software version of
-// the accelerated kernels.
-//
-// If GEM5_HARNESS is defined:
-//
-// MAP_ARRAY_TO_ACCEL(myReqCode, myArrayName, myArrayPtr, mySize)
-// ===> mapArrayToAccelerator(myReqCode, myArrayName, myArrayPtr, mySize)
-//
-// INVOKE_KERNEL(myReqCode, kernelFuncName, args...)
-// ===> invokeAcceleratorAndBlock(myReqCode)
-//
-// Otherwise:
-// MAP_ARRAY_TO_ACCEL(myReqCode, myArrayName, myArrayPtr, mySize)
-// expands to nothing
-//
-// INVOKE_KERNEL(myReqCode, kernelFuncName, args...)
-// ===> kernelFuncName(args)
-//
-#ifdef GEM5_HARNESS
-
-#define MAP_ARRAY_TO_ACCEL(req_code, name, base_addr, size) \
- mapArrayToAccelerator(req_code, name, base_addr, size)
-#define INVOKE_KERNEL(req_code, kernel_ptr, args...) \
- do { \
- UNUSED(kernel_ptr); \
- invokeAcceleratorAndBlock(req_code); \
- } while (0)
-#define INVOKE_KERNEL_NOBLOCK(req_code, finish_flag, kernel_ptr, args...) \
- do { \
- UNUSED(kernel_ptr); \
- invokeAcceleratorAndReturn2(req_code, finish_flag); \
- } while (0)
-
-#define INVOKE_DMA_READ_TRAFFIC_GEN(start_addr, size) \
- do { \
- invokeAladdinTrafficGenAndBlock(start_addr, size, false, false); \
- } while (0)
-#define INVOKE_DMA_WRITE_TRAFFIC_GEN(start_addr, size) \
- do { \
- invokeAladdinTrafficGenAndBlock(start_addr, size, true, false); \
- } while (0)
-#define INVOKE_ACP_READ_TRAFFIC_GEN(start_addr, size) \
- do { \
- invokeAladdinTrafficGenAndBlock(start_addr, size, false, true); \
- } while (0)
-#define INVOKE_ACP_WRITE_TRAFFIC_GEN(start_addr, size) \
- do { \
- invokeAladdinTrafficGenAndBlock(start_addr, size, true, true); \
- } while (0)
-
-#else
-
-#define MAP_ARRAY_TO_ACCEL(req_code, name, base_addr, size) \
- do { \
- INFO_MSG("Mapping array %s @ %p, size %d.\n", \
- name, (void*)base_addr, (int)(size)); \
- UNUSED(req_code); \
- UNUSED(name); \
- UNUSED(base_addr); \
- UNUSED(size); \
- } while (0)
-#define INVOKE_KERNEL(req_code, kernel_ptr, args...) kernel_ptr(args)
-#define INVOKE_KERNEL_NOBLOCK(req_code, finish_flag, kernel_ptr, args...) \
- kernel_ptr(args)
-#define INVOKE_DMA_READ_TRAFFIC_GEN(start_addr, size) \
- do { \
- UNUSED(start_addr); \
- UNUSED(size); \
- } while (0)
-#define INVOKE_DMA_WRITE_TRAFFIC_GEN(start_addr, size) \
- do { \
- UNUSED(start_addr); \
- UNUSED(size); \
- } while (0)
-#define INVOKE_ACP_READ_TRAFFIC_GEN(start_addr, size) \
- do { \
- UNUSED(start_addr); \
- UNUSED(size); \
- } while (0)
-#define INVOKE_ACP_WRITE_TRAFFIC_GEN(start_addr, size) \
- do { \
- UNUSED(start_addr); \
- UNUSED(size); \
- } while (0)
-
-#endif
-
-// Simplified version of MAP_ARRAY_TO_ACCEL.
-//
-// This assumes that the current name of the base pointer is also the name of
-// the array in the top level function of the dynamic trace. THIS IS VERY
-// IMPORTANT - if the argument passed to a top level function has been renamed in
-// the function, then this WILL NOT WORK!
-//
-// MAP_ARRAY(myReqCode, myArray, mySize)
-// ===> MAP_ARRAY_TO_ACCEL(myReqCode, "myArray", myArray, mySize)
-#define MAP_ARRAY(req_code, name_and_base_addr, size) \
- MAP_ARRAY_TO_ACCEL( \
- req_code, STRING(name_and_base_addr), name_and_base_addr, size)
-
-// Use these convenience macros to cast a raw pointer into a multidimensional
-// variable-length array, which lets us use [] notation inside of the ugly
-// sub2ind syntax!
-//
-// Usage:
-// If we have an array like array[5][4]:
-// ARRAY_2D(TYPE, output_name, array, 4);
-//
-// If we have an array like array[5][4][3]:
-// ARRAY_3D(TYPE, output_name, array, 4, 3);
-//
-// If we have an array like array[5][4][3][2]
-// ARRAY_4D(TYPE, output_name, array, 4, 3, 2);
-//
-// And so on...
-#define ARRAY_1D(TYPE, output_array_name, input_array_name) \
- TYPE* output_array_name = (TYPE*)input_array_name
-
-#define ARRAY_2D(TYPE, output_array_name, input_array_name, DIM_1) \
- TYPE(*output_array_name)[DIM_1] = (TYPE(*)[DIM_1])input_array_name
-
-#define ARRAY_3D(TYPE, output_array_name, input_array_name, DIM_1, DIM_2) \
- TYPE(*output_array_name)[DIM_1][DIM_2] = \
- (TYPE(*)[DIM_1][DIM_2])input_array_name
-
-#define ARRAY_4D( \
- TYPE, output_array_name, input_array_name, DIM_1, DIM_2, DIM_3) \
- TYPE(*output_array_name)[DIM_1][DIM_2][DIM_3] = \
- (TYPE(*)[DIM_1][DIM_2][DIM_3])input_array_name
-
-#define ARRAY_5D( \
- TYPE, output_array_name, input_array_name, DIM_1, DIM_2, DIM_3, DIM_4) \
- TYPE(*output_array_name)[DIM_1][DIM_2][DIM_3][DIM_4] = \
- (TYPE(*)[DIM_1][DIM_2][DIM_3][DIM_4])input_array_name
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/dma_interface.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/dma_interface.c
deleted file mode 100644
index 81bce54469886153170f994a77250a784cc9b7d7..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/dma_interface.c
+++ /dev/null
@@ -1,73 +0,0 @@
-#include <assert.h>
-#include <string.h>
-#include "dma_interface.h"
-
-// All _dmaImplN functions must be always inlined or we'll get extra functions
-// in the trace.
-
-#if defined(DMA_INTERFACE_V3)
-
-// Starting with version 3, all versioning will be distinguished by the return
-// value of the DMA functions.
-
-__attribute__((__always_inline__))
-int _dmaImpl3(void* dst_addr, void* src_addr, size_t size) {
- assert(size > 0);
- memmove(dst_addr, src_addr, size);
- return 3;
-}
-
-int dmaLoad(void* dst_addr, void* src_host_addr, size_t size) {
- return _dmaImpl3(dst_addr, src_host_addr, size);
-}
-
-int dmaStore(void* dst_host_addr, void* src_addr, size_t size) {
- return _dmaImpl3(dst_host_addr, src_addr, size);
-}
-
-int setReadyBits(void* start_addr, size_t size, unsigned value) {
- asm("");
- return 0;
-}
-
-#elif defined(DMA_INTERFACE_V2)
-
-// With version 2 and earlier, we return (void*)NULL and use the number of
-// function arguments to distinguish the DMA functions.
-
-__attribute__((__always_inline__))
-void* _dmaImpl2(void* base_addr, size_t src_off, size_t dst_off, size_t size) {
- assert(size > 0);
- memmove(base_addr + dst_off, base_addr + src_off, size);
- return NULL;
-}
-
-void* dmaLoad(void* base_addr, size_t src_off, size_t dst_off, size_t size) {
- return _dmaImpl2(base_addr, src_off, dst_off, size);
-}
-
-void* dmaStore(void* base_addr, size_t src_off, size_t dst_off, size_t size) {
- return _dmaImpl2(base_addr, src_off, dst_off, size);
-}
-
-#else
-
-__attribute__((__always_inline__))
-void* _dmaImpl1(void* base_addr, size_t offset, size_t size) {
- assert(size > 0);
- asm("");
- return NULL;
-}
-
-void* dmaLoad(void* addr, size_t offset, size_t size) {
- return _dmaImpl1(addr, offset, size);
-}
-
-void* dmaStore(void* addr, size_t offset, size_t size) {
- return _dmaImpl1(addr, offset, size);
-}
-#endif
-
-void dmaFence() {
- asm("");
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/dma_interface.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/dma_interface.h
deleted file mode 100644
index f23234eede4df99db84b144646530dfe240c6e62..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/dma_interface.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __DMA_INTERFACE_H__
-#define __DMA_INTERFACE_H__
-
-#include <stddef.h>
-
-#define PAGE_SIZE 4096
-
-#if defined(DMA_INTERFACE_V3)
-
-// Version 3 of the DMA interface enables memcpy operations from arbitrary
-// source and destination addresses.
-
-int dmaLoad(void* dst_addr, void* src_host_addr, size_t size);
-int dmaStore(void* dst_host_addr, void* src_addr, size_t size);
-
-// The user can explicitly toggle the state of ready bits, if ready mode is
-// enabled. This requires support from DMA v3.
-int setReadyBits(void* start_addr, size_t size, unsigned value);
-
-#elif defined(DMA_INTERFACE_V2)
-
-#warning "DMA interface v2 is deprecated!"
-
-// Version 2 of the DMA interface separates source and destination offsets from
-// the base address into different fields, and on the host machine, memory is
-// actually copied from source to destination (the memory copy will not show up
-// in the trace).
-
-void* dmaLoad(void* base_addr, size_t src_off, size_t dst_off, size_t size);
-void* dmaStore(void* base_addr, size_t src_off, size_t dst_off, size_t size);
-
-#else
-
-#warning "DMA interface v1 is deprecated!"
-
-// Version 1 of the DMA interface is now deprecated and will be removed entirely.
-
-void* dmaLoad(void* addr, size_t offset, size_t size);
-void* dmaStore(void* addr, size_t offset, size_t size);
-
-#endif
-void dmaFence();
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/gem5_harness.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/gem5_harness.h
deleted file mode 100644
index 36859cfe1ba67bc8197d7ea3961adfbeb95c70b1..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/gem5_harness.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _GEM5_HARNESS_H_
-#define _GEM5_HARNESS_H_
-
-/* One header to include them all. */
-
-//#include "aladdin_sys_connection.h"
-//#include "aladdin_sys_constants.h"
-#include "dma_interface.h"
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/load_cam_model.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/load_cam_model.c
deleted file mode 100644
index 124fe0b7d175c2655feac562ecd6e2a5b73cc96a..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/load_cam_model.c
+++ /dev/null
@@ -1,335 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-#include "utility.h"
-#include "pipe_stages.h"
-#include "load_cam_model.h"
-
-// Get color space transform
-float* get_Ts(char* cam_model_path) {
- float *Ts;
- int err = posix_memalign((void **)&Ts, CACHELINE_SIZE, sizeof(float) * 9);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Open file for reading
- char file_name[] = "raw2jpg_transform.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx >= 1 && line_idx <= 3) {
- for (int j = 0; j < 3; j++) {
- Ts[(line_idx - 1) * 3 + j] = line_data[j];
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return Ts;
-}
-
-// Get white balance transform
-float* get_Tw(char* cam_model_path, int wb_index) {
- float *Tw;
- int err = posix_memalign((void **)&Tw, CACHELINE_SIZE, sizeof(float) * 9);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Calculate base for the white balance transform selected
- // For more details see the camera model readme
- int wb_base = 8 + 5*(wb_index-1);
-
- // Open file for reading
- // Open file for reading
- char file_name[] = "raw2jpg_transform.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- // Read a line at a time
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx == wb_base) {
- // Convert the white balance vector into a diagaonal matrix
- for (int i=0; i<3; i++) {
- for (int j=0; j<3; j++) {
- if (i == j) {
- Tw[i * 3 + j] = line_data[i];
- } else {
- Tw[i * 3 + j] = 0.0;
- }
- }
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return Tw;
-}
-
-
-// Get combined transforms for checking
-float* get_TsTw(char* cam_model_path, int wb_index) {
- float *TsTw;
- int err = posix_memalign((void **)&TsTw, CACHELINE_SIZE, sizeof(float) * 9);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Calculate base for the white balance transform selected
- // For more details see the camera model readme
- int wb_base = 5 + 5*(wb_index-1);
-
- // Open file for reading
- char file_name[] = "raw2jpg_transform.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- // Read a line at a time
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx >= wb_base && line_idx <= (wb_base + 2)) {
- for (int j = 0; j < 3; j++) {
- TsTw[(line_idx - wb_base) * 3 + j] = line_data[j];
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return TsTw;
-}
-
-// Get control points
-float* get_ctrl_pts(char* cam_model_path, int num_cntrl_pts) {
- float *ctrl_pnts;
- int err = posix_memalign((void **)&ctrl_pnts, CACHELINE_SIZE,
- sizeof(float) * num_cntrl_pts * 3);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Open file for reading
- char file_name[] = "raw2jpg_ctrlPoints.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- // Read a line at a time
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx >= 1 && line_idx <= num_cntrl_pts) {
- for (int j = 0; j < 3; j++) {
- ctrl_pnts[(line_idx - 1) * 3 + j] = line_data[j];
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return ctrl_pnts;
-}
-
-// Get weights
-float* get_weights(char* cam_model_path, int num_cntrl_pts) {
- float *weights;
- int err = posix_memalign((void **)&weights, CACHELINE_SIZE,
- sizeof(float) * num_cntrl_pts * 3);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Open file for reading
- char file_name[] = "raw2jpg_coefs.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- // Read a line at a time
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx >= 1 && line_idx <= num_cntrl_pts) {
- for (int j = 0; j < 3; j++) {
- weights[(line_idx - 1) * 3 + j] = line_data[j];
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return weights;
-}
-
-// Get coeficients
-float* get_coefs(char* cam_model_path, int num_cntrl_pts) {
- float *coefs;
- int err = posix_memalign((void **)&coefs, CACHELINE_SIZE, sizeof(float) * 12);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Open file for reading
- char file_name[] = "raw2jpg_coefs.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- // Read a line at a time
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx >= (num_cntrl_pts + 1) && line_idx <= (num_cntrl_pts + 4)) {
- for (int j = 0; j < 3; j++) {
- coefs[(line_idx - num_cntrl_pts - 1) * 3 + j] = line_data[j];
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return coefs;
-}
-
-
-// Get tone mapping table
-float* get_tone_map(char* cam_model_path) {
- float *tone_map;
- int err = posix_memalign((void **)&tone_map, CACHELINE_SIZE,
- sizeof(float) * 256 * CHAN_SIZE);
- assert(err == 0 && "Failed to allocate memory!");
- char *line;
- char *str;
- float line_data[3];
- size_t len = 0;
- int line_idx = 0;
-
- // Open file for reading
- char file_name[] = "raw2jpg_respFcns.txt";
- char file_path[100];
- strcpy(file_path, cam_model_path);
- strcat(file_path, file_name);
- FILE *fp = fopen(file_path, "r");
- if (fp == NULL) {
- printf("Didn't find the camera model file!\n");
- exit(1);
- }
-
- // Read a line at a time
- while (getline(&line, &len, fp) != -1) {
- str = strtok(line, " \n");
- int i = 0;
- while (str != NULL) {
- line_data[i] = atof(str);
- str = strtok(NULL, " \n");
- i++;
- }
-
- if (line_idx >= 1 && line_idx <= 256) {
- for (int j = 0; j < 3; j++) {
- tone_map[(line_idx - 1) * 3 + j] = line_data[j];
- }
- }
- line_idx = line_idx + 1;
- }
- fclose(fp);
- free(line);
- return tone_map;
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/load_cam_model.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/load_cam_model.h
deleted file mode 100644
index 8e5ee95217c901e57250bcce6b3cfc37cd9d6ce7..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/load_cam_model.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _LOAD_CAM_MODEL_H_
-#define _LOAD_CAM_MODEL_H_
-
-// Get color space transform
-float *get_Ts(char *cam_model_path);
-
-// Get white balance transform
-float *get_Tw(char *cam_model_path, int wb_index);
-
-// Get combined transforms for checking
-float *get_TsTw(char *cam_model_path, int wb_index);
-
-// Get control points
-float *get_ctrl_pts(char *cam_model_path, int num_cntrl_pts);
-
-// Get weights
-float *get_weights(char *cam_model_path, int num_cntrl_pts);
-
-// Get coeficients
-float *get_coefs(char *cam_model_path, int num_cntrl_pts);
-
-// Get tone mapping table
-float *get_tone_map(char *cam_model_path);
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/main.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/main.c
deleted file mode 100644
index cc75beb66419ae3a23f2d9578d9b5c19a238c4fe..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/main.c
+++ /dev/null
@@ -1,156 +0,0 @@
-
-#include <stdlib.h>
-#include "utility.h"
-#include "visc.h"
-#include "defs.h"
-
-
-typedef struct __attribute__((__packed__)) {
- float* input; size_t bytes_input;
- float* result; size_t bytes_result;
-}
-RootIn;
-
-/*
-typedef struct __attribute__((__packed__)) {
- uint8_t *input; size_t bytes_input;
- uint8_t *result; size_t bytes_result;
- float *input_scaled; size_t bytes_input_scaled;
- float *result_scaled; size_t bytes_result_scaled;
- float *demosaic_out; size_t bytes_demosaic_out;
- float *denoise_out; size_t bytes_denoise_out;
- float *transform_out; size_t bytes_transform_out;
- float *gamut_out;size_t bytes_gamut_out;
- float *TsTw; size_t bytes_TsTw;
- float *ctrl_pts; size_t bytes_ctrl_pts;
- float *weights; size_t bytes_weights;
- float*coefs; size_t bytes_coefs;
- float *l2_dist; size_t bytes_l2_dist;
- float *tone_map; size_t bytes_tone_map;
- int row_size; int col_size;
-}
-RootIn;
-*/
-
-
-
-void scale_values(float* input, size_t num_elems) {
-
- __visc__hint(DEVICE);
- __visc__attributes(1, input, 1, input);
-
- for (int ind = 0; ind < num_elems; ind++){
- input[ind] = input[ind] * 2.0;
- }
-
- __visc__return(1, num_elems);
-}
-
-
-
-
-void graphRoot(/*0*/ float* input, /*1*/ size_t bytes_input,
- /*2*/ float* result, /*3*/ size_t bytes_result) {
-
- //Specifies compilation target for current node
- __visc__hint(CPU_TARGET);
-
- __visc__attributes(2, input, result, 2, input, result);
-
- // Create an 0D (specified by 1st argument) HPVM node - so a single node
- // associated with node function ---_fxp_wrapper
-
- void* scaleNode = __visc__createNodeND(0, scale_values);
-
- // BindIn binds inputs of current node with specified node
- // - destination node
- // - argument position in argument list of function of source node
- // - argument position in argument list of function of destination node
- // - streaming (1) or non-streaming (0)
-
- // Edge transfers data between nodes within the same level of hierarchy.
- // - source and destination dataflow nodes
- // - edge type, all-all (1) or one-one(0)
- // - source position (in output struct of source node)
- // - destination position (in argument list of destination node)
- // - streaming (1) or non-streaming (0)
-
- // scale_fxp inputs
- __visc__bindIn(scaleNode, 0, 0, 0); // input -> ScNode:input
- __visc__bindIn(scaleNode, 1, 1, 0); // bytes_input -> ScNode:bytes_input
-
- // Similar to bindIn, but for the output. Output of a node is a struct, and
- // we consider the fields in increasing ordering.
- __visc__bindOut(scaleNode, 0, 0, 0);
-
-}
-
-
-
-
-
-int main(int argc, char* argv[]) {
-
- size_t input_size = 100;
- size_t result_size = 100;
-
- size_t input_bytes = input_size * sizeof(float);
- size_t result_bytes = result_size * sizeof(float);
-
- // This is host_input in cam_pipe()
- float* input = (float*) malloc(input_bytes);
- for(unsigned int i = 0; i < input_size; i++){
- input[i] = 1.0;
- }
- // This is host_result in cam_pipe()
- float* result = (float*) malloc(result_bytes);
-
-
- __visc__init();
-
- RootIn* rootArgs = (RootIn*) malloc(sizeof(RootIn));
-
- // Set up HPVM DFG inputs in the rootArgs struct.
- rootArgs->input = input;
- rootArgs->bytes_input = input_size;
-
- printf("input = %d input_bytes = %d \n", input, input_bytes);
-
- rootArgs->result = result;
- rootArgs->bytes_result = result_size;
-
-
- llvm_visc_track_mem(input, input_bytes);
- llvm_visc_track_mem(result, result_bytes);
-
-
- void* testDFG = __visc__launch(0, graphRoot, (void*) rootArgs);
- __visc__wait(testDFG);
-
-
- printf("input = %d \n", input);
-
- llvm_visc_request_mem(input, input_bytes);
- //llvm_visc_request_mem(result, result_bytes);
-
- printf("requested mem \n");
-
- for(unsigned int i = 0; i < input_size; i++){
- printf("input[%d] = %f \n", i, input[i]);
- }
-
- //llvm_visc_untrack_mem(input);
- //llvm_visc_untrack_mem(result);
-
- printf ("untracked mem \n");
-
- __visc__cleanup();
-
- printf ("cleaned up visc");
-
- return 0;
-}
-
-
-
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/main_old.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/main_old.c
deleted file mode 100644
index ea42ad0bf87fd8e0b337ea1e7d0ad803025e849e..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/main_old.c
+++ /dev/null
@@ -1,865 +0,0 @@
-#include <argp.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <assert.h>
-#include <string.h>
-#include <math.h>
-#include "utility.h"
-
-#include "cam_pipe_utility.h"
-#include "pipe_stages.h"
-#include "load_cam_model.h"
-
-#include "visc.h"
-
-int NUM_TEST_CASES;
-int NUM_CLASSES;
-int INPUT_DIM;
-int NUM_WORKER_THREADS;
-
-// Type of struct that is used to pass arguments to the HPVM dataflow graph
-// using the hpvm launch operation
-typedef struct __attribute__((__packed__)) {
- uint8_t *input; size_t bytes_input;
- uint8_t *result; size_t bytes_result;
- float *input_scaled; size_t bytes_input_scaled;
- float *result_scaled; size_t bytes_result_scaled;
- float *demosaic_out; size_t bytes_demosaic_out;
- float *denoise_out; size_t bytes_denoise_out;
- float *transform_out; size_t bytes_transform_out;
- float *gamut_out;size_t bytes_gamut_out;
- float *TsTw; size_t bytes_TsTw;
- float *ctrl_pts; size_t bytes_ctrl_pts;
- float *weights; size_t bytes_weights;
- float*coefs; size_t bytes_coefs;
- float *l2_dist; size_t bytes_l2_dist;
- float *tone_map; size_t bytes_tone_map;
- int row_size; int col_size;
-}
-RootIn;
-
-typedef enum _argnum {
- RAW_IMAGE_BIN,
- OUTPUT_IMAGE_BIN,
- NUM_REQUIRED_ARGS,
- DATA_FILE = NUM_REQUIRED_ARGS,
- NUM_ARGS,
-} argnum;
-
-typedef struct _arguments {
- char* args[NUM_ARGS];
- int num_inputs;
- int num_threads;
-} arguments;
-
-static char prog_doc[] = "\nCamera pipeline on gem5-Aladdin.\n";
-static char args_doc[] = "path/to/raw-image-binary path/to/output-image-binary";
-static struct argp_option options[] = {
- { "num-inputs", 'n', "N", 0, "Number of input images" }, { 0 },
- { "data-file", 'f', "F", 0,
- "File to read data and weights from (if data-init-mode == READ_FILE or "
- "save-params is true). *.txt files are decoded as text files, while "
- "*.bin files are decoded as binary files." },
-};
-
-static error_t parse_opt(int key, char* arg, struct argp_state* state) {
- arguments* args = (arguments*)(state->input);
- switch (key) {
- case 'n': {
- args->num_inputs = strtol(arg, NULL, 10);
- break;
- }
- case 'f': {
- args->args[DATA_FILE] = arg;
- break;
- }
- case 't': {
- args->num_threads = strtol(arg, NULL, 10);
- break;
- }
- case ARGP_KEY_ARG: {
- if (state->arg_num >= NUM_REQUIRED_ARGS)
- argp_usage(state);
- args->args[state->arg_num] = arg;
- break;
- }
- case ARGP_KEY_END: {
- if (state->arg_num < NUM_REQUIRED_ARGS) {
- fprintf(stderr,
- "Not enough arguments! Got %d, require %d.\n",
- state->arg_num,
- NUM_REQUIRED_ARGS);
- argp_usage(state);
- }
- break;
- }
- default:
- return ARGP_ERR_UNKNOWN;
- }
- return 0;
-}
-
-void set_default_args(arguments* args) {
- args->num_inputs = 1;
- args->num_threads = 0;
- for (int i = 0; i < NUM_ARGS; i++) {
- args->args[i] = NULL;
- }
-}
-
-static struct argp parser = { options, parse_opt, args_doc, prog_doc };
-
-// Helper function for printing intermediate results
-void descale_cpu(float *input, size_t bytes_input,
- uint8_t *output, size_t bytes_result,
- int row_size, int col_size) {
-
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++) {
- int index = (chan*row_size + row) * col_size + col;
- output[index] = min(max(input[index] * 255, 0), 255);
- }
-}
-
-static void sort(float arr[], int n) {
- int i, j;
- for (i = 0; i < n - 1; i++)
- for (j = 0; j < n - i - 1; j++)
- if (arr[j] > arr[j + 1]) {
- float temp = arr[j];
- arr[j] = arr[j + 1];
- arr[j + 1] = temp;
- }
-}
-
-/**************************************************************/
-/*** HPVM Leaf node Functions - Performing the computations ***/
-/**************************************************************/
-
-// In this benchmark, no use of HPVM query intrinsics in the leaf node functions
-
-// Leaf HPVM node function for scale
-void scale_fxp(uint8_t *input, size_t bytes_input,
- float *output, size_t bytes_output,
- int row_size, int col_size) {
-
- //Specifies compilation target for current node
- __visc__hint(DEVICE);
-
- // Specifies pointer arguments that will be used as "in" and "out" arguments
- // - count of "in" arguments
- // - list of "in" argument , and similar for "out"
- __visc__attributes(2, input, output, 1, output);
-
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++){
- int index = (chan*row_size + row) * col_size + col;
- output[index] = input[index] * 1.0 / 255;
- }
- __visc__return(1, bytes_output);
-}
-
-// Leaf HPVM node function for descale
-void descale_fxp(float *input, size_t bytes_input,
- uint8_t *output, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, output, 1, output);
-
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++) {
- int index = (chan*row_size + row) * col_size + col;
- output[index] = min(max(input[index] * 255, 0), 255);
- }
- __visc__return(1, bytes_result);
-}
-
-// Leaf HPVM node function for demosaicing
-void demosaic_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, result, 1, result);
-
- for (int row = 1; row < row_size - 1; row++)
- for (int col = 1; col < col_size - 1; col++) {
- int index_0 = (0 * row_size + row) * col_size + col;
- int index_1 = (1 * row_size + row) * col_size + col;
- int index_2 = (2 * row_size + row) * col_size + col;
- if (row % 2 == 0 && col % 2 == 0) {
- // Green pixel
- // Getting the R values
- float R1 = input[index_0 - 1];
- float R2 = input[index_0 + 1];
- // Getting the B values
- float B1 = input[index_2 - col_size];
- float B2 = input[index_2 + col_size];
- // R
- result[index_0] = (R1 + R2) / 2;
- // G
- result[index_1] = input[index_1] * 2;
- // B
- result[index_2] = (B1 + B2) / 2;
- } else if (row % 2 == 0 && col % 2 == 1) {
- // Red pixel
- // Getting the G values
- float G1 = input[index_1 - col_size];
- float G2 = input[index_1 + col_size];
- float G3 = input[index_1 - 1];
- float G4 = input[index_1 + 1];
- // Getting the B values
- float B1 = input[index_2 - col_size - 1];
- float B2 = input[index_2 - col_size + 1];
- float B3 = input[index_2 + col_size - 1];
- float B4 = input[index_2 + col_size + 1];
- // R
- result[index_0] = input[index_0];
- // G
- result[index_1] = (G1 + G2 + G3 + G4) / 2;
- // B (center pixel)
- result[index_2] = (B1 + B2 + B3 + B4) / 4;
- } else if (row % 2 == 1 && col % 2 == 0) {
- // Blue pixel
- // Getting the R values
- float R1 = input[index_0 - col_size - 1];
- float R2 = input[index_0 + col_size - 1];
- float R3 = input[index_0 - col_size + 1];
- float R4 = input[index_0 + col_size + 1];
- // Getting the G values
- float G1 = input[index_1 - col_size];
- float G2 = input[index_1 + col_size];
- float G3 = input[index_1 - 1];
- float G4 = input[index_1 + 1];
- // R
- result[index_0] = (R1 + R2 + R3 + R4) / 4;
- // G
- result[index_1] = (G1 + G2 + G3 + G4) / 2;
- // B
- result[index_2] = input[index_2];
- } else {
- // Bottom Green pixel
- // Getting the R values
- float R1 = input[index_0 - col_size];
- float R2 = input[index_0 + col_size];
- // Getting the B values
- float B1 = input[index_2 - 1];
- float B2 = input[index_2 + 1];
- // R
- result[index_0] = (R1 + R2) / 2;
- // G
- result[index_1] = input[index_1] * 2;
- // B
- result[index_2] = (B1 + B2) / 2;
- }
- }
- __visc__return(1, bytes_result);
-}
-
-// Leaf HPVM node function for denoise
-void denoise_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, result, 1, result);
-
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++)
- if (row >= 1 && row < row_size - 1 && col >= 1 && col < col_size - 1) {
- float filter[9];
- for (int i = -1; i < 2; i++)
- for (int j = -1; j < 2; j++) {
- int index = ((i+row) - row + 1) * 3 + (j+col) - col + 1;
- filter[index] = input[(chan * row_size + (i + row)) * col_size + (j + col)];
- }
- sort(filter, 9);
- result[(chan * row_size + row) * col_size + col] = filter[4];
- } else {
- result[(chan * row_size + row) * col_size + col] = input[(chan * row_size + row) * col_size + col];
- }
- __visc__return(1, bytes_result);
-}
-
-// Leaf HPVM node function, for color map and white balance transform
-void transform_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *TsTw_tran, size_t bytes_TsTw,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(3, input, result, TsTw_tran, 1, result);
-
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++) {
- int index = (chan * row_size + row) * col_size + col;
- int index_0 = (0 * row_size + row) * col_size + col;
- int index_1 = (1 * row_size + row) * col_size + col;
- int index_2 = (2 * row_size + row) * col_size + col;
- int index_2d_0 = 0 * CHAN_SIZE + chan;
- int index_2d_1 = 1 * CHAN_SIZE + chan;
- int index_2d_2 = 2 * CHAN_SIZE + chan;
- result[index] =
- max(input[index_0] * TsTw_tran[index_2d_0] +
- input[index_1] * TsTw_tran[index_2d_1] +
- input[index_2] * TsTw_tran[index_2d_2],
- 0);
- }
- __visc__return(1, bytes_result);
-}
-
-// Leaf HPVM node function, for gamut mapping
-void gamut_map_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *ctrl_pts, size_t bytes_ctrl_pts,
- float *weights, size_t bytes_weights,
- float *coefs, size_t bytes_coefs,
- float *l2_dist, size_t bytes_l2_dist,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(6, input, result, ctrl_pts, weights, coefs, l2_dist, 2, result, l2_dist);
-
- // First, get the L2 norm from every pixel to the control points,
- // Then, sum it and weight it. Finally, add the bias.
-
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++) {
- for (int cp = 0; cp < 3702; cp++) {
- int index_0 = (0 * row_size + row) * col_size + col;
- int index_1 = (1 * row_size + row) * col_size + col;
- int index_2 = (2 * row_size + row) * col_size + col;
- float val1 = (input[index_0] - ctrl_pts[cp * 3 + 0]);
- float val2 = (input[index_0] - ctrl_pts[cp * 3 + 0]);
- float val3 = (input[index_1] - ctrl_pts[cp * 3 + 1]);
- float val4 = (input[index_1] - ctrl_pts[cp * 3 + 1]);
- float val5 = (input[index_2] - ctrl_pts[cp * 3 + 2]);
- float val6 = (input[index_2] - ctrl_pts[cp * 3 + 2]);
- float val = val1 * val2 + val3 * val4 + val5 * val6;
- float sqrt_val = sqrt(val);
- l2_dist[cp] = sqrt_val;
- }
- for (int chan = 0; chan < CHAN_SIZE; chan++) {
- float chan_val = 0.0;
- for (int cp = 0; cp < 3702; cp++) {
- chan_val += l2_dist[cp] * weights[cp * CHAN_SIZE + chan];
- }
- chan_val += coefs[0 * CHAN_SIZE + chan] +
- coefs[1 * CHAN_SIZE + chan] * input[(0 * row_size + row) * col_size + col] +
- coefs[2 * CHAN_SIZE + chan] * input[(1 * row_size + row) * col_size + col] +
- coefs[3 * CHAN_SIZE + chan] * input[(2 * row_size + row) * col_size + col];
- result[(chan * row_size + row) * col_size + col] = max(chan_val, 0);
- }
- }
- __visc__return(1, bytes_result);
-}
-
-// HPVM leaf node function, for tone mapping
-void tone_map_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *tone_map, size_t bytes_tone_map,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(3, input, result, tone_map, 1, result);
-
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- for (int row = 0; row < row_size; row++)
- for (int col = 0; col < col_size; col++) {
- int index = (chan * row_size + row) * col_size + col;
- uint8_t x = input[index] * 255;
- result[index] = tone_map[x * CHAN_SIZE + chan];
- }
- __visc__return(1, bytes_result);
-}
-
-/********************************************************************/
-/*** HPVM Internal node Functions - Determine the graph structure ***/
-/********************************************************************/
-
-// We create a wrapper node per leaf node - this is an implementation
-// requirement for the FPGA backend . The CPU backend also supports this,
-// so it does not cause a portability issue.
-
-void scale_fxp_wrapper(uint8_t *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(2, input, result, 1, result);
-
- // Create an 1D (specified by 1st argument) HPVM node with 1 dynamic
- // instance (last argument) associated with node function scale_fxp
- void *ScaleNode = __visc__createNodeND(1, scale_fxp, (size_t)1);
-
- // Binds inputs of current node with specified node
- // - destination node
- // - argument position in argument list of function of source node
- // - argument position in argument list of function of destination node
- // - streaming (1) or non-streaming (0)
- __visc__bindIn(ScaleNode, 0, 0, 0); // bind input
- __visc__bindIn(ScaleNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(ScaleNode, 2, 2, 0); // bind result
- __visc__bindIn(ScaleNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(ScaleNode, 4, 4, 0); // bind row_size
- __visc__bindIn(ScaleNode, 5, 5, 0); // bind col_size
-
- // Similar to bindIn, but for the output. Output of a node is a struct, and
- // we consider the fields in increasing ordering.
- __visc__bindOut(ScaleNode, 0, 0, 0);
-}
-
-void descale_fxp_wrapper(float *input, size_t bytes_input,
- uint8_t *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(2, input, result, 1, result);
- void *DescaleNode = __visc__createNodeND(1, descale_fxp, (size_t)1);
- __visc__bindIn(DescaleNode, 0, 0, 0); // bind input
- __visc__bindIn(DescaleNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(DescaleNode, 2, 2, 0); // bind result
- __visc__bindIn(DescaleNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(DescaleNode, 4, 4, 0); // bind row_size
- __visc__bindIn(DescaleNode, 5, 5, 0); // bind col_size
-
- __visc__bindOut(DescaleNode, 0, 0, 0);
-}
-
-void demosaic_fxp_wrapper(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(2, input, result, 1, result);
- void *DemosaicNode = __visc__createNodeND(1, demosaic_fxp, (size_t)1);
- __visc__bindIn(DemosaicNode, 0, 0, 0); // bind input
- __visc__bindIn(DemosaicNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(DemosaicNode, 2, 2, 0); // bind result
- __visc__bindIn(DemosaicNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(DemosaicNode, 4, 4, 0); // bind row_size
- __visc__bindIn(DemosaicNode, 5, 5, 0); // bind col_size
-
- __visc__bindOut(DemosaicNode, 0, 0, 0);
-}
-
-void denoise_fxp_wrapper(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(2, input, result, 1, result);
- void *DenoiseNode = __visc__createNodeND(1, denoise_fxp, (size_t)1);
- __visc__bindIn(DenoiseNode, 0, 0, 0); // bind input
- __visc__bindIn(DenoiseNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(DenoiseNode, 2, 2, 0); // bind result
- __visc__bindIn(DenoiseNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(DenoiseNode, 4, 4, 0); // bind row_size
- __visc__bindIn(DenoiseNode, 5, 5, 0); // bind col_size
-
- __visc__bindOut(DenoiseNode, 0, 0, 0);
-}
-
-void transform_fxp_wrapper(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *TsTw_tran, size_t bytes_TsTw,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(3, input, result, TsTw_tran, 1, result);
- void *TransformNode = __visc__createNodeND(1, transform_fxp, (size_t)1);
- __visc__bindIn(TransformNode, 0, 0, 0); // bind input
- __visc__bindIn(TransformNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(TransformNode, 2, 2, 0); // bind result
- __visc__bindIn(TransformNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(TransformNode, 4, 4, 0); // bind tstw
- __visc__bindIn(TransformNode, 5, 5, 0); // bind bytes_tstw
- __visc__bindIn(TransformNode, 6, 6, 0); // bind row_size
- __visc__bindIn(TransformNode, 7, 7, 0); // bind col_size
-
- __visc__bindOut(TransformNode, 0, 0, 0);
-}
-
-void gamut_fxp_wrapper(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *ctrl_pts, size_t bytes_ctrl_pts,
- float *weights, size_t bytes_weights,
- float *coefs, size_t bytes_coefs,
- float *l2_dist, size_t bytes_l2_dist,
- int row_size, int col_size) {
- __visc__hint(CPU_TARGET);
- __visc__attributes(6, input, result, ctrl_pts, weights, coefs, l2_dist, 1, result);
- void *GamutNode = __visc__createNodeND(1, gamut_map_fxp, (size_t)1);
- __visc__bindIn(GamutNode, 0, 0, 0); // bind input
- __visc__bindIn(GamutNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(GamutNode, 2, 2, 0); // bind result
- __visc__bindIn(GamutNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(GamutNode, 4, 4, 0); // bind ctrl_pts
- __visc__bindIn(GamutNode, 5, 5, 0); // bind bytes_ctrl_pts
- __visc__bindIn(GamutNode, 6, 6, 0); // bind weights
- __visc__bindIn(GamutNode, 7, 7, 0); // bind bytes_weights
- __visc__bindIn(GamutNode, 8, 8, 0); // bind coefs
- __visc__bindIn(GamutNode, 9, 9, 0); // bind bytes_coefs
- __visc__bindIn(GamutNode, 10, 10, 0); // bind l2_dist
- __visc__bindIn(GamutNode, 11, 11, 0); // bind bytes_l2_dist
- __visc__bindIn(GamutNode, 12, 12, 0); // bind row_size
- __visc__bindIn(GamutNode, 13, 13, 0); // bind col_size
-
- __visc__bindOut(GamutNode, 0, 0, 0);
-}
-void tone_map_fxp_wrapper(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *tone_map, size_t bytes_tone_map,
- int row_size, int col_size) {
-
- __visc__hint(CPU_TARGET);
- __visc__attributes(3, input, result, tone_map, 1, result);
- void *ToneMapNode = __visc__createNodeND(1, tone_map_fxp, (size_t)1);
- __visc__bindIn(ToneMapNode, 0, 0, 0); // bind input
- __visc__bindIn(ToneMapNode, 1, 1, 0); // bind bytes_input
- __visc__bindIn(ToneMapNode, 2, 2, 0); // bind result
- __visc__bindIn(ToneMapNode, 3, 3, 0); // bind bytes_result
- __visc__bindIn(ToneMapNode, 4, 4, 0); // bind tone_map
- __visc__bindIn(ToneMapNode, 5, 5, 0); // bind bytes_tone_map
- __visc__bindIn(ToneMapNode, 6, 6, 0); // bind row_size
- __visc__bindIn(ToneMapNode, 7, 7, 0); // bind col_size
-
- __visc__bindOut(ToneMapNode, 0, 0, 0);
-}
-
-
-/*** ROOT Node - Top Level of the Graph Hierarchy ***/
-void CamPipeRoot(/*0*/ uint8_t *input, /*1*/ size_t bytes_input,
- /*2*/ uint8_t *result, /*3*/ size_t bytes_result,
- /*4*/ float *input_scaled, /*5*/ size_t bytes_input_scaled,
- /*6*/ float *result_scaled, /*7*/ size_t bytes_result_scaled,
- /*8*/ float *demosaic_out, /*9*/ size_t bytes_demosaic_out,
- /*10*/ float *denoise_out, /*11*/ size_t bytes_denoise_out,
- /*12*/ float *transform_out, /*13*/ size_t bytes_transform_out,
- /*14*/ float *gamut_out, /*15*/ size_t bytes_gamut_out,
- /*16*/ float *TsTw, /*17*/ size_t bytes_TsTw,
- /*18*/ float *ctrl_pts, /*19*/ size_t bytes_ctrl_pts,
- /*20*/ float *weights, /*21*/ size_t bytes_weights,
- /*22*/ float*coefs, /*23*/ size_t bytes_coefs,
- /*24*/ float *l2_dist, /*25*/ size_t bytes_l2_dist,
- /*26*/ float *tone_map, /*27*/ size_t bytes_tone_map,
- /*28*/ int row_size, /*29*/ int col_size) {
-
- //Specifies compilation target for current node
- __visc__hint(CPU_TARGET);
-
- // Specifies pointer arguments that will be used as "in" and "out" arguments
- // - count of "in" arguments
- // - list of "in" argument , and similar for "out"
- __visc__attributes(14, input, result, input_scaled, result_scaled, demosaic_out, denoise_out,
- transform_out, gamut_out, TsTw, ctrl_pts, weights, coefs, tone_map, l2_dist,
- 5, result, demosaic_out, denoise_out, transform_out, gamut_out);
-
- // Create an 0D (specified by 1st argument) HPVM node - so a single node
- // associated with node function ---_fxp_wrapper
- void* ScNode = __visc__createNodeND(0, scale_fxp_wrapper);
- void* DmNode = __visc__createNodeND(0, demosaic_fxp_wrapper);
- void *DnNode = __visc__createNodeND(0, denoise_fxp_wrapper);
- void *TrNode = __visc__createNodeND(0, transform_fxp_wrapper);
- void *GmNode = __visc__createNodeND(0, gamut_fxp_wrapper);
- void *TnNode = __visc__createNodeND(0, tone_map_fxp_wrapper);
- void *DsNode = __visc__createNodeND(0, descale_fxp_wrapper);
-
- // BindIn binds inputs of current node with specified node
- // - destination node
- // - argument position in argument list of function of source node
- // - argument position in argument list of function of destination node
- // - streaming (1) or non-streaming (0)
-
- // Edge transfers data between nodes within the same level of hierarchy.
- // - source and destination dataflow nodes
- // - edge type, all-all (1) or one-one(0)
- // - source position (in output struct of source node)
- // - destination position (in argument list of destination node)
- // - streaming (1) or non-streaming (0)
-
- // scale_fxp inputs
- __visc__bindIn(ScNode, 0, 0, 0); // input -> ScNode:input
- __visc__bindIn(ScNode, 1, 1, 0); // bytes_input -> ScNode:bytes_input
- __visc__bindIn(ScNode, 4, 2, 0); // input_scaled -> ScNode:result
- __visc__bindIn(ScNode, 5, 3, 0); // bytes_input_scaled -> ScNode:bytes_result
- __visc__bindIn(ScNode, 28, 4, 0); // row_size -> ScNode:row_size
- __visc__bindIn(ScNode, 29, 5, 0); // col_size -> ScNode:col_size
-
- // demosaic_fxp inputs
- __visc__bindIn(DmNode, 4, 0, 0); // input_scaled -> DmNode:input
- __visc__edge(ScNode, DmNode, 1, 0, 1, 0); // SCNode:bytes_result -> DmNode:bytes_input
- __visc__bindIn(DmNode, 8, 2, 0); // demosaic_out -> DmNode:result
- __visc__bindIn(DmNode, 9, 3, 0); // bytes_demosaic_out -> DmNode:bytes_result
- __visc__bindIn(DmNode, 28, 4, 0); // row_size -> DmNode:row_size
- __visc__bindIn(DmNode, 29, 5, 0); // col_size -> DmNode:col_size
-
- // denoise_fxp inputs
- __visc__bindIn(DnNode, 8, 0, 0); // demosaic_out -> DnNode:input
- __visc__edge(DmNode, DnNode, 1, 0, 1, 0); // DMNode:bytes_result -> DnNode:bytes_input
- __visc__bindIn(DnNode, 10, 2, 0); // denoise_out -> DnNode:result
- __visc__bindIn(DnNode, 11, 3, 0); // bytes_denoise_out -> DnNode:bytes_result
- __visc__bindIn(DnNode, 28, 4, 0); // row_size -> DnNode:row_size
- __visc__bindIn(DnNode, 29, 5, 0); // col_size -> DnNode:col_size
-
- // transform_fxp inputs
- __visc__bindIn(TrNode, 10, 0, 0); // denoise_out -> TrNode:input
- __visc__edge(DnNode, TrNode, 1, 0, 1, 0); // DnNode:bytes_result -> TrNode:bytes_input
- __visc__bindIn(TrNode, 12, 2, 0); // transform_out -> TrNode:result
- __visc__bindIn(TrNode, 13, 3, 0); // bytes_result_scaled -> TrNode:bytes_result
- __visc__bindIn(TrNode, 16, 4, 0); // TsTw -> TrNode:TsTw_trann
- __visc__bindIn(TrNode, 17, 5, 0); // bytes_TsTw -> TrNode:bytes_TsTw
- __visc__bindIn(TrNode, 28, 6, 0); // row_size -> TrNode:row_size
- __visc__bindIn(TrNode, 29, 7, 0); // col_size -> TrNode:col_size
-
- // gamut_fxp inputs
- __visc__bindIn(GmNode, 12, 0, 0); // transform_out -> GmNode:input
- __visc__edge(TrNode, GmNode, 1, 0, 1, 0); // TrNode:bytes_result -> GmNode:bytes_input
- __visc__bindIn(GmNode, 14, 2, 0); // gamut_out -> GmNode:result
- __visc__bindIn(GmNode, 15, 3, 0); // bytes_gamut_out -> GmNode:bytes_result
- __visc__bindIn(GmNode, 18, 4, 0); // ctrl_pts -> GmNode:ctrl_pts
- __visc__bindIn(GmNode, 19, 5, 0); // bytes_ctrl_pts -> GmNode:bytes_ctrl_pts
- __visc__bindIn(GmNode, 20, 6, 0); // weights -> GmNode:weights
- __visc__bindIn(GmNode, 21, 7, 0); // bytes_weights -> GmNode:bytes_weights
- __visc__bindIn(GmNode, 22, 8, 0); // coefs -> GmNode:coefs
- __visc__bindIn(GmNode, 23, 9, 0); // bytes_coefs -> GmNode:bytes_coefs
- __visc__bindIn(GmNode, 24, 10, 0); // l2_dist -> GmNode: l2_dist
- __visc__bindIn(GmNode, 25, 11, 0); // bytes_l2_dist -> GmNode:bytes_l2_dist
- __visc__bindIn(GmNode, 28, 12, 0); // row_size -> GmNode:row_size
- __visc__bindIn(GmNode, 29, 13, 0); // col_size -> GmNode:col_size
-
- // tone_map_fxp inputs
- __visc__bindIn(TnNode, 14, 0, 0); // gamut_out -> TnNode:input
- __visc__edge(GmNode, TnNode, 1, 0, 1, 0); // GmNode:bytes_result -> TnNode:bytes_input
- __visc__bindIn(TnNode, 6, 2, 0); // result_scaled -> TnNode:result
- __visc__bindIn(TnNode, 7, 3, 0); // bytes_result_scaled -> TnNode:bytes_result
- __visc__bindIn(TnNode, 26, 4, 0); // tone_map -> TnNode:tone_map
- __visc__bindIn(TnNode, 27, 5, 0); // bytes_tone_map -> TnNode:bytes_tone_map
- __visc__bindIn(TnNode, 28, 6, 0); // row_size -> TnNode:row_size
- __visc__bindIn(TnNode, 29, 7, 0); // col_size -> TnNode:col_size
-
- // descale_fxp inputs
- __visc__bindIn(DsNode, 6, 0, 0); // result_scaled -> DsNode:input
- __visc__edge(TnNode, DsNode, 1, 0, 1, 0); // TnNode:bytes_result -> DsNode:bytes_input
- __visc__bindIn(DsNode, 2, 2, 0); // result -> DsNode:result
- __visc__bindIn(DsNode, 3, 3, 0); // bytes_result -> DsNode:bytes_result
- __visc__bindIn(DsNode, 28, 4, 0); // row_size -> DsNode:row_size
- __visc__bindIn(DsNode, 29, 5, 0); // col_size -> DsNode:col_size
-
- // Similar to bindIn, but for the output. Output of a node is a struct, and
- // we consider the fields in increasing ordering.
- __visc__bindOut(DsNode, 0, 0, 0);
-
-}
-
-int main(int argc, char* argv[]) {
- // Parse the arguments.
- arguments args;
- set_default_args(&args);
- argp_parse(&parser, argc, argv, 0, 0, &args);
-
- // Read a raw image.
- // NOTE: We deliberately perform this file I/O outside of the kernel.
- printf("Reading a raw image from %s\n", args.args[RAW_IMAGE_BIN]);
- int row_size, col_size;
- uint8_t *image_in = read_image_from_binary(args.args[RAW_IMAGE_BIN], &row_size, &col_size);
-
- printf("Raw image shape: %d x %d x %d\n", row_size, col_size, CHAN_SIZE);
-
- // Allocate a buffer for storing the output image data.
- // (This is currently the same size as the input image data.)
- size_t bytes_image = sizeof(uint8_t) * row_size * col_size * CHAN_SIZE;
- size_t bytes_fimage = sizeof(float) * row_size * col_size * CHAN_SIZE;
- uint8_t *image_out = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t *image_out_gamut = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t *image_out_demosaic = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t *image_out_denoise = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t *image_out_transform = (uint8_t*) malloc_aligned(bytes_image);
-
- __visc__init();
-
- ///////////////////////////////////////////////////////////////
- // Camera Model Parameters
- ///////////////////////////////////////////////////////////////
- // Path to the camera model to be used
-// char cam_model_path[100];
-// char cam_model_path = "cam_models/NikonD7000/";
- // White balance index (select white balance from transform file)
- // The first white balance in the file has a wb_index of 1
- // For more information on model format see the readme
- int wb_index = 6;
-
- // Number of control points
- int num_ctrl_pts = 3702;
- uint8_t *input, *result;
- float *input_scaled, *result_scaled, *demosaic_out, *denoise_out, *transform_out, *gamut_out;
- float *TsTw, *ctrl_pts, *weights, *coefs, *tone_map, *l2_dist;
-
- TsTw = get_TsTw("cam_models/NikonD7000/", wb_index);
- float *trans = transpose_mat(TsTw, CHAN_SIZE, CHAN_SIZE);
- free(TsTw);
- TsTw = trans;
- ctrl_pts = get_ctrl_pts("cam_models/NikonD7000/", num_ctrl_pts);
- weights = get_weights("cam_models/NikonD7000/", num_ctrl_pts);
- coefs = get_coefs("cam_models/NikonD7000/", num_ctrl_pts);
- tone_map = get_tone_map("cam_models/NikonD7000/");
-
- input_scaled = (float*) malloc_aligned(bytes_fimage);
- result_scaled = (float*) malloc_aligned(bytes_fimage);
- demosaic_out = (float*) malloc_aligned(bytes_fimage);
- denoise_out = (float*) malloc_aligned(bytes_fimage);
- transform_out = (float*) malloc_aligned(bytes_fimage);
- gamut_out = (float*) malloc_aligned(bytes_fimage);
- l2_dist = (float*) malloc_aligned(sizeof(float) * num_ctrl_pts);
-
- // This is host_input in cam_pipe()
- input = (uint8_t*) malloc_aligned(bytes_image);
- convert_hwc_to_chw(image_in, row_size, col_size, &input);
-
- // This is host_result in cam_pipe()
- result = (uint8_t*) malloc_aligned(bytes_image);
-
- // Allocate struct to pass DFG inputs
- RootIn* rootArgs = (RootIn*) malloc(sizeof(RootIn));
-
- // Set up HPVM DFG inputs in the rootArgs struct.
- rootArgs->input = input;
- rootArgs->bytes_input = bytes_image;
-
- rootArgs->result = result;
- rootArgs->bytes_result = bytes_image;
-
- rootArgs->input_scaled = input_scaled;
- rootArgs->bytes_input_scaled = bytes_fimage;
-
- rootArgs->result_scaled = result_scaled;
- rootArgs->bytes_result_scaled = bytes_fimage;
-
- rootArgs->demosaic_out = demosaic_out;
- rootArgs->bytes_demosaic_out = bytes_fimage;
-
- rootArgs->denoise_out = denoise_out;
- rootArgs->bytes_denoise_out = bytes_fimage;
-
- rootArgs->transform_out = transform_out;
- rootArgs->bytes_transform_out = bytes_fimage;
-
- rootArgs->gamut_out = gamut_out;
- rootArgs->bytes_gamut_out = bytes_fimage;
-
- rootArgs->TsTw = TsTw;
- rootArgs->bytes_TsTw = CHAN_SIZE * CHAN_SIZE * sizeof(float);
-
- rootArgs->ctrl_pts = ctrl_pts;
- rootArgs->bytes_ctrl_pts = num_ctrl_pts * CHAN_SIZE * sizeof(float);
-
- rootArgs->weights = weights;
- rootArgs->bytes_weights = num_ctrl_pts * CHAN_SIZE * sizeof(float);
-
- rootArgs->coefs = coefs;
- rootArgs->bytes_coefs = 4 * CHAN_SIZE * sizeof(float);
-
- rootArgs->tone_map = tone_map;
- rootArgs->bytes_tone_map = 256 * CHAN_SIZE * sizeof(float);
-
- rootArgs->l2_dist = l2_dist;
- rootArgs->bytes_l2_dist = num_ctrl_pts * sizeof(float);
-
- rootArgs->row_size = row_size;
- rootArgs->col_size = col_size;
-
- // Memory tracking is required for pointer arguments.
- // Nodes can be scheduled on different targets, and
- // dataflow edge implementation needs to request data.
- // The pair (pointer, size) is inserted in memory tracker using this call
- llvm_visc_track_mem(input, bytes_image);
- llvm_visc_track_mem(result, bytes_image);
- llvm_visc_track_mem(input_scaled, bytes_fimage);
- llvm_visc_track_mem(result_scaled, bytes_fimage);
- llvm_visc_track_mem(demosaic_out, bytes_fimage);
- llvm_visc_track_mem(denoise_out, bytes_fimage);
- llvm_visc_track_mem(transform_out, bytes_fimage);
- llvm_visc_track_mem(gamut_out, bytes_fimage);
- llvm_visc_track_mem(TsTw, CHAN_SIZE * CHAN_SIZE * sizeof(float));
- llvm_visc_track_mem(ctrl_pts, num_ctrl_pts * CHAN_SIZE * sizeof(float));
- llvm_visc_track_mem(weights, num_ctrl_pts * CHAN_SIZE * sizeof(float));
- llvm_visc_track_mem(coefs, 4 * CHAN_SIZE *sizeof(float));
- llvm_visc_track_mem(tone_map, 256 * CHAN_SIZE * sizeof(float));
- llvm_visc_track_mem(l2_dist, num_ctrl_pts * sizeof(float));
-
- printf("\n\nLaunching CAVA pipeline!\n");
-
- void* camPipeDFG = __visc__launch(0, CamPipeRoot, (void*) rootArgs);
- __visc__wait(camPipeDFG);
-
- printf("\n\nPipeline execution completed!\n");
- printf("\n\nRequesting memory!\n");
-
- // Request data from graph.
- llvm_visc_request_mem(result, bytes_image);
- llvm_visc_request_mem(demosaic_out, bytes_fimage);
- llvm_visc_request_mem(denoise_out, bytes_fimage);
- llvm_visc_request_mem(transform_out, bytes_fimage);
- llvm_visc_request_mem(gamut_out, bytes_fimage);
- printf("\n\nDone requesting memory!\n");
-
-
- uint8_t* gamut_out_descaled = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t* demosaic_out_descaled = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t* transform_out_descaled = (uint8_t*) malloc_aligned(bytes_image);
- uint8_t* denoise_out_descaled = (uint8_t*) malloc_aligned(bytes_image);
-
- descale_cpu(demosaic_out, bytes_fimage, demosaic_out_descaled, bytes_image, row_size, col_size);
- descale_cpu(gamut_out, bytes_fimage, gamut_out_descaled, bytes_image, row_size, col_size);
- descale_cpu(denoise_out, bytes_fimage, denoise_out_descaled, bytes_image, row_size, col_size);
- descale_cpu(transform_out, bytes_fimage, transform_out_descaled, bytes_image, row_size, col_size);
-
- convert_chw_to_hwc(result, row_size, col_size, &image_out);
- convert_chw_to_hwc(gamut_out_descaled, row_size, col_size, &image_out_gamut);
- convert_chw_to_hwc(demosaic_out_descaled, row_size, col_size, &image_out_demosaic);
- convert_chw_to_hwc(denoise_out_descaled, row_size, col_size, &image_out_denoise);
- convert_chw_to_hwc(transform_out_descaled, row_size, col_size, &image_out_transform);
-
-
- // Remove tracked pointers.
- llvm_visc_untrack_mem(input);
- llvm_visc_untrack_mem(result);
- llvm_visc_untrack_mem(input_scaled);
- llvm_visc_untrack_mem(result_scaled);
- llvm_visc_untrack_mem(demosaic_out);
- llvm_visc_untrack_mem(denoise_out);
- llvm_visc_untrack_mem(transform_out);
- llvm_visc_untrack_mem(gamut_out);
-
- llvm_visc_untrack_mem(TsTw);
- llvm_visc_untrack_mem(ctrl_pts);
- llvm_visc_untrack_mem(weights);
- llvm_visc_untrack_mem(coefs);
- llvm_visc_untrack_mem(tone_map);
- llvm_visc_untrack_mem(l2_dist);
-
- // Output the image.
- // NOTE: We deliberately perform this file I/O outside of the kernel.
- char str[50], base_str[50];
- strcpy(base_str, args.args[OUTPUT_IMAGE_BIN]);
- strcpy(str, base_str);
- strcat(str, ".bin");
- printf("Writing output image to %s\n", str);
- write_image_to_binary(str, image_out, row_size, col_size);
- strcpy(str, base_str);
- strcat(str, "_gamut.bin");
- printf("Writing output image to %s\n", str);
- write_image_to_binary(str, image_out_gamut, row_size, col_size);
- strcpy(str, base_str);
- strcat(str, "_demosaic.bin");
- printf("Writing output image to %s\n", str);
- write_image_to_binary(str, image_out_demosaic, row_size, col_size);
- strcpy(str, base_str);
- strcat(str, "_denoise.bin");
- printf("Writing output image to %s\n", str);
- write_image_to_binary(str, image_out_denoise, row_size, col_size);
- strcpy(str, base_str);
- strcat(str, "_transform.bin");
- printf("Writing output image to %s\n", str);
- write_image_to_binary(str, image_out_transform, row_size, col_size);
-
- __visc__cleanup();
-
- return 0;
-}
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/new_main.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/new_main.c
deleted file mode 100644
index e6e36ba1db0d4d2e7806256b4c31e5955917e68c..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/new_main.c
+++ /dev/null
@@ -1,115 +0,0 @@
-
-
-#include <stdlib.h>
-
-
-typedef struct __attribute__((__packed__)) {
- float* input; size_t bytes_input;
- float* result; size_t bytes_result;
-}
-RootIn;
-
-
-
-
-void scale_values(float* input, size_t bytes_input) {
-
- __visc__hint(DEVICE);
- __visc__attributes(1, input, 1, input);
-
- for (int ind = 0; ind < bytes_input; ind++){
- input[ind] = input[ind] * 2.0;
- }
-
- __visc__return(1, bytes_input);
-}
-
-
-
-
-void graphRoot(/*0*/ float* input, /*1*/ size_t bytes_input,
- /*2*/ float* result, /*3*/ size_t bytes_result) {
-
- //Specifies compilation target for current node
- __visc__hint(CPU_TARGET);
-
- __visc__attributes(2, input, result, 2, input, result);
-
- // Create an 0D (specified by 1st argument) HPVM node - so a single node
- // associated with node function ---_fxp_wrapper
-
- void* scaleNode = __visc__createNodeND(0, scale_values);
-
- // BindIn binds inputs of current node with specified node
- // - destination node
- // - argument position in argument list of function of source node
- // - argument position in argument list of function of destination node
- // - streaming (1) or non-streaming (0)
-
- // Edge transfers data between nodes within the same level of hierarchy.
- // - source and destination dataflow nodes
- // - edge type, all-all (1) or one-one(0)
- // - source position (in output struct of source node)
- // - destination position (in argument list of destination node)
- // - streaming (1) or non-streaming (0)
-
- // scale_fxp inputs
- __visc__bindIn(scaleNode, 0, 0, 0); // input -> ScNode:input
- __visc__bindIn(scaleNode, 1, 1, 0); // bytes_input -> ScNode:bytes_input
-
- // Similar to bindIn, but for the output. Output of a node is a struct, and
- // we consider the fields in increasing ordering.
- __visc__bindOut(scaleNode, 0, 0, 0);
-
-}
-
-
-
-
-
-int main(int argc, char* argv[]) {
-
- __visc__init();
-
- size_t input_size = 100;
- size_t result_size = 100;
-
- size_t input_bytes = input_size * sizeof(float);
- size_t result_bytes = result_size * sizeof(float);
-
- // This is host_input in cam_pipe()
- input = (float*) malloc(input_bytes);
- // This is host_result in cam_pipe()
- result = (float*) malloc(result_bytes);
-
-
- RootIn* rootArgs = (RootIn*) malloc(sizeof(RootIn));
-
- // Set up HPVM DFG inputs in the rootArgs struct.
- rootArgs->input = input;
- rootArgs->bytes_input = input_bytes;
-
- rootArgs->result = result;
- rootArgs->bytes_result = result_bytes;
-
- llvm_visc_track_mem(input, input_bytes);
- llvm_visc_track_mem(result, result_bytes);
-
-
- void* testDFG = __visc__launch(0, graphRoot, (void*) rootArgs);
- __visc__wait(testDFG);
-
-
- llvm_visc_request_mem(result, input_bytes);
- llvm_visc_request_mem(result, result_bytes);
-
-
-
- __visc__cleanup();
-
- return 0;
-}
-
-
-
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/pipe_stages.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/pipe_stages.c
deleted file mode 100644
index 2ebedec936915b5e7f11881c5001c84b6db26474..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/pipe_stages.c
+++ /dev/null
@@ -1,290 +0,0 @@
-#include <stdio.h>
-#include <math.h>
-#include "pipe_stages.h"
-#include "cam_pipe_utility.h"
-
-//void scale_fxp(uint8_t *input, int row_size, int col_size, float *output) {
-void scale_fxp(uint8_t *input, size_t bytes_input,
- float *output, size_t bytes_output,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, output, 1, output);
-
- ARRAY_3D(uint8_t, _input, input, row_size, col_size);
- ARRAY_3D(float, _output, output, row_size, col_size);
- sl_chan:
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- sl_row:
- for (int row = 0; row < row_size; row++)
- sl_col:
- for (int col = 0; col < col_size; col++)
- _output[chan][row][col] = _input[chan][row][col] * 1.0 / 255;
-
- __visc__return(1, bytes_output);
-}
-
-//void descale_fxp(float *input, int row_size, int col_size, uint8_t *output) {
-void descale_fxp(float *input, size_t bytes_input,
- uint8_t *output, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, output, 1, output);
-
- ARRAY_3D(float, _input, input, row_size, col_size);
- ARRAY_3D(uint8_t, _output, output, row_size, col_size);
- dsl_chan:
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- dsl_row:
- for (int row = 0; row < row_size; row++)
- dsl_col:
- for (int col = 0; col < col_size; col++)
- _output[chan][row][col] = min(max(_input[chan][row][col] * 255, 0), 255);
-
- __visc__return(1, bytes_output);
-}
-
-// Demosaicing stage
-// G R
-// B G
-//void demosaic_fxp(float *input, int row_size, int col_size, float *result) {
-void demosaic_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, result, 1, result);
-
- printf("Demosaicing.\n");
- ARRAY_3D(float, _input, input, row_size, col_size);
- ARRAY_3D(float, _result, result, row_size, col_size);
-
- dm_row:
- for (int row = 1; row < row_size - 1; row++)
- dm_col:
- for (int col = 1; col < col_size - 1; col++)
- if (row % 2 == 0 && col % 2 == 0) {
- // Green pixel
- // Getting the R values
- float R1 = _input[0][row][col - 1];
- float R2 = _input[0][row][col + 1];
- // Getting the B values
- float B1 = _input[2][row - 1][col];
- float B2 = _input[2][row + 1][col];
- // R
- _result[0][row][col] = (R1 + R2) / 2;
- // G
- _result[1][row][col] = _input[1][row][col] * 2;
- // B
- _result[2][row][col] = (B1 + B2) / 2;
- } else if (row % 2 == 0 && col % 2 == 1) {
- // Red pixel
- // Getting the G values
- float G1 = _input[1][row - 1][col];
- float G2 = _input[1][row + 1][col];
- float G3 = _input[1][row][col - 1];
- float G4 = _input[1][row][col + 1];
- // Getting the B values
- float B1 = _input[2][row - 1][col - 1];
- float B2 = _input[2][row - 1][col + 1];
- float B3 = _input[2][row + 1][col - 1];
- float B4 = _input[2][row + 1][col + 1];
- // R
- _result[0][row][col] = _input[0][row][col];
- // G
- _result[1][row][col] = (G1 + G2 + G3 + G4) / 2;
- // B (center pixel)
- _result[2][row][col] = (B1 + B2 + B3 + B4) / 4;
- } else if (row % 2 == 1 && col % 2 == 0) {
- // Blue pixel
- // Getting the R values
- float R1 = _input[0][row - 1][col - 1];
- float R2 = _input[0][row + 1][col - 1];
- float R3 = _input[0][row - 1][col + 1];
- float R4 = _input[0][row + 1][col + 1];
- // Getting the G values
- float G1 = _input[1][row - 1][col];
- float G2 = _input[1][row + 1][col];
- float G3 = _input[1][row][col - 1];
- float G4 = _input[1][row][col + 1];
- // R
- _result[0][row][col] = (R1 + R2 + R3 + R4) / 4;
- // G
- _result[1][row][col] = (G1 + G2 + G3 + G4) / 2;
- // B
- _result[2][row][col] = _input[2][row][col];
- } else {
- // Bottom Green pixel
- // Getting the R values
- float R1 = _input[0][row - 1][col];
- float R2 = _input[0][row + 1][col];
- // Getting the B values
- float B1 = _input[2][row][col - 1];
- float B2 = _input[2][row][col + 1];
- // R
- _result[0][row][col] = (R1 + R2) / 2;
- // G
- _result[1][row][col] = _input[1][row][col] * 2;
- // B
- _result[2][row][col] = (B1 + B2) / 2;
- }
-
- __visc__return(1, bytes_result);
-}
-
-static void sort(float arr[], int n) {
- int i, j;
- dn_sort_i:
- for (i = 0; i < n - 1; i++)
- dn_sort_j:
- for (j = 0; j < n - i - 1; j++)
- if (arr[j] > arr[j + 1]) {
- float temp = arr[j];
- arr[j] = arr[j + 1];
- arr[j + 1] = temp;
- }
-}
-
-// Simple denoise
-//void denoise_fxp(float *input, int row_size, int col_size, float *result) {
-void denoise_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(2, input, result, 1, result);
-
- printf("Denoising.\n");
- ARRAY_3D(float, _input, input, row_size, col_size);
- ARRAY_3D(float, _result, result, row_size, col_size);
-
- dn_chan:
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- dn_row:
- for (int row = 0; row < row_size; row++)
- dn_col:
- for (int col = 0; col < col_size; col++)
- if (row >= 1 && row < row_size - 1 && col >= 1 && col < col_size - 1) {
- float filter[9];
- dn_slide_row:
- for (int i = row-1; i < row+2; i++)
- dn_slide_col:
- for (int j = col-1; j < col+2; j++) {
- int index = (i - row + 1) * 3 + j - col + 1;
- filter[index] = _input[chan][i][j];
- }
- sort(filter, 9);
- _result[chan][row][col] = filter[4];
- } else {
- _result[chan][row][col] = _input[chan][row][col];
- }
- __visc__return(1, bytes_result);
-}
-
-// Color map and white balance transform
-//void transform_fxp(float *input, int row_size, int col_size, float *result,
-// float *TsTw_tran) {
-void transform_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *TsTw_tran, size_t bytes_TsTw,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(3, input, result, TsTw_tran, 1, result);
-
- printf("Color mapping.\n");
- ARRAY_3D(float, _input, input, row_size, col_size);
- ARRAY_3D(float, _result, result, row_size, col_size);
- ARRAY_2D(float, _TsTw_tran, TsTw_tran, 3);
-
- tr_chan:
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- tr_row:
- for (int row = 0; row < row_size; row++)
- tr_col:
- for (int col = 0; col < col_size; col++)
- _result[chan][row][col] =
- max(_input[0][row][col] * _TsTw_tran[0][chan] +
- _input[1][row][col] * _TsTw_tran[1][chan] +
- _input[2][row][col] * _TsTw_tran[2][chan],
- 0);
- __visc__return(1, bytes_result);
-}
-
-//
-// Weighted radial basis function for gamut mapping
-//
-//void gamut_map_fxp(float *input, int row_size, int col_size, float *result,
-// float *ctrl_pts, float *weights, float *coefs, float *l2_dist) {
-void gamut_map_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *ctrl_pts, size_t bytes_ctrl_pts,
- float *weights, size_t bytes_weights,
- float *coefs, size_t bytes_coefs,
- float *l2_dist, size_t bytes_l2_dist,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(6, input, result, ctrl_pts, weights, coefs, l2_dist, 1, result);
-
- printf("Gamut mapping.\n");
- ARRAY_3D(float, _input, input, row_size, col_size);
- ARRAY_3D(float, _result, result, row_size, col_size);
- ARRAY_2D(float, _ctrl_pts, ctrl_pts, 3);
- ARRAY_2D(float, _weights, weights, 3);
- ARRAY_2D(float, _coefs, coefs, 3);
-
- // First, get the L2 norm from every pixel to the control points,
- // Then, sum it and weight it. Finally, add the bias.
- gm_rbf_row:
- for (int row = 0; row < row_size; row++)
- gm_rbf_col:
- for (int col = 0; col < col_size; col++) {
- gm_rbf_cp0:
- for (int cp = 0; cp < num_ctrl_pts; cp++) {
- l2_dist[cp] =
- sqrt((_input[0][row][col] - _ctrl_pts[cp][0]) *
- (_input[0][row][col] - _ctrl_pts[cp][0]) +
- (_input[1][row][col] - _ctrl_pts[cp][1]) *
- (_input[1][row][col] - _ctrl_pts[cp][1]) +
- (_input[2][row][col] - _ctrl_pts[cp][2]) *
- (_input[2][row][col] - _ctrl_pts[cp][2]));
- }
- gm_rbf_chan:
- for (int chan = 0; chan < CHAN_SIZE; chan++) {
- float chan_val = 0.0;
- gm_rbf_cp1:
- for (int cp = 0; cp < num_ctrl_pts; cp++) {
- chan_val += l2_dist[cp] * _weights[cp][chan];
- }
- // Add on the biases for the RBF
- chan_val += _coefs[0][chan] + _coefs[1][chan] * _input[0][row][col] +
- _coefs[2][chan] * _input[1][row][col] +
- _coefs[3][chan] * _input[2][row][col];
- _result[chan][row][col] = max(chan_val, 0);
- }
- }
- __visc__return(1, bytes_result);
-}
-
-// Tone mapping
-//void tone_map_fxp(float *input, int row_size, int col_size, float *tone_map,
-// float *result) {
-void tone_map_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *tone_map, size_t bytes_tone_map,
- int row_size, int col_size) {
- __visc__hint(DEVICE);
- __visc__attributes(3, input, result, tone_map, 1, result);
-
- printf("Tone mapping.\n");
- ARRAY_3D(float, _input, input, row_size, col_size);
- ARRAY_3D(float, _result, result, row_size, col_size);
- ARRAY_2D(float, _tone_map, tone_map, 3);
-
- tm_chan:
- for (int chan = 0; chan < CHAN_SIZE; chan++)
- tm_row:
- for (int row = 0; row < row_size; row++)
- tm_col:
- for (int col = 0; col < col_size; col++) {
- uint8_t x = _input[chan][row][col] * 255;
- _result[chan][row][col] = _tone_map[x][chan];
- }
- __visc__return(1, bytes_result);
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/pipe_stages.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/pipe_stages.h
deleted file mode 100644
index eae4347b991fe948173fc85334c65f084d40b745..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/pipe_stages.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef _PIPE_STAGES_H_
-#define _PIPE_STAGES_H_
-
-#include "defs.h"
-
-#define CHAN_SIZE 3
-
-#define ISP 0x4
-
-#define max(a,b) \
- ({ __typeof__ (a) _a = (a); \
- __typeof__ (b) _b = (b); \
- _a > _b ? _a : _b; })
-
-#define min(a,b) \
- ({ __typeof__ (a) _a = (a); \
- __typeof__ (b) _b = (b); \
- _a < _b ? _a : _b; })
-
-#define abs(a) \
- ({ __typeof__ (a) _a = (a); \
- _a < 0 ? -_a : _a; })
-
-extern int num_ctrl_pts;
-
-void scale_fxp(uint8_t *input, size_t bytes_input,
- float *output, size_t bytes_output,
- int row_size, int col_size);
-
-void descale_fxp(float *input, size_t bytes_input,
- uint8_t *output, size_t bytes_result,
- int row_size, int col_size);
-
-void demosaic_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size);
-
-void denoise_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- int row_size, int col_size);
-
-void transform_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *TsTw_tran, size_t bytes_TsTw,
- int row_size, int col_size);
-
-void gamut_map_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *ctrl_pts, size_t bytes_ctrl_pts,
- float *weights, size_t bytes_weights,
- float *coefs, size_t bytes_coefs,
- float *l2_dist, size_t bytes_l2_dist,
- int row_size, int col_size);
-
-void tone_map_fxp(float *input, size_t bytes_input,
- float *result, size_t bytes_result,
- float *tone_map, size_t bytes_tone_map,
- int row_size, int col_size);
-
-void tone_map_approx_fxp(float *input, int row_size, int col_size,
- float *result);
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/utility.c b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/utility.c
deleted file mode 100644
index c1eaee3333c2afffdcae827f956efa4e25705352..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/utility.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <stdlib.h>
-#include <assert.h>
-#include "defs.h"
-#include "utility.h"
-
-void *malloc_aligned(size_t size) {
- void *ptr = NULL;
- int err = posix_memalign((void **)&ptr, CACHELINE_SIZE, size);
- assert(err == 0 && "Failed to allocate memory!");
- return ptr;
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/utility.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/utility.h
deleted file mode 100644
index fc407c72a3c251dc5628bc90e23e71040a074a32..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/utility.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _COMMON_UTILITY_H_
-#define _COMMON_UTILITY_H_
-
-#include <stddef.h>
-
-void *malloc_aligned(size_t size);
-
-#endif
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/visc.h b/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/visc.h
deleted file mode 100644
index a263e352523431a868637b1849ac532d7ed716a9..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/cava_test/src/visc.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/***************************************************************************
- *cr
- *cr (C) Copyright 2010 The Board of Trustees of the
- *cr University of Illinois
- *cr All Rights Reserved
- *cr
- ***************************************************************************/
-
-#ifndef DEVICE
-#define DEVICE GPU_TARGET
-#endif
-
-#include "llvm/SupportVISC/VISCHint.h"
-
-#ifdef __cplusplus
-extern "C" {
-void __visc__hint(visc::Target);
-//void __visc__wait(void*);
-#else
-void __visc__hint(enum Target);
-//void __visc__wait(unsigned);
-#endif
-
-#ifdef __cplusplus
-//void* __visc__node(...);
-//void* __visc__createNode(...);
-//void* __visc__createNode1D(...);
-//void* __visc__createNode2D(...);
-//void* __visc__createNode3D(...);
-//void __visc__return(...);
-#endif
-
-void* __visc__createNodeND(unsigned,...);
-void __visc__return(unsigned, ...);
-
-void __visc__attributes(unsigned, ...);
-void __visc__init();
-void __visc__cleanup();
-
-void __visc__bindIn(void*, unsigned, unsigned, unsigned);
-void __visc__bindOut(void*, unsigned, unsigned, unsigned);
-void* __visc__edge(void*, void*, unsigned, unsigned, unsigned, unsigned);
-void __visc__push(void*, void*);
-void* __visc__pop(void*);
-void* __visc__launch(unsigned, ...);
-void __visc__wait(void*);
-
-void* __visc__getNode();
-void* __visc__getParentNode(void*);
-void __visc__barrier();
-void* __visc__malloc(long);
-long __visc__getNodeInstanceID_x(void*);
-long __visc__getNodeInstanceID_y(void*);
-long __visc__getNodeInstanceID_z(void*);
-long __visc__getNumNodeInstances_x(void*);
-long __visc__getNumNodeInstances_y(void*);
-long __visc__getNumNodeInstances_z(void*);
-
-// Atomic
-// signed int
-int __visc__atomic_cmpxchg(int*, int, int);
-int __visc__atomic_add(int*, int);
-int __visc__atomic_sub(int*, int);
-int __visc__atomic_xchg(int*, int);
-int __visc__atomic_inc(int*);
-int __visc__atomic_dec(int*);
-int __visc__atomic_min(int*, int);
-int __visc__atomic_max(int*, int);
-int __visc__atomic_umax(int*, int);
-int __visc__atomic_umin(int*, int);
-int __visc__atomic_and(int*, int);
-int __visc__atomic_or(int*, int);
-int __visc__atomic_xor(int*, int);
-
-// Special Func
-float __visc__floor(float);
-float __visc__rsqrt(float);
-float __visc__sqrt(float);
-float __visc__sin(float);
-float __visc__cos(float);
-// unsigned int
-//unsigned __visc__atomic_cmpxchg(unsigned*, unsigned, unsigned);
-//unsigned __visc__atomic_add(unsigned*, unsigned);
-//unsigned __visc__atomic_sub(unsigned*, unsigned);
-//unsigned __visc__atomic_xchg(unsigned*, unsigned);
-//unsigned __visc__atomic_inc(unsigned*);
-//unsigned __visc__atomic_dec(unsigned*);
-//unsigned __visc__atomic_min(unsigned*, unsigned);
-//unsigned __visc__atomic_max(unsigned*, unsigned);
-//unsigned __visc__atomic_and(unsigned*, unsigned);
-//unsigned __visc__atomic_or(unsigned*, unsigned);
-//unsigned __visc__atomic_xor(unsigned*, unsigned);
-
-
-#include <unistd.h>
-
-long get_global_id(int);
-long get_group_id(int);
-long get_local_id(int);
-long get_local_size(int);
-
-
-void llvm_visc_track_mem(void*, size_t);
-void llvm_visc_untrack_mem(void*);
-void llvm_visc_request_mem(void*, size_t);
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fcl/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/fcl/Makefile
deleted file mode 100644
index 3470e4041838e0ca6ac7ccee41e39c3c14a0fa6e..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fcl/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-CC = $(LLVM_SRC_ROOT)/../build/bin/clang++
-OPT = $(LLVM_SRC_ROOT)/../build/bin/opt
-LLVM_DIS = $(LLVM_SRC_ROOT)/../build/bin/llvm-dis
-LLVM_LINK = $(LLVM_SRC_ROOT)/../build/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = fcl
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_LIB_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -lpthread -lcudart -lcurand -lcudnn -lcublas
-
-VISC_OPTFLAGS = -load LLVMBuildDFG.so -load LLVMInPlaceDFGAnalysis.so -load LLVMDFG2LLVM_CUDNN.so -load LLVMDFG2LLVM_X86.so -load LLVMClearDFG.so -inplace -dfg2llvm-cudnn -dfg2llvm-x86 -clearDFG
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm -S -o $@ $<
-
-#-visc-timers-gen
-$(BUILD_DIR)/%.visc.ll: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $< -S -o $@
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.visc.ll
- $(OPT) $(VISC_OPTFLAGS) $< -o $@
- $(LLVM_LINK) $@ $(VISC_RT_PATH) -o $(BUILD_DIR)/fcl_linked.bc
- $(CC) $(BUILD_DIR)/fcl_linked.bc $(TENSOR_LIB_DIR) -o $(BUILD_DIR)/fcl_linked $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fcl/src/fcl.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/fcl/src/fcl.cpp
deleted file mode 100644
index 70e50d76edb25d263faed6e509db66323e678315..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fcl/src/fcl.cpp
+++ /dev/null
@@ -1,112 +0,0 @@
-#include <iostream>
-#include <cstdio>
-#include <cstring>
-#include <cinttypes>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-using namespace std;
-
-void tensorMulNode(void *t1, size_t bytes1, void *t2, size_t bytes2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- // X * W = t2 * t1
- void *r = __visc__tensor_mul(t2, t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void tensorAddNode(void *t1, size_t bytest1, void *t2, size_t bytest2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void* r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void *w, size_t bytesw, void *x, size_t bytesx, void *b, size_t bytesb) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(3, w, x, b, 0);
-
- void *nodeMul = __visc__createNodeND(0, tensorMulNode);
- void *nodeAdd = __visc__createNodeND(0, tensorAddNode);
-
- // node, src, dst, stream
- __visc__bindIn(nodeMul, 0, 0, 0);
- __visc__bindIn(nodeMul, 1, 1, 0);
- __visc__bindIn(nodeMul, 2, 2, 0);
- __visc__bindIn(nodeMul, 3, 3, 0);
-
- // node, node, type, src, dst, stream
- __visc__edge(nodeMul, nodeAdd, 1, 0, 0, 0);
- __visc__edge(nodeMul, nodeAdd, 1, 1, 1, 0);
-
- __visc__bindIn(nodeAdd, 4, 2, 0);
- __visc__bindIn(nodeAdd, 5, 3, 0);
-
- __visc__bindOut(nodeAdd, 0, 0, 0);
- __visc__bindOut(nodeAdd, 1, 1, 0);
-
-}
-
-
-// Return type for the nodes
-struct ret_t {
- void *tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void *w;
- size_t bytesw;
- void *x;
- size_t bytesx;
- void *b;
- size_t bytesb;
- struct ret_t r;
-}
-RootIn;
-
-int main() {
-
- void *w;
- void *x;
- void *b;
- int test_batch_size = 1000;
- std::string prefix = "../../../../../../projects/hpvm-tensor-rt/model_params";
- std::string input_data_path = prefix + std::string("/FC_network2/mnist_float_input.bin");
- std::string W_path = prefix + std::string("/fc2_clipped/fc1.bin");
- std::string B_path = prefix + std::string("/fc2_clipped/fc1_bias.bin");
-
- printf("Reading Input Data from = %s \n", input_data_path.c_str());
-
- x = readTrainedWeights(input_data_path.c_str(), float_type,
- test_batch_size, 1, 28, 28);
- w = readTrainedWeights(W_path.c_str(), float_type, 1, 1, 784, 128);
- b = readTrainedWeights(B_path.c_str(), float_type, 1, 128, 1, 1);
-
- __visc__init();
-
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
- args->w = w;
- args->bytesw = 0;
- args->x = x;
- args->bytesx = 0;
- args->b = b;
- args->bytesb = 0;
-
- void *dfg = __visc__launch(0, root, (void *)args);
-
- __visc__wait(dfg);
-
- // FIXME: Value returned in the wrong index!!
- //void *r = static_cast<RootIn*>(args)->r.tensor;
- void *r = static_cast<RootIn*>(args)->w;
- hpvm_request_tensor(r, 0);
-
- __visc__cleanup();
- return 0;
-}
-
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fft/data/autotuner_data/tuner_confs_25.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/fft/data/autotuner_data/tuner_confs_25.txt
deleted file mode 100644
index 459b78ca10695e88ce30917e763f51f73ecd3c8c..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fft/data/autotuner_data/tuner_confs_25.txt
+++ /dev/null
@@ -1,420 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp32 1
-11 gpu conv fp32 1
------
-+++++
-conf1 1.3884 1.0000 45.4290 154.5710
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf2 1.3670 1.0000 53.4371 146.5629
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf3 1.2897 1.0000 45.4318 154.5682
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf4 1.2856 1.0000 53.0654 146.9346
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf5 1.3086 1.0000 45.0590 154.9410
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf6 1.2954 1.0000 48.0372 151.9628
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf7 1.2952 1.0000 46.9100 153.0900
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf8 1.2895 1.0000 45.4276 154.5724
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf9 1.3952 1.0000 46.9100 153.0900
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf10 1.4061 1.0000 45.2330 154.7670
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf11 1.3047 1.0000 45.2396 154.7604
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf12 1.3046 1.0000 45.2403 154.7597
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf13 1.3777 1.0000 48.3076 151.6924
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf14 1.3953 1.0000 48.0288 151.9712
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf15 1.3712 1.0000 52.9336 147.0664
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf16 1.2801 1.0000 48.3130 151.6870
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf17 1.2952 1.0000 48.0288 151.9712
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf18 1.4063 1.0000 45.2318 154.7682
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf19 1.3778 1.0000 47.1405 152.8595
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf20 1.3047 1.0000 45.2318 154.7682
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf21 1.1906 1.0000 52.9638 147.0362
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf22 1.3779 1.0000 48.3085 151.6915
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf23 1.2804 1.0000 48.3141 151.6859
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf24 1.2746 1.0000 53.0916 146.9084
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf25 1.3887 1.0000 45.4276 154.5724
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf26 1.2895 1.0000 45.4344 154.5656
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf27 1.3049 1.0000 45.2385 154.7615
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf28 1.2708 1.0000 53.4446 146.5554
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf29 1.2170 1.0000 45.2535 154.7465
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce reduce 45
-5 gpu reduce fp32 1
-6 gpu reduce reduce 45
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fft/data/autotuner_data/tuner_confs_30.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/fft/data/autotuner_data/tuner_confs_30.txt
deleted file mode 100644
index 6a37ee0605f2f110bdf1e9444f329043109b9662..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/fft/data/autotuner_data/tuner_confs_30.txt
+++ /dev/null
@@ -1,140 +0,0 @@
-+++++
-conf0 1.0000 1.0000 200.0000 0.0000
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp32 1
-11 gpu conv fp32 1
------
-+++++
-conf1 1.3843 1.0000 53.0477 146.9523
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf2 1.2896 1.0000 52.6084 147.3916
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf3 1.3714 1.0000 53.0914 146.9086
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf4 1.3886 1.0000 52.7651 147.2349
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf5 1.2748 1.0000 53.0911 146.9089
-1 gpu fft fp32 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf6 1.2895 1.0000 52.6084 147.3916
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp32 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
-+++++
-conf7 1.2858 1.0000 53.0477 146.9523
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf8 1.2895 1.0000 52.6084 147.3916
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp16 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp16 1
-10 gpu map2 fp32 1
-11 gpu conv fp16 1
------
-+++++
-conf9 1.2859 1.0000 53.0596 146.9404
-1 gpu fft fp16 1
-2 gpu map2 fp32 1
-3 gpu fft fp32 1
-4 gpu reduce fp32 1
-5 gpu reduce fp32 1
-6 gpu reduce fp32 1
-7 gpu reduce fp32 1
-8 gpu map2 fp16 1
-9 gpu map2 fp32 1
-10 gpu map2 fp16 1
-11 gpu conv fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/Makefile
deleted file mode 100644
index 961a15db146a6c1f60ee4af0b88ec8a8ca8099a5..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/Makefile
+++ /dev/null
@@ -1,65 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-# NOTE: can configure build directory
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_hpvm/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = lenet
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_LIB_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a
-TENSOR_AUTOTUNER_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_autotuner.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -lpthread -lcudart -lcurand -lcudnn -lcublas -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_CUDNN.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -dfg2llvm-cudnn -dfg2llvm-x86 -clearDFG
-
-
-QUANT_FILE_PATH=/home/hsharif3/Gitlab/hpvm/llvm/test/VISC/DNN_Benchmarks/benchmarks/lenet/data/quant_ranges.txt
-
-VISC_OPTFLAGS2 = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_PROMISE.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_CUDNN.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMFuseHPVMTensorNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -hpvm-fuse -dfg2llvm-promise -quantization-levels-filename=$(QUANT_FILE_PATH) -dfg2llvm-cudnn -dfg2llvm-x86 -clearDFG
-
-
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm src/$(APP).cpp -S -o $(BUILD_DIR)/$(APP).ll
- $(CC) $(CC_FLAGS) -emit-llvm src/$(APP)_promise.cpp -S -o $(BUILD_DIR)/$(APP)_promise.ll
-
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP).ll -S -o $(BUILD_DIR)/$(APP).visc.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP)_promise.ll -S -o $(BUILD_DIR)/$(APP)_promise.visc.ll
- $(OPT) $(VISC_OPTFLAGS) $(BUILD_DIR)/$(APP).visc.ll -o $(BUILD_DIR)/$(APP)_cudnn.bc
- $(OPT) $(VISC_OPTFLAGS2) $(BUILD_DIR)/$(APP)_promise.visc.ll -o $(BUILD_DIR)/$(APP)_promise.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_cudnn.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_cudnn_linked.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_promise.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_promise_linked.bc
- $(CC) $(BUILD_DIR)/$(APP)_cudnn_linked.bc $(TENSOR_LIB_DIR) -o $(BUILD_DIR)/$(APP)_cudnn_linked $(LINKER_FLAGS)
- $(CC) $(BUILD_DIR)/$(APP)_promise_linked.bc $(TENSOR_LIB_DIR) -o $(BUILD_DIR)/$(APP)_promise_linked $(LINKER_FLAGS)
- #$(CC) $(BUILD_DIR)/$(APP)_cudnn_linked.bc $(TENSOR_AUTOTUNER_DIR) -o $(BUILD_DIR)/lenet_tune $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_confs_batch220.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_confs_batch220.txt
deleted file mode 100644
index 7f127df520bd043e2f798c2adb35f26d55e8e29b..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_confs_batch220.txt
+++ /dev/null
@@ -1,3288 +0,0 @@
-+++++
-conf1 1 0 99.69 0
-1 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-2 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-3 gpu mul fp32 1 add fp32 1 tanh fp32 1
-4 gpu mul fp32 1 add fp32 1 tanh fp32 1
-5 gpu softmax fp32 1
------
-+++++
-conf1 1.78817265464 0 99.220001 0.7049985000000021
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf2 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf3 1.73515484904 0 99.559998 0.5300020000000046
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf4 1.72017310656 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf5 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf6 2.00016617632 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf7 1.72333900478 0 99.620003 0.4699970000000008
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf8 1.78817265464 0 99.099998 0.8850029999999975
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf9 1.73515484904 0 99.580002 0.5099980000000045
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf10 1.78817265464 0 99.32 0.5550000000000068
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf11 1.73515484904 0 99.699997 0.39000300000000154
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf12 1.77226558474 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf13 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf14 1.72333900478 0 99.620003 0.4699970000000008
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf15 1.7756263212 0 99.099998 0.8850029999999975
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf16 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf17 1.7756263212 0 99.260002 0.6449969999999965
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf18 1.51382277464 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf19 1.5 0 99.699997 0.39000300000000154
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf20 1.97610564729 0 99.599998 0.4900019999999984
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf21 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf22 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf23 1.78817265464 0 99.239998 0.6750029999999967
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf24 1.72333900478 0 99.519997 0.5700029999999942
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf25 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf26 1.77226558474 0 99.339996 0.5250059999999976
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf27 1.72017310656 0 99.300003 0.5849954999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf28 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf29 1.73515484904 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf30 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf31 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf32 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf33 1.7756263212 0 99.279999 0.6150014999999911
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf34 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf35 1.72017310656 0 99.620003 0.4699970000000008
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf36 1.72333900478 0 99.639999 0.45000099999999466
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf37 1.73515484904 0 99.559998 0.5300020000000046
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf38 1.78817265464 0 99.239998 0.6750029999999967
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf39 1.77226558474 0 99.059998 0.9450030000000069
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf40 1.99590274244 0 99.580002 0.5099980000000045
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf41 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf42 1.7756263212 0 99.239998 0.6750029999999967
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf43 1.7756263212 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf44 1.73515484904 0 99.599998 0.4900019999999984
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf45 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf46 1.72333900478 0 99.620003 0.4699970000000008
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf47 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf48 1.75663902891 0 99.540001 0.549998999999994
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf49 2.00016617632 0 99.379997 0.46500449999999205
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf50 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf51 1.7756263212 0 99.32 0.5550000000000068
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf52 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf53 1.51382277464 0 99.620003 0.4699970000000008
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf54 1.72017310656 0 99.440002 0.6499979999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf55 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf56 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf57 1.7756263212 0 99.040001 0.974998499999991
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf58 1.78817265464 0 99.300003 0.5849954999999909
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf59 1.77226558474 0 99.459999 0.6300010000000015
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf60 1.77226558474 0 99.18 0.7649999999999864
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf61 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf62 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf63 1.78817265464 0 99.32 0.5550000000000068
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf64 1.72333900478 0 99.660004 0.42999599999999705
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf65 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf66 1.73515484904 0 99.519997 0.5700029999999942
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf67 1.73515484904 0 99.5 0.5899999999999977
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf68 1.78817265464 0 99.279999 0.6150014999999911
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf69 1.7756263212 0 99.32 0.5550000000000068
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf70 1.73515484904 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf71 1.75663902891 0 99.160004 0.7949939999999955
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf72 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf73 1.72333900478 0 99.480003 0.6099970000000013
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf74 1.7756263212 0 99.300003 0.5849954999999909
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf75 1.77226558474 0 99.300003 0.5849954999999909
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf76 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf77 1.78817265464 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf78 1.75663902891 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf79 1.78817265464 0 99.519997 0.5700029999999942
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf80 2.00016617632 0 99.519997 0.5700029999999942
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf81 1.70544786131 0 99.639999 0.45000099999999466
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf82 1.73515484904 0 99.620003 0.4699970000000008
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf83 1.77226558474 0 99.220001 0.7049985000000021
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf84 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf85 1.51137932951 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf86 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf87 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf88 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf89 1.75663902891 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf90 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf91 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf92 1.78817265464 0 99.239998 0.6750029999999967
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf93 1.72017310656 0 99.559998 0.5300020000000046
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf94 1.72333900478 0 99.639999 0.45000099999999466
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf95 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf96 1.7756263212 0 99.32 0.5550000000000068
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf97 1.73515484904 0 99.639999 0.45000099999999466
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf98 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf99 1.522932631 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf100 1.51382277464 0 99.599998 0.4900019999999984
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf101 2.00016617632 0 99.620003 0.4699970000000008
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf102 1.522932631 0 99.639999 0.45000099999999466
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf103 1.7756263212 0 99.360001 0.49499850000000123
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf104 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf105 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf106 1.77226558474 0 99.199997 0.7350045000000023
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf107 1.75663902891 0 99.199997 0.7350045000000023
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf108 1.99590274244 0 99.599998 0.4900019999999984
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf109 1.78817265464 0 99.199997 0.7350045000000023
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf110 1.522932631 0 99.68 0.4099999999999909
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf111 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf112 1.72333900478 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf113 1.7756263212 0 99.300003 0.5849954999999909
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf114 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf115 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf116 1.72333900478 0 99.540001 0.549998999999994
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf117 1.70544786131 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf118 1.78817265464 0 99.379997 0.46500449999999205
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf119 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf120 1.7756263212 0 99.160004 0.7949939999999955
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf121 1.73515484904 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf122 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf123 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf124 1.70544786131 0 99.620003 0.4699970000000008
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf125 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf126 1.7756263212 0 99.379997 0.46500449999999205
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf127 1.51137932951 0 99.660004 0.42999599999999705
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf128 1.73515484904 0 99.639999 0.45000099999999466
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf129 1.5 0 99.699997 0.39000300000000154
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf130 1.78817265464 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf131 1.72017310656 0 99.300003 0.5849954999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf132 1.73515484904 0 99.519997 0.5700029999999942
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf133 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf134 1.78817265464 0 99.279999 0.6150014999999911
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf135 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf136 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf137 1.77226558474 0 99.120003 0.8549955000000011
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf138 1.73515484904 0 99.599998 0.4900019999999984
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf139 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf140 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf141 1.73515484904 0 99.459999 0.6300010000000015
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf142 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf143 1.78817265464 0 99.239998 0.6750029999999967
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf144 1.7756263212 0 99.459999 0.6300010000000015
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf145 1.78817265464 0 99.239998 0.6750029999999967
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf146 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf147 1.72333900478 0 99.620003 0.4699970000000008
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf148 2.00016617632 0 98.400002 1.9349969999999956
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf149 1.72017310656 0 99.559998 0.5300020000000046
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf150 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf151 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf152 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf153 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf154 1.70544786131 0 99.620003 0.4699970000000008
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf155 1.97610564729 0 99.599998 0.4900019999999984
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf156 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf157 1.75663902891 0 99.199997 0.7350045000000023
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf158 1.78817265464 0 99.279999 0.6150014999999911
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf159 1.73515484904 0 99.699997 0.39000300000000154
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf160 1.78817265464 0 99.32 0.5550000000000068
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf161 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf162 1.78817265464 0 99.059998 0.9450030000000069
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf163 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf164 1.75663902891 0 99.199997 0.7350045000000023
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf165 1.72333900478 0 99.639999 0.45000099999999466
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf166 1.72017310656 0 99.620003 0.4699970000000008
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf167 1.73515484904 0 99.639999 0.45000099999999466
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf168 1.7756263212 0 99.279999 0.6150014999999911
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf169 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf170 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf171 1.70544786131 0 99.620003 0.4699970000000008
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf172 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf173 1.7756263212 0 99.160004 0.7949939999999955
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf174 1.75663902891 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf175 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf176 1.99590274244 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf177 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf178 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf179 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf180 1.78817265464 0 98.980003 1.064995500000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf181 1.7756263212 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf182 1.78817265464 0 99.379997 0.46500449999999205
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf183 1.70544786131 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf184 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf185 1.75663902891 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf186 1.73515484904 0 99.599998 0.4900019999999984
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf187 1.78817265464 0 99.32 0.5550000000000068
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf188 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf189 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf190 1.78817265464 0 99.199997 0.7350045000000023
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf191 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf192 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf193 1.77226558474 0 99.059998 0.9450030000000069
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf194 1.78817265464 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf195 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf196 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf197 1.77226558474 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf198 1.78817265464 0 99.080002 0.9149970000000067
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf199 1.70544786131 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf200 1.7756263212 0 99.360001 0.49499850000000123
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf201 1.7756263212 0 99.199997 0.7350045000000023
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf202 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf203 1.77226558474 0 99.199997 0.7350045000000023
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf204 1.51382277464 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf205 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf206 1.7756263212 0 99.099998 0.8850029999999975
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf207 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf208 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf209 1.75663902891 0 99.160004 0.7949939999999955
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf210 1.97610564729 0 98.440002 1.8749969999999863
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf211 1.72017310656 0 99.300003 0.5849954999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf212 1.77226558474 0 98.940002 1.1249969999999863
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf213 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf214 1.75663902891 0 99.32 0.5550000000000068
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf215 1.78817265464 0 99.620003 0.4699970000000008
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf216 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf217 1.73515484904 0 99.519997 0.5700029999999942
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf218 1.51137932951 0 99.440002 0.6499979999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf219 1.97610564729 0 98.480003 1.814995500000002
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf220 1.73515484904 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf221 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf222 1.77226558474 0 99.5 0.5899999999999977
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf223 1.522932631 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf224 1.522932631 0 99.540001 0.549998999999994
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf225 1.522932631 0 99.68 0.4099999999999909
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf226 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf227 1.72333900478 0 99.660004 0.42999599999999705
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf228 1.77226558474 0 98.980003 1.064995500000002
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf229 1.78817265464 0 99.220001 0.7049985000000021
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf230 1.7756263212 0 99.239998 0.6750029999999967
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf231 1.70544786131 0 99.639999 0.45000099999999466
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf232 1.73515484904 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf233 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf234 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf235 1.78817265464 0 99.559998 0.5300020000000046
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf236 1.5 0 99.699997 0.39000300000000154
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf237 1.73515484904 0 99.639999 0.45000099999999466
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf238 1.97610564729 0 98.440002 1.8749969999999863
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf239 1.77226558474 0 98.800003 1.334995499999991
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf240 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf241 1.75663902891 0 99.160004 0.7949939999999955
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf242 1.78817265464 0 99.239998 0.6750029999999967
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf243 1.75663902891 0 99.699997 0.39000300000000154
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf244 1.72017310656 0 99.419998 0.670001999999991
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf245 2.00016617632 0 99.0 1.0349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf246 1.99590274244 0 98.519997 1.7550044999999912
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf247 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf248 1.72333900478 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf249 1.72333900478 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf250 1.51137932951 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf251 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf252 1.7756263212 0 99.160004 0.7949939999999955
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf253 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf254 1.72017310656 0 97.860001 2.7449985000000012
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf255 1.72333900478 0 99.68 0.4099999999999909
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf256 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf257 1.72333900478 0 99.660004 0.42999599999999705
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf258 2.00016617632 0 99.620003 0.4699970000000008
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf259 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf260 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf261 1.97610564729 0 99.599998 0.4900019999999984
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf262 2.00016617632 0 97.980003 2.564995500000002
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf263 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf264 1.99590274244 0 98.099998 2.3850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf265 2.00016617632 0 98.080002 2.4149970000000067
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf266 1.70544786131 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf267 1.7756263212 0 99.32 0.5550000000000068
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf268 1.97610564729 0 98.480003 1.814995500000002
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf269 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf270 1.99590274244 0 98.139999 2.325001499999992
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf271 1.73515484904 0 99.699997 0.39000300000000154
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf272 1.7756263212 0 99.260002 0.6449969999999965
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf273 1.51382277464 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf274 1.72017310656 0 99.559998 0.5300020000000046
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf275 1.75663902891 0 98.0 2.5349999999999966
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf276 1.73515484904 0 99.5 0.5899999999999977
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf277 1.78817265464 0 98.959999 1.0950015000000022
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf278 1.7756263212 0 99.639999 0.45000099999999466
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf279 1.99590274244 0 98.519997 1.7550044999999912
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf280 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf281 1.78817265464 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf282 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf283 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf284 1.78817265464 0 99.300003 0.5849954999999909
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf285 1.73515484904 0 99.519997 0.5700029999999942
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf286 1.78817265464 0 99.660004 0.42999599999999705
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf287 1.77226558474 0 98.599998 1.6350029999999975
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf288 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf289 1.77226558474 0 99.059998 0.9450030000000069
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf290 1.522932631 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf291 1.72333900478 0 99.540001 0.549998999999994
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf292 1.7756263212 0 99.32 0.5550000000000068
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf293 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf294 1.7756263212 0 99.040001 0.974998499999991
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf295 1.97610564729 0 98.440002 1.8749969999999863
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf296 1.99590274244 0 98.599998 1.6350029999999975
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf297 2.00016617632 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf298 1.73515484904 0 99.559998 0.5300020000000046
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf299 1.73515484904 0 99.580002 0.5099980000000045
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf300 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf301 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf302 1.7756263212 0 97.760002 2.8949969999999965
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf303 1.75663902891 0 99.32 0.5550000000000068
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf304 1.77226558474 0 99.5 0.5899999999999977
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf305 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf306 1.78817265464 0 98.82 1.3050000000000068
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf307 1.75663902891 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf308 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf309 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf310 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf311 1.77226558474 0 99.279999 0.6150014999999911
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf312 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf313 1.78817265464 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf314 1.522932631 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf315 1.75663902891 0 99.199997 0.7350045000000023
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf316 2.00016617632 0 99.519997 0.5700029999999942
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf317 1.72017310656 0 99.580002 0.5099980000000045
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf318 1.7756263212 0 99.32 0.5550000000000068
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf319 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf320 1.72017310656 0 99.440002 0.6499979999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf321 1.7756263212 0 99.199997 0.7350045000000023
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf322 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf323 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf324 1.73515484904 0 99.5 0.5899999999999977
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf325 1.99590274244 0 99.580002 0.5099980000000045
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf326 1.99590274244 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf327 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf328 1.72333900478 0 99.660004 0.42999599999999705
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf329 1.78817265464 0 98.940002 1.1249969999999863
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf330 1.78817265464 0 99.18 0.7649999999999864
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf331 1.72333900478 0 99.639999 0.45000099999999466
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf332 1.7756263212 0 99.300003 0.5849954999999909
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf333 1.78817265464 0 99.199997 0.7350045000000023
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf334 1.78817265464 0 99.32 0.5550000000000068
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf335 1.78817265464 0 99.099998 0.8850029999999975
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf336 2.00016617632 0 99.0 1.0349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf337 2.00016617632 0 98.059998 2.445003000000007
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf338 2.00016617632 0 98.580002 1.6649970000000067
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf339 1.72333900478 0 99.620003 0.4699970000000008
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf340 2.00016617632 0 98.419998 1.9050029999999865
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf341 2.00016617632 0 98.0 2.5349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf342 1.75663902891 0 99.160004 0.7949939999999955
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf343 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf344 2.00016617632 0 98.400002 1.9349969999999956
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf345 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf346 1.72017310656 0 99.300003 0.5849954999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf347 1.73515484904 0 99.660004 0.42999599999999705
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf348 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf349 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf350 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf351 1.78817265464 0 98.980003 1.064995500000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf352 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf353 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf354 1.72333900478 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf355 1.73515484904 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf356 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf357 1.70544786131 0 99.620003 0.4699970000000008
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf358 1.7756263212 0 99.279999 0.6150014999999911
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf359 1.7756263212 0 98.82 1.3050000000000068
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf360 1.7756263212 0 99.379997 0.46500449999999205
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf361 1.99590274244 0 99.599998 0.4900019999999984
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf362 1.78817265464 0 99.279999 0.6150014999999911
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf363 1.70544786131 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf364 1.70544786131 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf365 1.78817265464 0 97.760002 2.8949969999999965
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf366 1.72017310656 0 99.620003 0.4699970000000008
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf367 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf368 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf369 1.7756263212 0 99.160004 0.7949939999999955
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf370 1.78817265464 0 99.080002 0.9149970000000067
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf371 1.75663902891 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf372 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf373 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf374 1.72333900478 0 99.599998 0.4900019999999984
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf375 1.99590274244 0 97.940002 2.6249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf376 1.78817265464 0 98.980003 1.064995500000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf377 1.7756263212 0 99.279999 0.6150014999999911
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf378 1.522932631 0 99.540001 0.549998999999994
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf379 1.5 0 99.699997 0.39000300000000154
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf380 1.78817265464 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf381 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf382 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf383 1.72017310656 0 99.300003 0.5849954999999909
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf384 1.70544786131 0 99.639999 0.45000099999999466
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf385 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf386 1.73515484904 0 99.639999 0.45000099999999466
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf387 1.72017310656 0 99.620003 0.4699970000000008
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf388 1.51382277464 0 99.660004 0.42999599999999705
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf389 1.7756263212 0 99.300003 0.5849954999999909
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf390 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf391 1.97610564729 0 99.599998 0.4900019999999984
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf392 1.72333900478 0 99.620003 0.4699970000000008
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf393 1.51382277464 0 99.620003 0.4699970000000008
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf394 2.00016617632 0 98.980003 1.064995500000002
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf395 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf396 1.73515484904 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf397 1.77226558474 0 99.32 0.5550000000000068
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf398 1.75663902891 0 99.32 0.5550000000000068
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf399 1.77226558474 0 98.980003 1.064995500000002
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf400 2.00016617632 0 98.040001 2.474998499999991
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf401 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf402 1.78817265464 0 99.300003 0.5849954999999909
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf403 1.75663902891 0 99.199997 0.7350045000000023
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf404 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf405 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf406 1.7756263212 0 98.400002 1.9349969999999956
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf407 1.73515484904 0 99.559998 0.5300020000000046
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf408 1.72333900478 0 99.580002 0.5099980000000045
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf409 1.72333900478 0 99.639999 0.45000099999999466
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf410 1.73515484904 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_pareto_confs_batch220.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_pareto_confs_batch220.txt
deleted file mode 100644
index 20b92832d433de5c65f50c946c50153e1d3eebc9..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_pareto_confs_batch220.txt
+++ /dev/null
@@ -1,904 +0,0 @@
-+++++
-conf1 1 0 99.69 0
-1 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-2 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-3 gpu mul fp32 1 add fp32 1 tanh fp32 1
-4 gpu mul fp32 1 add fp32 1 tanh fp32 1
-5 gpu softmax fp32 1
------
-+++++
-conf1 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf2 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf3 2.00016617632 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf4 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf5 1.97610564729 0 99.599998 0.4900019999999984
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf6 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf7 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf8 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf9 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf10 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf11 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf12 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf13 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf14 1.99590274244 0 99.580002 0.5099980000000045
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf15 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf16 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf17 2.00016617632 0 99.379997 0.46500449999999205
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf18 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf19 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf20 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf21 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf22 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf23 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf24 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf25 2.00016617632 0 99.519997 0.5700029999999942
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf26 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf27 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf28 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf29 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf30 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf31 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf32 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf33 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf34 2.00016617632 0 99.620003 0.4699970000000008
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf35 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf36 1.99590274244 0 99.599998 0.4900019999999984
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf37 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf38 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf39 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf40 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf41 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf42 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf43 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf44 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf45 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf46 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf47 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf48 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf49 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf50 2.00016617632 0 98.400002 1.9349969999999956
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf51 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf52 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf53 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf54 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf55 1.97610564729 0 99.599998 0.4900019999999984
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf56 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf57 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf58 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf59 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf60 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf61 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf62 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf63 1.99590274244 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf64 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf65 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf66 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf67 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf68 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf69 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf70 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf71 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf72 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf73 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf74 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf75 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf76 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf77 1.97610564729 0 98.440002 1.8749969999999863
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf78 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf79 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf80 1.97610564729 0 98.480003 1.814995500000002
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf81 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf82 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf83 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf84 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf85 1.97610564729 0 98.440002 1.8749969999999863
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf86 2.00016617632 0 99.0 1.0349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf87 1.99590274244 0 98.519997 1.7550044999999912
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf88 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf89 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf90 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf91 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf92 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf93 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf94 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf95 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf96 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf97 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf98 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf99 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf100 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf101 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf102 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf103 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf104 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf105 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf106 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf107 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf108 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf109 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf110 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf111 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf112 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_promise_confs_batch220_multi.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_promise_confs_batch220_multi.txt
deleted file mode 100644
index d00ab536d689932379baa3325a11652a95138c93..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_promise_confs_batch220_multi.txt
+++ /dev/null
@@ -1,13968 +0,0 @@
-+++++
-conf1 1 0 99.69 0
-1 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-2 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-3 gpu mul fp32 1 add fp32 1 tanh fp32 1
-4 gpu mul fp32 1 add fp32 1 tanh fp32 1
-5 gpu softmax fp32 1
------
-+++++
-conf1 3.86059861244 0 99.5865002 0.5034997999999945
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf2 2.47778695782 0 99.401499275 0.6885007249999916
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf3 2.50228643329 0 99.302000275 0.5819995875000004
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf4 3.92040413524 0 99.545499375 0.5445006249999921
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf5 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf6 2.47778695782 0 99.04700025 0.964499625000002
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf7 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf8 2.00016617632 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf9 3.77195447337 0 99.631001025 0.4589989749999944
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf10 2.47778695782 0 99.2549994 0.6525008999999926
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf11 6.14799414721 0 99.50250035 0.5874996499999924
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf12 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf13 2.47778695782 0 99.38799915 0.4530012749999983
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf14 3.84474688915 0 99.5614995 0.5285005000000013
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf15 3.34244261096 0 99.594499925 0.4955000750000039
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf16 2.50228643329 0 99.4655008 0.6244991999999968
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf17 2.47778695782 0 98.991999975 1.0470000374999984
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf18 6.14799414721 0 99.41749905 0.6725009499999942
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf19 3.34244261096 0 99.51449975 0.5755002499999989
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf20 3.92040413524 0 99.5669999 0.5230000999999987
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf21 3.80166404425 0 99.543499725 0.546500274999994
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf22 3.85964385182 0 99.4755007 0.6144993
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf23 2.47778695782 0 99.31599945 0.5610008249999865
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf24 2.47778695782 0 99.405499825 0.6845001749999909
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf25 2.50228643329 0 99.37349895 0.4747515749999991
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf26 6.61857279171 0 99.494500325 0.5954996749999936
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf27 3.84474688915 0 99.417499625 0.6725003749999928
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf28 2.47778695782 0 99.026998925 0.9945016124999952
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf29 2.50228643329 0 99.370499525 0.4792507124999972
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf30 6.30106886729 0 99.5040001 0.5859998999999988
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf31 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf32 3.7862916372 0 99.5900006 0.49999940000000154
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf33 3.86059861244 0 99.612000375 0.4779996250000039
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf34 3.92040413524 0 99.558499875 0.5315001250000023
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf35 3.86059861244 0 99.56849965 0.521500349999991
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf36 5.02870270579 0 99.267000425 0.6344993624999873
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf37 6.14799414721 0 99.50099985 0.5890001499999983
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf38 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf39 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf40 2.50228643329 0 99.027499025 0.9937514625000006
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf41 6.14799414721 0 99.554999675 0.535000324999993
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf42 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf43 3.84474688915 0 99.7254995 0.3645004999999998
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf44 3.92040413524 0 99.57699975 0.5130002499999989
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf45 6.14799414721 0 99.5009999 0.5890001000000012
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf46 2.47778695782 0 99.376999825 0.46950026249999866
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf47 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf48 3.85964385182 0 99.269500375 0.6307494374999862
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf49 3.13161472572 0 99.5865002 0.5034997999999945
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf50 6.30106886729 0 99.25849995 0.6472500749999952
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf51 5.92620561097 0 99.54949965 0.5405003499999964
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf52 2.47124761202 0 99.10999975 0.8700003749999965
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf53 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf54 3.38717868509 0 99.33499915 0.5325012749999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf55 3.80166404425 0 99.513499725 0.5765002749999951
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf56 2.44096937877 0 99.3519992 0.5070012000000048
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf57 3.92040413524 0 99.475999775 0.6140002249999924
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf58 3.92040413524 0 99.3189995 0.5565007499999908
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf59 2.47778695782 0 99.479500975 0.6104990250000043
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf60 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf61 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf62 2.81322619695 0 99.540999075 0.5490009249999958
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf63 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf64 3.86059861244 0 99.615501 0.474499000000003
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf65 3.86059861244 0 99.585999975 0.5040000250000048
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf66 3.86059861244 0 99.515000025 0.5749999749999916
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf67 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf68 5.79060658268 0 99.425999975 0.6640000250000014
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf69 2.50228643329 0 98.901499925 1.1827501125000026
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf70 2.47124761202 0 98.265500075 2.136749887499988
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf71 3.77195447337 0 99.63050095 0.45949904999999946
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf72 2.50228643329 0 98.91149985 1.167750224999999
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf73 5.02870270579 0 99.46900055 0.6209994499999937
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf74 2.00016617632 0 98.580002 1.6649970000000067
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf75 2.57685599488 0 99.371499325 0.4777510124999935
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf76 2.51187737029 0 99.390999175 0.6990008249999932
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf77 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf78 6.14799414721 0 99.49949955 0.5905004500000018
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf79 2.47124761202 0 99.21099945 0.7185008249999925
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf80 6.30106886729 0 99.517499475 0.5725005250000038
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf81 5.92620561097 0 99.542999375 0.547000625000004
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf82 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf83 3.33055390722 0 99.418500225 0.6714997749999952
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf84 6.61857279171 0 99.50099985 0.5890001499999983
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf85 3.80166404425 0 99.521499575 0.5685004249999907
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf86 4.4071692756 0 99.419500275 0.6704997249999934
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf87 2.47124761202 0 99.37749925 0.46875112499999716
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf88 5.79060658268 0 99.565499625 0.5245003749999967
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf89 6.7963162944 0 99.453000325 0.6369996749999928
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf90 1.99590274244 0 98.440002 1.8749969999999863
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf91 6.14799414721 0 99.43249995 0.6575000500000044
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf92 3.85964385182 0 99.473000375 0.6169996249999997
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf93 2.50228643329 0 98.878998975 1.216501537499994
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf94 5.02870270579 0 99.442000525 0.6479994750000003
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf95 6.57211871555 0 99.33249975 0.5362503750000016
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf96 3.38717868509 0 99.336998575 0.5295021375000033
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf97 3.92040413524 0 99.5710002 0.5189997999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf98 4.64385542353 0 99.51799975 0.5720002499999964
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf99 2.47124761202 0 99.01849985 1.007250225
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf100 2.5439518228 0 99.4895 0.600499999999991
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf101 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf102 6.10789096832 0 99.341499625 0.5227505625000006
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf103 2.50228643329 0 99.438500325 0.651499674999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf104 2.50228643329 0 99.4235 0.6664999999999935
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf105 2.50228643329 0 99.00049975 1.034250374999992
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf106 6.10789096832 0 99.590500925 0.49949907499999713
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf107 3.80166404425 0 99.5274999 0.5625001000000026
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf108 6.7963162944 0 99.495500375 0.5944996249999918
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf109 6.14799414721 0 99.495000225 0.5949997749999995
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf110 3.86059861244 0 99.5875 0.5024999999999921
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf111 2.00016617632 0 98.980003 1.064995500000002
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf112 4.90489779833 0 99.4235004 0.6664996000000031
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf113 4.93072604433 0 99.519499875 0.5705001250000038
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf114 2.47124761202 0 99.22599905 0.6960014249999986
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf115 2.57685599488 0 99.38249875 0.4612518750000021
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf116 2.47778695782 0 99.387499325 0.4537510125000068
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf117 3.92040413524 0 99.4889999 0.6010001000000017
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf118 2.47124761202 0 99.3574979 0.49875314999999887
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf119 4.90489779833 0 99.338499075 0.5272513874999945
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf120 2.57685599488 0 98.909499725 1.1707504124999915
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf121 3.7862916372 0 99.425500575 0.6644994249999968
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf122 5.02870270579 0 99.51799975 0.5720002499999964
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf123 6.10789096832 0 99.41449975 0.6755002499999933
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf124 3.80166404425 0 99.5164998 0.5735001999999924
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf125 6.30106886729 0 99.469500325 0.6204996749999993
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf126 4.93072604433 0 99.522999375 0.567000625
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf127 3.86059861244 0 99.618499975 0.4715000249999918
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf128 2.55088214386 0 99.382999475 0.46050078749998846
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf129 6.14799414721 0 99.513499725 0.5765002749999951
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf130 6.30106886729 0 99.449999925 0.6400000749999976
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf131 2.50228643329 0 98.300999875 2.083500187499993
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf132 3.33055390722 0 99.563499475 0.5265005249999973
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf133 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf134 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf135 1.99590274244 0 98.139999 2.325001499999992
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf136 3.85964385182 0 99.47600045 0.613999549999997
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf137 2.78229733114 0 99.5514998 0.5385001999999958
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf138 3.77195447337 0 99.3254996 0.5467505999999958
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf139 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf140 2.81322619695 0 99.5814995 0.508500499999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf141 2.57685599488 0 99.417499875 0.6725001249999935
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf142 4.93072604433 0 99.5164998 0.5735001999999924
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf143 2.50228643329 0 99.466500825 0.6234991750000006
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf144 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf145 2.77405457184 0 99.573499525 0.5165004749999952
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf146 3.70186719231 0 99.722999925 0.3670000750000014
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf147 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf148 3.92040413524 0 99.5589999 0.5310000999999943
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf149 6.61857279171 0 99.414999925 0.6750000749999941
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf150 3.38717868509 0 99.56849935 0.5215006500000016
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf151 3.34244261096 0 99.616000475 0.47399952499999076
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf152 5.33920664205 0 99.4435006 0.6464994000000047
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf153 2.5439518228 0 98.314999825 2.062500262499995
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf154 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf155 2.50228643329 0 98.911000225 1.168499662500004
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf156 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf157 2.50228643329 0 99.39599955 0.6940004499999987
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf158 3.38717868509 0 99.46750085 0.6224991500000044
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf159 2.81322619695 0 99.461000775 0.6289992249999955
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf160 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf161 2.50228643329 0 99.007999825 1.0230002624999983
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf162 3.92040413524 0 99.5534999 0.5365000999999922
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf163 2.50228643329 0 99.43850055 0.6514994499999972
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf164 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf165 2.01610051566 0 97.879997 2.715004499999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf166 6.30106886729 0 99.2590004 0.6464993999999891
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf167 2.50228643329 0 98.98099975 1.0635003750000038
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf168 2.50228643329 0 99.372998825 0.4755017625000022
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf169 5.02870270579 0 99.4364997 0.6535002999999989
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf170 2.50228643329 0 97.885499575 2.7067506375000008
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf171 2.01610051566 0 97.900002 2.6849969999999956
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf172 2.50228643329 0 98.90100005 1.1834999250000067
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf173 2.50228643329 0 98.326998875 2.044501687499995
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf174 3.92040413524 0 99.4730004 0.6169995999999941
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf175 5.02870270579 0 99.25650025 0.6502496249999936
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf176 2.50228643329 0 99.40049935 0.6895006499999937
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf177 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf178 2.50228643329 0 99.375999275 0.47100108749999947
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf179 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf180 2.81322619695 0 99.341498825 0.5227517624999933
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf181 6.30106886729 0 99.451500425 0.6384995749999917
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf182 2.50228643329 0 99.094000075 0.8939998875000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf183 3.92040413524 0 99.31999995 0.5550000750000024
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf184 2.50228643329 0 99.373498975 0.47475153749999066
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf185 2.50228643329 0 99.47200125 0.6179987499999925
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf186 3.92040413524 0 99.582000275 0.5079997249999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf187 3.85964385182 0 99.5244993 0.5655006999999955
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf188 6.30106886729 0 99.459000325 0.6309996749999925
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf189 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf190 6.30106886729 0 99.472500875 0.6174991250000034
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf191 2.50228643329 0 97.651000575 3.0584991375
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf192 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf193 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf194 3.92040413524 0 99.551 0.5389999999999958
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf195 2.50228643329 0 99.423000075 0.6669999249999933
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf196 3.85964385182 0 99.475500725 0.6144992749999943
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf197 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf198 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf199 6.30106886729 0 99.517000075 0.5729999249999992
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf200 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf201 3.85964385182 0 99.437000325 0.6529996749999981
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf202 6.30106886729 0 99.437500275 0.6524997249999928
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf203 2.50228643329 0 99.188499275 0.7522510874999995
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf204 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf205 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf206 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf207 6.30106886729 0 99.440500775 0.6494992249999939
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf208 2.47778695782 0 98.98650045 1.0552493250000055
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf209 3.92040413524 0 99.559499725 0.5305002750000029
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf210 6.14799414721 0 99.559999775 0.5300002250000034
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf211 4.93072604433 0 99.5089997 0.5810002999999938
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf212 4.90489779833 0 99.332999675 0.535500487500002
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf213 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf214 2.47124761202 0 99.316000575 0.5609991374999908
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf215 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf216 3.92040413524 0 99.5844996 0.5055003999999969
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf217 2.47124761202 0 99.1250007 0.847498949999995
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf218 2.47124761202 0 99.381998825 0.4620017625000017
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf219 6.14799414721 0 99.42000025 0.6699997499999967
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf220 6.10789096832 0 99.416 0.6740000000000009
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf221 5.92620561097 0 99.5324998 0.5575002000000012
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf222 2.50228643329 0 99.3659991 0.4860013500000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf223 2.81322619695 0 99.59350015 0.49649985000000074
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf224 3.85964385182 0 99.272000525 0.626999212500003
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf225 6.14799414721 0 99.46450015 0.6254998499999914
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf226 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf227 6.14799414721 0 99.49450015 0.5954998500000045
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf228 2.81322619695 0 99.334998975 0.5325015374999893
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf229 6.14799414721 0 99.5029999 0.5870000999999917
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf230 3.86059861244 0 99.57099965 0.5190003499999932
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf231 6.30106886729 0 99.4249999 0.6650000999999947
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf232 3.77195447337 0 99.64550045 0.44449954999999763
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf233 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf234 6.30106886729 0 99.455500425 0.634499575000001
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf235 2.44096937877 0 99.4455007 0.6444993000000011
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf236 5.02870270579 0 99.430500375 0.6594996250000037
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf237 2.77405457184 0 99.431500125 0.6584998749999983
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf238 6.30106886729 0 99.259000225 0.6464996625000055
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf239 3.92040413524 0 99.331999675 0.5370004874999879
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf240 3.34244261096 0 99.561499925 0.528500074999991
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf241 6.10789096832 0 99.344999375 0.5175009374999959
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf242 4.93072604433 0 99.524499625 0.5655003749999935
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf243 2.47778695782 0 99.0039994 1.0290008999999998
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf244 6.14799414721 0 99.501000025 0.5889999750000016
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf245 3.86059861244 0 99.590000225 0.4999997750000006
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf246 2.81322619695 0 99.585999875 0.5040001249999989
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf247 3.84474688915 0 99.570500075 0.5194999249999995
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf248 3.38717868509 0 99.3339993 0.5340010499999934
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf249 2.00016617632 0 99.379997 0.46500449999999205
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf250 2.50228643329 0 99.2840001 0.6089998499999965
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf251 6.10789096832 0 99.57099985 0.5190001499999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf252 5.02870270579 0 99.26750015 0.6337497749999912
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf253 2.50228643329 0 99.388999175 0.45150123750000404
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf254 3.71567552873 0 99.558999425 0.5310005750000016
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf255 1.99590274244 0 99.599998 0.4900019999999984
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf256 3.33055390722 0 99.567500075 0.5224999249999996
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf257 2.50228643329 0 99.387999625 0.4530005624999873
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf258 2.47778695782 0 99.325999725 0.5460004124999926
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf259 3.80166404425 0 99.533999275 0.5560007249999984
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf260 2.00016617632 0 99.0 1.0349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf261 1.99590274244 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf262 2.47778695782 0 99.37499845 0.47250232499998646
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf263 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf264 2.00016617632 0 98.980003 1.064995500000002
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf265 4.78704248134 0 99.542999225 0.5470007749999951
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf266 3.86059861244 0 99.6060007 0.48399930000000213
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf267 3.86059861244 0 99.614001325 0.47599867499999393
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf268 3.86059861244 0 99.5959999 0.4940001000000024
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf269 5.02870270579 0 99.524999575 0.5650004250000024
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf270 3.34244261096 0 99.583499925 0.5065000749999996
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf271 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf272 3.92040413524 0 99.54199885 0.5480011499999989
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf273 3.86059861244 0 99.582500175 0.5074998249999908
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf274 3.33055390722 0 99.724499675 0.36550032499999363
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf275 6.14799414721 0 99.504500025 0.5854999749999991
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf276 2.47124761202 0 98.819999675 1.3050004874999885
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf277 6.10789096832 0 99.40649895 0.6835010499999982
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf278 6.10789096832 0 99.577999475 0.5120005249999992
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf279 2.47778695782 0 99.30150025 0.5827496249999911
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf280 2.50228643329 0 99.3719988 0.4770017999999965
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf281 2.50228643329 0 98.29700015 2.089499774999993
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf282 4.93072604433 0 99.470500775 0.6194992249999928
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf283 2.50228643329 0 99.439000875 0.6509991249999928
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf284 6.14799414721 0 99.46549985 0.6245001499999973
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf285 3.85964385182 0 99.43350045 0.6564995500000009
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf286 6.30106886729 0 99.4350001 0.6549999000000014
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf287 2.50228643329 0 98.327000375 2.0444994375000007
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf288 3.38717868509 0 99.326000275 0.545999587499999
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf289 2.50228643329 0 99.420999875 0.669000124999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf290 2.50228643329 0 99.467501025 0.6224989749999935
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf291 3.92040413524 0 99.583000475 0.506999524999992
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf292 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf293 2.50228643329 0 99.38349915 0.4597512749999879
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf294 2.81322619695 0 99.4725008 0.6174991999999918
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf295 1.99590274244 0 99.540001 0.549998999999994
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf296 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf297 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf298 3.85964385182 0 99.4755009 0.6144990999999976
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf299 3.80166404425 0 99.524499125 0.5655008749999922
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf300 3.86059861244 0 99.5054997 0.5845002999999963
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf301 6.30106886729 0 99.45100085 0.638999149999998
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf302 5.02870270579 0 99.4765002 0.6134997999999939
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf303 2.47778695782 0 99.0105 1.0192500000000067
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf304 3.92040413524 0 99.562000025 0.5279999749999945
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf305 6.30106886729 0 99.50299955 0.5870004499999993
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf306 3.84474688915 0 99.729999675 0.3600003249999958
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf307 6.14799414721 0 99.5119996 0.578000400000002
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf308 4.90489779833 0 99.58749965 0.5025003499999997
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf309 3.7862916372 0 99.33799965 0.528000524999996
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf310 6.30106886729 0 99.2670004 0.6344993999999957
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf311 6.30106886729 0 99.435500625 0.6544993749999947
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf312 2.47778695782 0 99.331499275 0.5377510874999984
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf313 2.77405457184 0 99.580000425 0.5099995750000034
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf314 6.14799414721 0 99.54800025 0.5419997499999966
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf315 2.50228643329 0 98.917000175 1.1594997374999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf316 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf317 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf318 3.92040413524 0 99.55649935 0.533500650000002
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf319 2.47778695782 0 99.265 0.6374999999999957
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf320 2.47124761202 0 98.317499 2.0587514999999996
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf321 3.33055390722 0 99.427499975 0.6625000249999943
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf322 2.50228643329 0 99.00349965 1.0297505250000043
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf323 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf324 6.30106886729 0 99.4665007 0.6234993000000003
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf325 4.93072604433 0 99.518999775 0.5710002250000002
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf326 5.92620561097 0 99.542499525 0.5475004750000011
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf327 3.86059861244 0 99.55699975 0.533000249999995
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf328 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf329 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf330 2.50228643329 0 99.3734996 0.47475059999999303
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf331 6.14799414721 0 99.50849975 0.5815002499999992
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf332 2.81322619695 0 99.33399895 0.5340015750000049
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf333 2.50228643329 0 99.375999975 0.47100003749999786
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf334 3.92040413524 0 99.546999 0.5430009999999982
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf335 6.30106886729 0 99.43900055 0.6509994499999948
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf336 3.85964385182 0 99.4830001 0.6069998999999996
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf337 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf338 5.02870270579 0 99.470500275 0.6194997249999915
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf339 2.50228643329 0 98.750500325 1.40924951249999
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf340 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf341 2.81322619695 0 99.540999625 0.549000375
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf342 5.02870270579 0 99.518000275 0.5719997249999921
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf343 6.30106886729 0 99.462500575 0.6274994249999907
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf344 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf345 5.02870270579 0 99.259499975 0.6457500375000009
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf346 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf347 2.50228643329 0 98.88849885 1.2022517249999893
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf348 2.50228643329 0 99.401999825 0.6880001749999934
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf349 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf350 2.50228643329 0 98.31600045 2.0609993249999903
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf351 3.85964385182 0 99.441 0.6489999999999952
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf352 2.50228643329 0 99.0334995 0.9847507499999892
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf353 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf354 2.50228643329 0 99.443500275 0.6464997249999925
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf355 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf356 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf357 2.81322619695 0 99.57849965 0.51150035
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf358 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf359 2.50228643329 0 99.42499965 0.665000349999994
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf360 2.50228643329 0 98.90749945 1.173750824999992
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf361 3.38717868509 0 99.3249995 0.5475007499999904
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf362 2.50228643329 0 99.01050035 1.0192494749999952
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf363 2.50228643329 0 99.37949865 0.46575202499999335
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf364 2.50228643329 0 98.987000375 1.0544994375000059
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf365 2.50228643329 0 99.467501025 0.6224989749999935
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf366 3.38717868509 0 99.533499175 0.5565008249999949
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf367 5.02870270579 0 99.465000275 0.6249997250000036
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf368 2.50228643329 0 98.8994997 1.1857504499999862
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf369 2.50228643329 0 99.095000075 0.8924998874999943
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf370 6.30106886729 0 99.465499825 0.6245001750000029
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf371 5.02870270579 0 99.480000725 0.6099992750000013
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf372 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf373 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf374 3.85964385182 0 99.462000625 0.627999374999996
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf375 3.38717868509 0 99.583499875 0.5065001249999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf376 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf377 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf378 6.30106886729 0 99.504999975 0.5850000249999937
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf379 6.30106886729 0 99.258500625 0.647249062500002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf380 2.50228643329 0 99.290000375 0.5999994374999886
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf381 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf382 5.02870270579 0 99.439500025 0.6504999749999968
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf383 2.50228643329 0 97.8925002 2.6962496999999956
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf384 3.38717868509 0 99.55950045 0.5304995499999962
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf385 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf386 6.30106886729 0 99.435499425 0.6545005749999945
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf387 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf388 2.47124761202 0 99.21699935 0.7095009750000045
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf389 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf390 6.14799414721 0 99.512499525 0.5775004750000022
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf391 6.14799414721 0 99.496000075 0.593999925
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf392 6.30106886729 0 99.256499475 0.6502507874999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf393 4.90489779833 0 99.41399975 0.6760002499999956
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf394 2.50228643329 0 99.37949885 0.46575172499998985
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf395 2.00016617632 0 99.519997 0.5700029999999942
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf396 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf397 6.10789096832 0 99.40799955 0.6820004499999982
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf398 4.93072604433 0 99.4785008 0.6114991999999916
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf399 2.47778695782 0 99.044499725 0.9682504125000051
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf400 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf401 3.92040413524 0 99.549000125 0.5409998749999915
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf402 4.78704248134 0 99.557500025 0.5324999750000018
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf403 3.92040413524 0 99.339499575 0.5257506374999892
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf404 3.77195447337 0 99.64400015 0.4459998500000012
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf405 2.78229733114 0 99.515498725 0.5745012749999973
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf406 1.99590274244 0 99.580002 0.5099980000000045
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf407 3.38717868509 0 99.539999575 0.5500004250000018
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf408 2.50228643329 0 99.28500105 0.6074984249999886
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf409 6.30106886729 0 99.4274997 0.6625002999999993
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf410 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf411 3.86059861244 0 99.61500045 0.47499955000000116
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf412 3.7862916372 0 99.422500375 0.6674996249999993
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf413 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf414 2.81322619695 0 99.592500325 0.4974996749999946
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf415 6.10789096832 0 99.3419997 0.5220004499999931
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf416 6.14799414721 0 99.461500375 0.6284996249999978
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf417 3.85964385182 0 99.4770005 0.6129994999999951
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf418 6.14799414721 0 99.508999875 0.5810001249999971
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf419 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf420 2.50228643329 0 99.3769985 0.4695022499999979
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf421 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf422 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf423 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf424 6.30106886729 0 99.4700003 0.6199997000000025
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf425 6.30106886729 0 99.45350025 0.636499749999993
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf426 3.84474688915 0 99.56299955 0.5270004499999971
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf427 2.81322619695 0 99.578000175 0.5119998249999981
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf428 2.47124761202 0 99.12450055 0.8482491750000065
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf429 4.90489779833 0 99.5894995 0.5005004999999955
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf430 2.47778695782 0 99.179000625 0.7664990624999959
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf431 3.86059861244 0 99.49899945 0.5910005499999983
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf432 2.50228643329 0 99.2835007 0.6097489499999895
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf433 3.38717868509 0 99.567999775 0.5220002249999937
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf434 6.14799414721 0 99.548998875 0.5410011250000025
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf435 2.77405457184 0 99.736499925 0.3535000749999938
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf436 4.93072604433 0 99.5544993 0.5355006999999944
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf437 4.90489779833 0 99.329499025 0.5407514624999905
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf438 5.02870270579 0 99.475999575 0.6140004249999947
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf439 6.30106886729 0 99.5009997 0.5890003000000036
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf440 3.80166404425 0 99.50849925 0.5815007499999979
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf441 6.30106886729 0 99.434000275 0.6559997249999953
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf442 6.14799414721 0 99.41999995 0.6700000499999931
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf443 3.85964385182 0 99.47000065 0.6199993499999948
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf444 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf445 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf446 6.14799414721 0 99.50449985 0.5855001499999958
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf447 3.38717868509 0 99.582499575 0.5075004249999978
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf448 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf449 3.38717868509 0 99.543499525 0.5465004749999963
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf450 2.00016617632 0 98.220001 2.204998500000002
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf451 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf452 6.30106886729 0 99.442500275 0.6474997249999973
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf453 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf454 2.50228643329 0 99.292000475 0.5969992875000045
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf455 2.44096937877 0 99.3534991 0.5047513500000065
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf456 2.50228643329 0 98.90349965 1.1797505249999958
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf457 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf458 2.47778695782 0 99.26350005 0.6397499249999896
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf459 4.93072604433 0 99.5080002 0.5819997999999998
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf460 2.81322619695 0 99.578999925 0.5110000749999927
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf461 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf462 3.92040413524 0 99.556999575 0.5330004249999917
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf463 2.50228643329 0 99.371499375 0.477750937499998
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf464 6.14799414721 0 99.41999945 0.6700005499999918
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf465 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf466 2.47124761202 0 98.272500275 2.1262495874999985
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf467 3.85964385182 0 99.4570007 0.632999300000003
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf468 6.10789096832 0 99.412499925 0.6775000749999919
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf469 6.30106886729 0 99.4435008 0.6464992000000024
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf470 2.47124761202 0 98.813000175 1.315499737499998
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf471 3.86059861244 0 99.49750055 0.5924994499999997
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf472 3.92040413524 0 99.553499375 0.5365006249999965
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf473 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf474 2.50228643329 0 99.40199945 0.6880005499999925
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf475 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf476 6.14799414721 0 99.4554998 0.6345001999999994
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf477 2.50228643329 0 99.3669987 0.48450195000000207
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf478 2.77405457184 0 99.7349998 0.35500020000000065
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf479 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf480 2.50228643329 0 99.00699965 1.0245005250000006
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf481 6.14799414721 0 99.540999725 0.5490002749999917
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf482 3.33055390722 0 99.7384998 0.35150019999999815
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf483 3.7862916372 0 99.594000025 0.49599997499999804
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf484 6.10789096832 0 99.580000225 0.5099997749999915
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf485 2.47124761202 0 99.50349965 0.5865003500000029
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf486 2.50228643329 0 99.19349965 0.7447505249999864
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf487 6.30106886729 0 99.457000125 0.6329998750000044
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf488 3.38717868509 0 99.471999825 0.6180001750000003
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf489 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf490 3.86059861244 0 99.607000275 0.48299972499999344
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf491 6.10789096832 0 99.334499875 0.5332501874999878
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf492 3.80166404425 0 99.413499775 0.6765002249999924
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf493 5.02870270579 0 99.448500525 0.6414994749999977
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf494 2.47124761202 0 99.21199905 0.7170014249999923
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf495 2.00016617632 0 98.980003 1.064995500000002
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf496 6.14799414721 0 99.503000075 0.586999924999995
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf497 2.50228643329 0 99.098501075 0.8872483874999944
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf498 5.02870270579 0 99.274000025 0.6239999624999868
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf499 4.90489779833 0 99.58150035 0.5084996499999989
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf500 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf501 3.85964385182 0 99.44050065 0.6494993499999936
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf502 2.50228643329 0 99.362999025 0.49050146250000637
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf503 3.86059861244 0 99.607500325 0.482499674999994
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf504 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf505 5.02870270579 0 99.439999975 0.6500000249999914
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf506 2.47778695782 0 99.422999625 0.667000374999995
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf507 3.80166404425 0 99.517499625 0.5725003749999985
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf508 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf509 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf510 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf511 2.50228643329 0 99.437500525 0.6524994749999934
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf512 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf513 6.30106886729 0 99.505500025 0.5844999749999943
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf514 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf515 5.02870270579 0 99.473500475 0.6164995250000033
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf516 3.38717868509 0 99.340999725 0.5235004124999918
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf517 3.92040413524 0 99.55600015 0.5339998499999951
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf518 2.81322619695 0 99.582499875 0.5075001250000014
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf519 5.02870270579 0 99.434999875 0.6550001249999952
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf520 5.02870270579 0 99.471500325 0.6184996750000039
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf521 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf522 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf523 3.38717868509 0 99.560999675 0.5290003249999927
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf524 3.85964385182 0 99.438000125 0.6519998749999957
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf525 2.50228643329 0 99.382499475 0.46125078749999204
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf526 2.50228643329 0 99.464500775 0.625499224999993
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf527 3.38717868509 0 99.577499825 0.5125001749999939
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf528 2.50228643329 0 98.99950025 1.0357496250000011
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf529 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf530 2.50228643329 0 99.387999225 0.45300116249999434
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf531 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf532 2.01610051566 0 97.879997 2.715004499999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf533 2.50228643329 0 99.0314993 0.9877510500000071
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf534 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf535 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf536 2.50228643329 0 98.74550055 1.4167491749999925
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf537 6.30106886729 0 99.462 0.6279999999999945
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf538 3.92040413524 0 99.32449935 0.548250975000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf539 3.85964385182 0 99.470000825 0.6199991749999981
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf540 2.50228643329 0 99.37150005 0.4777499250000048
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf541 6.30106886729 0 99.44350025 0.6464997499999982
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf542 6.30106886729 0 99.456000225 0.6339997750000009
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf543 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf544 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf545 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf546 5.02870270579 0 99.516499975 0.5735000249999956
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf547 2.01610051566 0 97.620003 3.104995500000001
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf548 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf549 3.38717868509 0 99.546999725 0.5430002749999915
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf550 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf551 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf552 3.92040413524 0 99.542999425 0.5470005749999928
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf553 3.38717868509 0 99.472000875 0.6179991249999915
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf554 2.50228643329 0 99.0099999 1.0200001500000013
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf555 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf556 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf557 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf558 3.85964385182 0 99.272500475 0.626249287499995
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf559 6.30106886729 0 99.43700055 0.6529994500000044
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf560 2.50228643329 0 98.316000025 2.0609999625000057
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf561 3.38717868509 0 99.5814995 0.508500499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf562 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf563 2.50228643329 0 97.960999825 2.593500262499994
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf564 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf565 6.30106886729 0 99.276000625 0.6209990625000046
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf566 2.50228643329 0 98.91400005 1.1639999249999988
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf567 3.92040413524 0 99.577500375 0.5124996249999981
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf568 2.50228643329 0 99.423500325 0.6664996749999915
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf569 3.85964385182 0 99.477500425 0.6124995749999954
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf570 2.47778695782 0 99.413500025 0.676499974999993
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf571 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf572 6.14799414721 0 99.504500025 0.5854999749999991
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf573 3.84474688915 0 99.570000775 0.5199992250000008
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf574 2.47778695782 0 99.013500075 1.0147498875000025
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf575 2.47124761202 0 99.385499425 0.4567508624999874
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf576 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf577 2.81322619695 0 99.545499275 0.5445007250000004
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf578 5.02870270579 0 99.44550065 0.6444993499999981
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf579 2.50228643329 0 99.1870008 0.7544987999999861
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf580 2.78229733114 0 99.51649875 0.5735012500000011
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf581 5.92620561097 0 99.553999775 0.5360002250000037
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf582 2.50228643329 0 99.368498525 0.4822522124999864
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf583 3.38717868509 0 99.547499275 0.5425007249999908
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf584 2.78229733114 0 99.57900015 0.5109998499999989
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf585 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf586 2.50228643329 0 99.375499 0.4717514999999892
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf587 2.81322619695 0 99.47250045 0.6174995499999995
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf588 2.50228643329 0 99.28450095 0.6082485750000046
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf589 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf590 6.14799414721 0 99.5135004 0.5764995999999997
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf591 6.14799414721 0 99.4965 0.5935000000000002
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf592 3.34244261096 0 99.561499825 0.5285001749999992
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf593 2.50228643329 0 99.029999175 0.990001237499996
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf594 6.30106886729 0 99.442000175 0.6479998249999938
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf595 2.47778695782 0 99.453499975 0.636500024999998
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf596 3.92040413524 0 99.56400005 0.5259999499999936
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf597 6.10789096832 0 99.339999275 0.5250010875000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf598 2.47124761202 0 99.3599983 0.49500254999999527
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf599 2.50228643329 0 99.469500725 0.6204992749999946
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf600 2.81322619695 0 99.589500425 0.5004995750000006
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf601 6.30106886729 0 99.2495001 0.6607498499999878
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf602 3.80166404425 0 99.522498725 0.5675012749999923
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf603 2.77405457184 0 99.742999825 0.34700017499999947
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf604 6.14799414721 0 99.5524999 0.5375000999999969
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf605 6.30106886729 0 99.446000725 0.6439992749999931
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf606 4.93072604433 0 99.47500045 0.6149995500000017
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf607 3.38717868509 0 99.574000075 0.515999924999997
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf608 3.33055390722 0 99.73199955 0.35800045000000014
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf609 3.92040413524 0 99.575000325 0.5149996749999929
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf610 4.90489779833 0 99.31799945 0.5580008249999935
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf611 6.30106886729 0 99.466000575 0.6239994250000024
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf612 6.14799414721 0 99.46900035 0.620999649999996
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf613 6.10789096832 0 99.4139997 0.6760002999999927
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf614 3.7862916372 0 99.3359989 0.5310016499999861
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf615 2.47778695782 0 99.5030006 0.5869994000000048
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf616 3.34244261096 0 99.577500025 0.5124999749999916
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf617 3.92040413524 0 99.5005001 0.5894999000000013
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf618 6.14799414721 0 99.420000025 0.6699999750000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf619 2.47778695782 0 99.4209994 0.6690005999999983
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf620 2.47124761202 0 99.224499975 0.6982500374999958
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf621 6.30106886729 0 99.428499925 0.6615000750000007
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf622 3.85964385182 0 99.435500575 0.6544994249999917
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf623 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf624 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf625 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf626 3.84474688915 0 99.7199993 0.37000069999999996
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf627 3.86059861244 0 99.49699995 0.5930000499999949
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf628 3.92040413524 0 99.320000325 0.5549995125000038
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf629 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf630 3.85964385182 0 99.523999725 0.5660002750000018
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf631 1.97610564729 0 99.660004 0.42999599999999705
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf632 6.30106886729 0 99.512499875 0.5775001249999946
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf633 2.78229733114 0 99.576000025 0.5139999749999987
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf634 6.10789096832 0 99.57550015 0.5144998500000014
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf635 4.90489779833 0 99.329999825 0.5400002624999942
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf636 3.34244261096 0 99.58599985 0.5040001500000045
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf637 1.97610564729 0 99.379997 0.46500449999999205
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf638 6.30106886729 0 99.455499575 0.6345004249999932
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf639 3.85964385182 0 99.263500425 0.639749362499991
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf640 6.14799414721 0 99.422499575 0.6675004249999944
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf641 2.47778695782 0 99.417500075 0.6724999249999911
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf642 6.14799414721 0 99.490500175 0.5994998250000038
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf643 2.50228643329 0 99.374999575 0.4725006374999907
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf644 2.50228643329 0 99.011500375 1.017749437500001
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf645 1.99590274244 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf646 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf647 2.47778695782 0 99.503999925 0.5860000749999955
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf648 6.10789096832 0 99.33900025 0.5264996249999996
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf649 6.10789096832 0 99.4024996 0.687500399999999
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf650 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf651 2.50228643329 0 98.8884997 1.202250450000001
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf652 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf653 3.92040413524 0 99.47850045 0.6114995499999992
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf654 3.77195447337 0 99.641501475 0.4484985249999994
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf655 5.02870270579 0 99.2675 0.6337499999999991
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf656 6.30106886729 0 99.470500425 0.6194995750000004
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf657 2.47778695782 0 99.435000375 0.6549996249999964
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf658 6.30106886729 0 99.43799965 0.652000350000003
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf659 2.50228643329 0 98.3299994 2.0400008999999883
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf660 6.14799414721 0 99.508499725 0.5815002750000048
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf661 3.38717868509 0 99.33649845 0.5302523250000064
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf662 2.81322619695 0 99.5795002 0.5104997999999995
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf663 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf664 2.47124761202 0 99.494999875 0.5950001249999929
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf665 3.80166404425 0 99.47750075 0.6124992499999934
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf666 3.86059861244 0 99.58 0.5099999999999995
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf667 6.30106886729 0 99.441500025 0.6484999750000014
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf668 1.99590274244 0 98.440002 1.8749969999999863
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf669 3.80166404425 0 99.525999075 0.5640009249999963
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf670 2.47124761202 0 99.323999 0.5490014999999957
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf671 2.50228643329 0 98.73550015 1.4317497750000072
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf672 6.30106886729 0 99.265999825 0.636000262500005
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf673 6.14799414721 0 99.4690007 0.6209993000000026
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf674 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf675 4.78704248134 0 99.554999925 0.5350000749999936
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf676 6.14799414721 0 99.559499325 0.5305006749999933
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf677 2.50228643329 0 99.29100025 0.5984996250000023
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf678 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf679 2.50228643329 0 99.366998475 0.4845022874999927
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf680 2.50228643329 0 97.97399995 2.5740000749999865
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf681 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf682 3.92040413524 0 99.5735001 0.5164998999999938
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf683 2.50228643329 0 99.032999775 0.9855003375000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf684 2.50228643329 0 99.280000725 0.6149989125000062
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf685 2.50228643329 0 98.88899965 1.201500524999993
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf686 2.50228643329 0 99.195000075 0.7424998875000028
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf687 2.50228643329 0 99.018499825 1.007250262499987
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf688 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf689 3.85964385182 0 99.27300055 0.6254991749999874
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf690 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf691 6.30106886729 0 99.468499525 0.6215004749999992
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf692 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf693 3.85964385182 0 99.4565008 0.6334991999999972
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf694 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf695 6.30106886729 0 99.447499925 0.6425000749999953
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf696 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf697 6.30106886729 0 99.501999875 0.5880001250000021
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf698 5.02870270579 0 99.467500675 0.6224993250000012
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf699 2.50228643329 0 99.435499925 0.6545000749999957
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf700 2.50228643329 0 99.4214999 0.6685000999999972
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf701 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf702 3.85964385182 0 99.47450035 0.6154996499999982
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf703 2.81322619695 0 99.4615009 0.6284990999999934
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf704 2.50228643329 0 98.3229992 2.0505011999999994
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf705 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf706 3.85964385182 0 99.436500175 0.6534998249999916
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf707 6.30106886729 0 99.43250055 0.6574994499999974
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf708 3.92040413524 0 99.559498975 0.530501025000001
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf709 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf710 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf711 2.50228643329 0 97.63800065 3.077999025000004
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf712 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf713 3.92040413524 0 99.318500375 0.5572494374999977
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf714 2.50228643329 0 98.90349935 1.1797509749999904
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf715 3.92040413524 0 99.5524996 0.5375003999999933
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf716 6.30106886729 0 99.2610001 0.6434998499999907
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf717 6.30106886729 0 99.446500275 0.6434997249999924
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf718 3.38717868509 0 99.567999775 0.5220002249999937
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf719 2.50228643329 0 99.101000225 0.883499662499986
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf720 3.85964385182 0 99.478500775 0.6114992249999972
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf721 2.47778695782 0 99.39299885 0.6970011499999998
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf722 3.85964385182 0 99.528499175 0.5615008250000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf723 6.14799414721 0 99.460000125 0.6299998750000043
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf724 2.50228643329 0 99.46000075 0.6299992499999917
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf725 3.92040413524 0 99.332999525 0.5355007124999887
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf726 3.80166404425 0 99.570999825 0.5190001749999965
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf727 2.47778695782 0 99.303500625 0.5797490624999995
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf728 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf729 3.92040413524 0 99.4830003 0.6069996999999973
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf730 6.30106886729 0 99.519000275 0.5709997250000015
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf731 5.02870270579 0 99.5234998 0.5665002000000016
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf732 3.86059861244 0 99.611500325 0.47849967500000334
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf733 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf734 2.50228643329 0 99.033498825 0.9847517625000037
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf735 3.38717868509 0 99.3329991 0.5355013500000041
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf736 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf737 6.14799414721 0 99.50600015 0.5839998499999922
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf738 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf739 3.34244261096 0 99.5624996 0.5275004000000024
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf740 2.47124761202 0 99.36199835 0.4920024750000067
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf741 6.14799414721 0 99.5104998 0.5795001999999926
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf742 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf743 2.81322619695 0 99.333499225 0.534751162500001
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf744 1.99590274244 0 99.599998 0.4900019999999984
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf745 3.38717868509 0 99.5830001 0.5069998999999911
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf746 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf747 2.81322619695 0 99.587500225 0.5024997749999983
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf748 3.85964385182 0 99.462500975 0.6274990250000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf749 6.30106886729 0 99.44100045 0.6489995499999935
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf750 3.86059861244 0 99.5044995 0.5855005000000034
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf751 6.10789096832 0 99.337499975 0.5287500374999965
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf752 3.92040413524 0 99.580999475 0.509000524999999
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf753 2.50228643329 0 99.394999575 0.6950004249999978
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf754 6.14799414721 0 99.420499375 0.6695006249999921
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf755 2.47778695782 0 99.374499425 0.47325086250000226
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf756 6.30106886729 0 99.43549985 0.6545001499999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf757 2.50228643329 0 99.43300005 0.6569999499999938
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf758 3.84474688915 0 99.4280003 0.6619997000000041
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf759 5.92620561097 0 99.533499625 0.5565003749999932
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf760 6.10789096832 0 99.575999775 0.5140002249999981
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf761 6.10789096832 0 99.40649965 0.6835003499999971
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf762 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf763 6.14799414721 0 99.505500225 0.584499774999992
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf764 2.47778695782 0 99.322999075 0.5505013874999989
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf765 6.30106886729 0 99.4675 0.6224999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf766 4.90489779833 0 99.32749945 0.5437508249999894
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf767 3.85964385182 0 99.432499925 0.6575000749999959
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf768 6.10789096832 0 99.578999975 0.5110000249999956
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf769 4.93072604433 0 99.5179994 0.5720006000000041
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf770 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf771 3.86059861244 0 99.557999225 0.5320007749999945
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf772 2.78229733114 0 99.614500525 0.4754994750000009
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf773 5.02870270579 0 99.432000675 0.6579993250000001
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf774 4.93072604433 0 99.517499825 0.5725001749999962
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf775 2.47778695782 0 99.4125002 0.6774998000000011
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf776 3.77195447337 0 99.6390002 0.4509997999999996
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf777 2.81322619695 0 99.538499125 0.5515008749999964
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf778 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf779 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf780 3.92040413524 0 99.4845006 0.6054993999999937
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf781 6.30106886729 0 99.501500475 0.5884995249999975
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf782 2.77405457184 0 99.736499225 0.3535007749999949
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf783 3.84474688915 0 99.42049985 0.669500149999999
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf784 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf785 2.50228643329 0 99.36849925 0.48225112499999767
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf786 6.30106886729 0 99.465499775 0.6245002249999999
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf787 3.85964385182 0 99.481500875 0.608499125000003
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf788 3.80166404425 0 99.42100005 0.6689999499999942
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf789 4.93072604433 0 99.511499675 0.5785003250000017
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf790 6.14799414721 0 99.5054997 0.5845002999999963
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf791 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf792 2.44096937877 0 99.4470006 0.6429994000000022
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf793 2.47778695782 0 98.260500175 2.1442497374999903
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf794 6.10789096832 0 99.33799975 0.5280003750000049
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf795 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf796 2.44096937877 0 99.353998575 0.5040021374999881
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf797 2.50228643329 0 99.42099945 0.6690005500000012
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf798 6.30106886729 0 99.442500625 0.6474993750000039
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf799 6.30106886729 0 99.428500225 0.6614997750000043
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf800 3.92040413524 0 99.56549965 0.5245003499999911
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf801 2.47124761202 0 99.185500075 0.7567498875000069
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf802 3.92040413524 0 99.53350015 0.556499850000003
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf803 6.14799414721 0 99.5049996 0.5850003999999928
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf804 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf805 2.00016617632 0 98.379997 1.965004499999992
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf806 6.14799414721 0 99.464499625 0.6255003749999958
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf807 1.99590274244 0 98.660004 1.5449939999999955
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf808 3.85964385182 0 99.53049925 0.5595007499999923
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf809 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf810 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf811 3.86059861244 0 99.591500125 0.4984998750000017
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf812 2.50228643329 0 99.382499425 0.4612508624999876
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf813 2.47124761202 0 98.818999725 1.3065004125000002
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf814 3.86059861244 0 99.6200006 0.4699994000000004
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf815 2.73595882486 0 99.6375013 0.45249870000000103
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf816 6.14799414721 0 99.545999725 0.5440002749999963
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf817 3.7862916372 0 99.3424988 0.5212517999999946
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf818 2.77405457184 0 99.4264998 0.6635001999999958
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf819 2.50228643329 0 99.0920006 0.896999099999988
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf820 5.02870270579 0 99.476000675 0.6139993250000032
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf821 3.92040413524 0 99.3214991 0.5527513500000012
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf822 2.47124761202 0 98.535999325 1.7310010124999877
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf823 2.78229733114 0 99.551999525 0.5380004749999984
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf824 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf825 3.85964385182 0 99.473999875 0.6160001249999937
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf826 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf827 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf828 6.30106886729 0 99.46050055 0.6294994499999916
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf829 2.50228643329 0 99.4435005 0.6464994999999988
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf830 2.81322619695 0 99.538499475 0.551500525000003
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf831 2.50228643329 0 98.230000275 2.1899995875000045
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf832 2.50228643329 0 99.466500825 0.6234991750000006
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf833 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf834 6.30106886729 0 99.4185003 0.6714996999999926
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf835 2.50228643329 0 98.889999625 1.2000005624999943
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf836 3.38717868509 0 99.478001025 0.6119989750000002
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf837 5.02870270579 0 99.467500025 0.622499974999991
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf838 2.50228643329 0 99.389499275 0.45075108749998805
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf839 2.81322619695 0 99.472000525 0.6179994749999992
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf840 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf841 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf842 3.85964385182 0 99.52599925 0.5640007499999996
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf843 2.50228643329 0 99.29100025 0.5984996250000023
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf844 3.92040413524 0 99.5589993 0.5310007000000013
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf845 3.85964385182 0 99.47500025 0.6149997500000041
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf846 3.85964385182 0 99.469500475 0.620499524999994
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf847 3.92040413524 0 99.48150035 0.6084996499999932
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf848 3.92040413524 0 99.536 0.5539999999999964
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf849 2.50228643329 0 99.4420006 0.6479993999999977
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf850 2.50228643329 0 97.654500925 3.0532486125000062
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf851 6.30106886729 0 99.4430001 0.6469998999999916
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf852 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf853 5.02870270579 0 99.458000775 0.6319992249999956
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf854 3.38717868509 0 99.329499675 0.5407504875000058
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf855 2.50228643329 0 98.3030002 2.080499699999997
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf856 3.92040413524 0 99.33299985 0.5355002250000069
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf857 2.01610051566 0 97.900002 2.6849969999999956
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf858 2.01610051566 0 97.620003 3.104995500000001
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf859 3.38717868509 0 99.57400005 0.5159999500000026
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf860 3.92040413524 0 99.542999475 0.5470005249999957
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf861 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf862 6.30106886729 0 99.504999775 0.585000224999996
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf863 2.50228643329 0 99.096000725 0.8909989125000024
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf864 2.50228643329 0 99.368999175 0.48150123749999807
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf865 6.30106886729 0 99.24349955 0.6697506750000031
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf866 5.02870270579 0 99.48200025 0.6079997499999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf867 5.02870270579 0 99.43700025 0.6529997500000008
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf868 2.50228643329 0 99.370499525 0.4792507124999972
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf869 2.50228643329 0 99.41749965 0.6725003500000014
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf870 3.85964385182 0 99.431000575 0.658999424999999
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf871 6.30106886729 0 99.46350045 0.6264995499999998
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf872 5.02870270579 0 99.512999425 0.5770005749999939
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf873 5.02870270579 0 99.269500575 0.630749137500004
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf874 2.50228643329 0 99.180999675 0.7635004875000035
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf875 2.50228643329 0 99.409499525 0.6805004749999967
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf876 2.50228643329 0 98.9994999 1.0357501499999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf877 2.47778695782 0 99.42899995 0.6610000499999927
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf878 3.38717868509 0 99.483500225 0.6064997749999975
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf879 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf880 3.33055390722 0 99.4320002 0.6579997999999933
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf881 3.33055390722 0 99.5704994 0.519500599999995
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf882 3.86059861244 0 99.610500025 0.4794999750000045
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf883 2.81322619695 0 99.577000375 0.5129996250000005
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf884 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf885 2.47778695782 0 99.40549945 0.6845005500000042
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf886 3.38717868509 0 99.569 0.5209999999999951
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf887 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf888 2.50228643329 0 99.43799995 0.6520000499999924
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf889 2.50228643329 0 99.473001075 0.6169989249999986
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf890 6.14799414721 0 99.555999325 0.5340006749999958
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf891 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf892 4.90489779833 0 99.4159999 0.674000099999995
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf893 4.90489779833 0 99.3299996 0.5400006000000062
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf894 4.93072604433 0 99.52499955 0.5650004499999938
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf895 3.86059861244 0 99.506999625 0.5830003749999918
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf896 3.86059861244 0 99.582499975 0.5075000249999931
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf897 3.92040413524 0 99.542500075 0.5474999249999911
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf898 2.47778695782 0 99.442000175 0.6479998249999938
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf899 2.50228643329 0 99.28750065 0.603749024999999
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf900 6.30106886729 0 99.43350035 0.656499649999995
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf901 6.14799414721 0 99.49950045 0.5904995499999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf902 5.02870270579 0 99.47200005 0.6179999499999923
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf903 3.34244261096 0 99.613500575 0.4764994249999944
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf904 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf905 3.7862916372 0 99.41650005 0.6734999500000015
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf906 6.14799414721 0 99.455000325 0.6349996749999974
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf907 2.50228643329 0 99.4335006 0.6564993999999956
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf908 6.14799414721 0 99.50550005 0.5844999500000029
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf909 2.47124761202 0 99.319999725 0.555000412499993
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf910 2.50228643329 0 99.42550005 0.6644999500000012
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf911 6.10789096832 0 99.56899955 0.5210004499999968
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf912 3.85964385182 0 99.48000055 0.609999449999998
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf913 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf914 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf915 2.44096937877 0 99.01699955 1.0095006750000053
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf916 4.90489779833 0 99.58049985 0.5095001500000024
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf917 2.47124761202 0 99.49900015 0.5909998499999972
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf918 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf919 4.93072604433 0 99.5589997 0.5310002999999966
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf920 5.02870270579 0 99.473000225 0.6169997749999908
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf921 3.92040413524 0 99.55299925 0.5370007499999986
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf922 3.85964385182 0 99.53349935 0.5565006499999982
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf923 6.30106886729 0 99.472000025 0.6179999749999979
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf924 2.50228643329 0 99.182499825 0.7612502625000062
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf925 3.86059861244 0 99.60850085 0.4814991499999991
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf926 6.14799414721 0 99.412 0.6779999999999916
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf927 6.30106886729 0 99.4530003 0.6369996999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf928 6.30106886729 0 99.499999825 0.5900001749999945
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf929 6.10789096832 0 99.407000125 0.6829998750000016
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf930 2.47778695782 0 99.322999475 0.5505007874999919
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf931 6.30106886729 0 99.419000225 0.6709997749999929
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf932 3.80166404425 0 99.48450075 0.6054992500000026
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf933 2.50228643329 0 98.997999775 1.0380003375000015
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf934 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf935 6.30106886729 0 99.467999775 0.6220002250000022
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf936 2.47778695782 0 98.96700135 1.0844979749999908
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf937 3.77195447337 0 99.637001 0.4529989999999998
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf938 6.30106886729 0 99.512999625 0.5770003749999916
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf939 2.47778695782 0 98.9210002 1.1534997000000047
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf940 1.99590274244 0 98.139999 2.325001499999992
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf941 2.47124761202 0 99.3819992 0.4620012000000031
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf942 2.50228643329 0 99.393999775 0.6960002250000002
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf943 2.47778695782 0 99.4064995 0.6835005000000024
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf944 6.14799414721 0 99.41999975 0.6700002499999954
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf945 3.71567552873 0 99.5574991 0.5325008999999966
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf946 4.93072604433 0 99.57149935 0.5185006500000015
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf947 2.00016617632 0 98.419998 1.9050029999999865
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf948 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf949 3.92040413524 0 99.55049875 0.539501249999995
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf950 3.34244261096 0 99.5865 0.5034999999999968
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf951 3.38717868509 0 99.541499675 0.5485003250000006
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf952 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf953 2.50228643329 0 98.90750005 1.1737499250000027
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf954 2.44096937877 0 98.241500025 2.1727499625000064
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf955 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf956 2.50228643329 0 99.439500375 0.6504996250000034
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf957 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf958 3.38717868509 0 99.5725004 0.5174996000000022
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf959 2.50228643329 0 99.001500125 1.0327498124999863
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf960 2.44096937877 0 99.376498775 0.470251837499994
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf961 3.92040413524 0 99.5484993 0.5415006999999946
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf962 1.99590274244 0 98.139999 2.325001499999992
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf963 3.7862916372 0 99.584000125 0.5059998749999949
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf964 2.47124761202 0 99.026499175 0.9952512374999998
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf965 3.80166404425 0 99.516499625 0.5735003750000033
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf966 3.85964385182 0 99.477000125 0.6129998749999942
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf967 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf968 3.86059861244 0 99.56150015 0.5284998499999972
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf969 6.14799414721 0 99.508499775 0.5815002249999935
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf970 2.50228643329 0 98.90099985 1.1835002249999889
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf971 1.99590274244 0 98.660004 1.5449939999999955
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf972 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf973 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf974 2.47124761202 0 98.536999 1.729501500000005
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf975 2.50228643329 0 98.23449995 2.1832500749999966
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf976 6.10789096832 0 99.406999775 0.683000224999995
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf977 6.14799414721 0 99.545499575 0.544500425000004
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf978 3.86059861244 0 99.61050155 0.4794984500000027
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf979 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf980 2.50228643329 0 99.4215 0.6685000000000031
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf981 3.7862916372 0 99.42750005 0.6624999499999916
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf982 3.34244261096 0 99.562499425 0.5275005749999991
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf983 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf984 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf985 2.00016617632 0 98.980003 1.064995500000002
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf986 5.92620561097 0 99.5314992 0.5585007999999988
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf987 2.78229733114 0 99.553500025 0.5364999749999925
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf988 2.47778695782 0 99.183000125 0.7604998124999867
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf989 3.86059861244 0 99.609000625 0.48099937500000467
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf990 3.86059861244 0 99.5019997 0.5880002999999988
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf991 6.30106886729 0 99.457000075 0.6329999250000015
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf992 3.84474688915 0 99.568499675 0.5215003249999995
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf993 6.14799414721 0 99.46 0.630000000000004
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf994 3.38717868509 0 99.3379988 0.5280018000000055
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf995 6.10789096832 0 99.577499425 0.5125005749999986
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf996 3.86059861244 0 99.5895003 0.5004997000000003
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf997 2.50228643329 0 99.37899965 0.4665005250000007
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf998 3.85964385182 0 99.475000975 0.6149990249999974
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf999 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1000 3.92040413524 0 99.559499525 0.530500474999991
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1001 6.30106886729 0 99.427999925 0.6620000750000031
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1002 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1003 2.50228643329 0 98.336499375 2.030250937499993
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1004 3.85964385182 0 99.4305002 0.6594998000000004
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1005 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1006 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1007 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1008 2.50228643329 0 99.2740006 0.623999100000006
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1009 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1010 5.02870270579 0 99.26250005 0.6412499249999968
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1011 2.50228643329 0 99.369499075 0.4807513875000069
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1012 5.02870270579 0 99.44500045 0.6449995500000029
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1013 2.50228643329 0 97.6395004 3.0757493999999923
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1014 5.02870270579 0 99.474500525 0.6154994750000015
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1015 3.92040413524 0 99.492000325 0.5979996749999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1016 3.92040413524 0 99.331499525 0.5377507124999994
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1017 6.30106886729 0 99.426500225 0.6634997749999997
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1018 3.38717868509 0 99.543499225 0.5465007749999927
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1019 3.38717868509 0 99.335999 0.531001499999995
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1020 3.92040413524 0 99.5434993 0.5465007000000043
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1021 2.50228643329 0 99.002499975 1.0312500374999871
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1022 3.38717868509 0 99.586500475 0.5034995250000037
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1023 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1024 5.02870270579 0 99.51149985 0.5785001499999908
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1025 3.85964385182 0 99.2685002 0.6322496999999885
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1026 2.81322619695 0 99.546999225 0.5430007750000044
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1027 3.38717868509 0 99.47600085 0.6139991499999923
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1028 2.81322619695 0 99.588999925 0.5010000750000018
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1029 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1030 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1031 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1032 2.50228643329 0 98.9885 1.0522499999999937
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1033 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1034 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1035 6.30106886729 0 99.516000025 0.573999975000001
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1036 6.30106886729 0 99.2645006 0.6382490999999888
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1037 6.30106886729 0 99.45900045 0.6309995499999929
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1038 2.50228643329 0 99.369999225 0.48000116249999536
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1039 2.50228643329 0 99.37249935 0.47625097499999924
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1040 5.02870270579 0 99.4795001 0.6104999000000021
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1041 2.50228643329 0 99.469000975 0.6209990249999976
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1042 6.30106886729 0 99.45850035 0.6314996500000035
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1043 2.81322619695 0 99.33899865 0.5265020250000063
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1044 3.85964385182 0 99.531499475 0.5585005249999938
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1045 3.85964385182 0 99.470500225 0.6194997750000028
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1046 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1047 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1048 2.47124761202 0 99.19199955 0.7470006749999882
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1049 2.00016617632 0 99.620003 0.4699970000000008
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1050 2.50228643329 0 99.43900005 0.6509999499999936
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1051 2.50228643329 0 99.035499225 0.9817511625000037
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1052 6.10789096832 0 99.575000075 0.5149999249999923
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1053 2.47124761202 0 99.26700025 0.6344996250000037
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1054 2.44096937877 0 99.011999775 1.0170003374999865
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1055 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1056 4.93072604433 0 99.5204999 0.5695000999999934
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1057 3.92040413524 0 99.576999675 0.5130003250000016
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1058 6.14799414721 0 99.550499275 0.5395007249999907
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1059 6.10789096832 0 99.41649995 0.6735000499999956
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1060 6.14799414721 0 99.45850075 0.6314992499999988
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1061 2.47778695782 0 99.001499775 1.0327503374999978
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1062 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1063 2.50228643329 0 99.419999775 0.670000225000004
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1064 2.50228643329 0 99.01399965 1.014000524999993
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1065 3.85964385182 0 99.457500475 0.6324995249999944
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1066 4.90489779833 0 99.413499575 0.6765004249999947
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1067 2.50228643329 0 99.363998825 0.4890017625000027
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1068 2.47778695782 0 99.4510009 0.6389991000000009
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1069 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1070 2.44096937877 0 99.3414992 0.5227511999999948
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1071 3.92040413524 0 99.46549975 0.6245002499999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1072 6.14799414721 0 99.502499625 0.5875003749999991
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1073 5.02870270579 0 99.26700025 0.6344996250000037
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1074 6.10789096832 0 99.327999975 0.5430000375000006
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1075 3.7862916372 0 99.425500025 0.6644999749999926
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1076 3.80166404425 0 99.519499 0.5705010000000016
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1077 2.47778695782 0 99.3090006 0.5714990999999898
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1078 2.78229733114 0 99.5504996 0.5395004000000029
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1079 6.14799414721 0 99.5105 0.5795000000000045
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1080 2.47124761202 0 99.356998675 0.49950198749999686
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1081 3.92040413524 0 99.551499975 0.538500024999999
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1082 3.92040413524 0 99.5609997 0.5290003000000013
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1083 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1084 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1085 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1086 3.80166404425 0 99.5354992 0.5545007999999939
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1087 6.30106886729 0 99.42449985 0.6655001499999941
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1088 6.30106886729 0 99.510999925 0.5790000750000047
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1089 2.47778695782 0 99.405999625 0.6840003749999909
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1090 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1091 3.38717868509 0 99.54649955 0.5435004500000048
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1092 6.14799414721 0 99.4960001 0.5939998999999944
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1093 6.30106886729 0 99.46200015 0.6279998500000034
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1094 6.30106886729 0 99.263000125 0.6404998124999892
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1095 6.30106886729 0 99.469499875 0.620500125000001
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1096 2.81322619695 0 99.576999575 0.5130004249999957
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1097 3.38717868509 0 99.3319991 0.5370013499999899
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1098 3.86059861244 0 99.6120008 0.47799919999999363
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1099 5.02870270579 0 99.467000225 0.622999774999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1100 4.93072604433 0 99.51999945 0.5700005499999975
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1101 3.86059861244 0 99.5900002 0.499999799999992
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1102 2.50228643329 0 99.0934995 0.8947507500000071
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1103 6.14799414721 0 99.41949945 0.6705005499999942
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1104 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1105 3.7862916372 0 99.331499775 0.5377503375000003
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1106 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1107 5.92620561097 0 99.541999675 0.5480003249999982
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1108 2.77405457184 0 99.5785001 0.5114998999999983
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1109 2.50228643329 0 99.39249935 0.6975006500000035
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1110 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1111 5.02870270579 0 99.5159995 0.5740004999999911
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1112 6.14799414721 0 99.465999875 0.6240001250000035
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1113 2.50228643329 0 99.415999925 0.6740000750000036
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1114 3.34244261096 0 99.60100035 0.488999649999991
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1115 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1116 3.92040413524 0 99.328499625 0.5422505624999872
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1117 3.85964385182 0 99.52999935 0.5600006500000007
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1118 2.50228643329 0 99.098500425 0.8872493625000004
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1119 6.30106886729 0 99.458000075 0.6319999249999967
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1120 2.00016617632 0 99.519997 0.5700029999999942
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1121 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1122 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1123 6.30106886729 0 99.507499575 0.5825004250000007
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1124 3.27579123647 0 99.64050075 0.4494992499999967
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1125 6.14799414721 0 99.49900015 0.5909998499999972
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1126 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1127 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1128 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1129 3.38717868509 0 99.333498075 0.5347528875000052
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1130 3.86059861244 0 99.5950008 0.49499920000000375
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1131 2.78229733114 0 99.580499625 0.5095003749999961
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1132 3.34244261096 0 99.5804993 0.5095006999999981
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1133 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1134 3.86059861244 0 99.592499975 0.49750002500000223
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1135 3.86059861244 0 99.61300085 0.4769991499999918
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1136 6.30106886729 0 99.429000375 0.6609996249999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1137 1.97610564729 0 98.440002 1.8749969999999863
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1138 2.47778695782 0 99.402999625 0.687000374999991
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1139 3.80166404425 0 99.51099975 0.5790002500000014
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1140 2.81322619695 0 99.5854998 0.504500200000004
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1141 2.50228643329 0 99.038999575 0.9765006374999885
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1142 6.30106886729 0 99.4325004 0.6574996000000027
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1143 6.10789096832 0 99.4115002 0.6784997999999917
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1144 6.10789096832 0 99.332999725 0.5355004125000065
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1145 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1146 6.14799414721 0 99.428500075 0.6614999249999954
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1147 3.80166404425 0 99.567500275 0.5224997249999973
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1148 2.50228643329 0 98.29800005 2.0879999249999983
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1149 3.86059861244 0 99.4985004 0.5914996000000002
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1150 3.33055390722 0 99.43350015 0.6564998499999973
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1151 6.30106886729 0 99.477000475 0.6129995250000008
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1152 6.14799414721 0 99.495000225 0.5949997749999995
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1153 2.47778695782 0 98.9710005 1.078499249999993
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1154 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1155 2.44096937877 0 99.014999325 1.012501012499989
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1156 4.93072604433 0 99.483500225 0.6064997749999975
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1157 2.47778695782 0 99.42549995 0.6645000499999952
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1158 2.78229733114 0 99.5529994 0.5370005999999933
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1159 2.78229733114 0 99.605500375 0.48449962499999233
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1160 3.92040413524 0 99.55899965 0.5310003499999937
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1161 5.02870270579 0 99.4565008 0.6334991999999972
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1162 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1163 2.47124761202 0 99.3154995 0.5617507499999945
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1164 6.10789096832 0 99.579999725 0.5100002750000044
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1165 6.30106886729 0 99.262000125 0.6419998124999964
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1166 3.86059861244 0 99.5529991 0.5370009000000039
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1167 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1168 5.02870270579 0 99.253000425 0.6554993625000023
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1169 3.92040413524 0 99.581499875 0.508500124999992
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1170 2.50228643329 0 99.467500525 0.6224994749999923
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1171 2.50228643329 0 98.75049975 1.409250374999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1172 3.38717868509 0 99.5780001 0.5119999000000007
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1173 6.30106886729 0 99.467501075 0.6224989249999965
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1174 5.02870270579 0 99.473000175 0.6169998250000021
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1175 2.01610051566 0 97.879997 2.715004499999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1176 2.50228643329 0 99.3804997 0.46425044999999443
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1177 2.50228643329 0 99.0319994 0.9870008999999911
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1178 3.38717868509 0 99.5639997 0.5260003000000012
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1179 2.50228643329 0 99.185500475 0.7567492874999999
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1180 3.85964385182 0 99.27000015 0.6299997749999946
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1181 6.30106886729 0 99.43400015 0.6559998499999949
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1182 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1183 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1184 2.50228643329 0 99.3659993 0.4860010499999987
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1185 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1186 2.01610051566 0 97.900002 2.6849969999999956
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1187 3.92040413524 0 99.31799965 0.55800052499999
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1188 3.92040413524 0 99.489999925 0.6000000749999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1189 2.50228643329 0 99.394499425 0.6955005749999913
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1190 3.92040413524 0 99.560999775 0.5290002249999987
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1191 6.30106886729 0 99.435999925 0.6540000749999934
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1192 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1193 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1194 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1195 6.30106886729 0 99.455999775 0.6340002250000026
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1196 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1197 3.85964385182 0 99.466000075 0.6239999250000011
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1198 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1199 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1200 6.30106886729 0 99.50349965 0.5865003500000029
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1201 3.38717868509 0 99.476000475 0.6139995249999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1202 2.50228643329 0 98.9125001 1.1662498499999927
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1203 3.92040413524 0 99.55849915 0.5315008499999948
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1204 2.50228643329 0 97.895000075 2.6924998874999986
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1205 2.50228643329 0 99.373498975 0.47475153749999066
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1206 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1207 5.02870270579 0 99.451001075 0.6389989250000042
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1208 2.50228643329 0 99.015499925 1.0117501124999961
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1209 2.50228643329 0 98.9950004 1.042499400000004
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1210 2.81322619695 0 99.5870001 0.5029999000000004
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1211 2.50228643329 0 99.468000825 0.6219991749999935
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1212 2.50228643329 0 99.44400025 0.6459997499999958
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1213 3.38717868509 0 99.581000225 0.5089997750000009
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1214 5.02870270579 0 99.519500225 0.5704997749999962
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1215 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1216 2.81322619695 0 99.5439997 0.5460002999999972
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1217 2.50228643329 0 99.472000875 0.6179991249999915
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1218 2.50228643329 0 99.36899875 0.4815018749999922
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1219 6.30106886729 0 99.263999775 0.6390003374999935
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1220 6.30106886729 0 99.45150035 0.6384996499999943
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1221 3.85964385182 0 99.2720009 0.6269986500000044
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1222 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1223 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1224 2.47124761202 0 99.3569989 0.49950165000000624
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1225 2.47778695782 0 99.005000125 1.0274998125000039
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1226 3.85964385182 0 99.482000425 0.6079995750000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1227 2.50228643329 0 99.193499925 0.7447501125000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1228 5.02870270579 0 99.440000575 0.6499994249999986
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1229 3.85964385182 0 99.535499725 0.5545002750000038
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1230 3.7862916372 0 99.426000075 0.6639999249999932
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1231 6.14799414721 0 99.511999775 0.578000224999991
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1232 6.30106886729 0 99.434500575 0.6554994249999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1233 3.77195447337 0 99.6400006 0.4499994000000044
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1234 3.80166404425 0 99.526999625 0.5630003749999958
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1235 1.99590274244 0 99.580002 0.5099980000000045
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1236 2.47778695782 0 99.029999325 0.9900010124999881
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1237 5.02870270579 0 99.482000275 0.6079997249999934
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1238 2.47778695782 0 99.403499575 0.6865004249999999
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1239 6.10789096832 0 99.323999075 0.5490013874999917
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1240 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1241 2.77405457184 0 99.42650065 0.6634993500000036
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1242 2.50228643329 0 99.438000575 0.651999424999994
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1243 6.30106886729 0 99.243999875 0.6690001874999965
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1244 6.14799414721 0 99.4244999 0.665500099999997
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1245 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1246 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1247 2.50228643329 0 99.02999865 0.9900020250000026
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1248 3.34244261096 0 99.508000025 0.5819999749999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1249 2.47778695782 0 99.48050135 0.6094986500000005
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1250 2.44096937877 0 99.0244998 0.9982502999999951
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1251 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1252 2.47124761202 0 99.38599915 0.4560012749999913
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1253 6.30106886729 0 99.432500225 0.6574997749999995
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1254 3.33055390722 0 99.574000275 0.5159997249999947
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1255 5.02870270579 0 99.268000775 0.63299883749999
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1256 3.92040413524 0 99.543499525 0.5465004749999963
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1257 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1258 6.14799414721 0 99.498500225 0.591499774999997
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1259 3.85964385182 0 99.48400015 0.6059998499999978
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1260 2.50228643329 0 99.2885006 0.6022490999999874
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1261 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1262 5.92620561097 0 99.547499375 0.5425006249999967
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1263 4.93072604433 0 99.42350015 0.6664998500000024
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1264 6.30106886729 0 99.5030001 0.5869999000000036
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1265 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1266 2.00016617632 0 99.379997 0.46500449999999205
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1267 1.99590274244 0 99.099998 0.8850029999999975
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1268 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1269 6.30106886729 0 99.46300005 0.6269999499999926
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1270 2.50228643329 0 99.42400025 0.6659997499999918
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1271 2.00016617632 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1272 3.38717868509 0 99.5705005 0.5194995000000034
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1273 3.86059861244 0 99.622001025 0.46799897499999477
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1274 6.14799414721 0 99.553999775 0.5360002250000037
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1275 6.14799414721 0 99.5039994 0.5860005999999999
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1276 2.81322619695 0 99.59050025 0.4994997499999926
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1277 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1278 6.14799414721 0 99.45850055 0.6314994500000012
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1279 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1280 2.50228643329 0 98.999500425 1.035749362500006
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1281 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1282 2.47124761202 0 99.37799915 0.468001275000006
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1283 4.90489779833 0 99.584500425 0.5054995749999961
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1284 3.80166404425 0 99.423000075 0.6669999249999933
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1285 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1286 5.92620561097 0 99.540499425 0.5495005750000047
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1287 6.30106886729 0 99.47250045 0.6174995499999995
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1288 3.92040413524 0 99.551499425 0.5385005749999948
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1289 2.47124761202 0 98.8219998 1.302000299999996
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1290 4.90489779833 0 99.412499525 0.6775004749999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1291 2.78229733114 0 99.517998175 0.5720018249999953
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1292 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1293 2.47778695782 0 99.43750055 0.652499450000002
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1294 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1295 3.38717868509 0 99.474000925 0.6159990749999992
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1296 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1297 6.10789096832 0 99.406000225 0.6839997749999981
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1298 2.47778695782 0 98.236000025 2.180999962500003
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1299 2.50228643329 0 99.004499675 1.0282504874999887
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1300 2.81322619695 0 99.585500025 0.504499974999996
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1301 2.77405457184 0 99.4325001 0.6574998999999991
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1302 2.50228643329 0 98.298500325 2.0872495124999872
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1303 3.77195447337 0 99.63650085 0.4534991499999933
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1304 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1305 2.47778695782 0 98.9780005 1.0679992500000068
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1306 2.47124761202 0 99.11650015 0.8602497750000069
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1307 6.30106886729 0 99.464500275 0.6254997249999917
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1308 3.7862916372 0 99.584499975 0.5055000249999978
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1309 3.80166404425 0 99.5214992 0.5685008000000039
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1310 2.50228643329 0 99.28400045 0.6089993250000063
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1311 6.14799414721 0 99.515500125 0.5744998749999951
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1312 3.85964385182 0 99.2660004 0.6359994000000029
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1313 2.47124761202 0 99.192499825 0.7462502624999985
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1314 2.47124761202 0 99.2194988 0.7057518000000016
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1315 6.14799414721 0 99.411000025 0.6789999749999908
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1316 6.30106886729 0 99.501499425 0.588500574999992
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1317 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1318 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1319 2.50228643329 0 98.240000175 2.174999737499988
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1320 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1321 2.50228643329 0 99.466000925 0.6239990749999947
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1322 6.14799414721 0 99.503499825 0.586500174999992
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1323 2.47778695782 0 99.322 0.5519999999999925
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1324 2.50228643329 0 99.371498925 0.47775161250000053
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1325 2.47778695782 0 99.42149925 0.6685007500000012
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1326 6.30106886729 0 99.26800005 0.632999925
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1327 6.14799414721 0 99.492500075 0.5974999250000025
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1328 5.02870270579 0 99.4635003 0.6264996999999909
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1329 2.78229733114 0 99.5604995 0.5295004999999918
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1330 1.99590274244 0 98.440002 1.8749969999999863
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1331 2.50228643329 0 99.438000275 0.6519997250000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1332 3.92040413524 0 99.329498225 0.5407526625000045
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1333 2.50228643329 0 99.473000725 0.6169992749999921
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1334 1.97610564729 0 98.480003 1.814995500000002
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1335 6.30106886729 0 99.4390005 0.6509994999999918
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1336 6.14799414721 0 99.555500175 0.5344998249999918
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1337 4.78704248134 0 99.554999825 0.5350001750000019
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1338 2.47124761202 0 99.034499725 0.9832504124999915
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1339 2.47124761202 0 99.35549875 0.5017518750000036
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1340 2.50228643329 0 98.7550001 1.402499849999991
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1341 2.50228643329 0 98.317499175 2.0587512375000045
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1342 3.92040413524 0 99.476000275 0.6139997249999937
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1343 2.50228643329 0 99.396999175 0.6930008249999929
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1344 2.50228643329 0 99.280500325 0.6142495124999883
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1345 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1346 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1347 2.50228643329 0 98.8924994 1.1962508999999883
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1348 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1349 2.50228643329 0 99.37049845 0.47925232499999737
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1350 2.50228643329 0 98.7390001 1.426499849999999
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1351 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1352 6.30106886729 0 99.46000045 0.6299995500000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1353 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1354 5.02870270579 0 99.27500045 0.6224993250000068
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1355 3.92040413524 0 99.321999375 0.5520009374999901
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1356 3.85964385182 0 99.478000325 0.6119996750000013
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1357 2.50228643329 0 99.18700025 0.7544996250000011
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1358 3.38717868509 0 99.580999825 0.5090001749999914
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1359 6.30106886729 0 99.258000725 0.6479989124999932
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1360 3.85964385182 0 99.273500675 0.6247489875000056
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1361 3.85964385182 0 99.528999325 0.5610006749999968
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1362 2.01610051566 0 97.900002 2.6849969999999956
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1363 2.50228643329 0 99.386499 0.4552514999999957
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1364 2.81322619695 0 99.58850025 0.5014997500000021
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1365 3.38717868509 0 99.471000175 0.6189998249999974
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1366 6.30106886729 0 99.44 0.65
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1367 3.92040413524 0 99.54600005 0.5439999499999942
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1368 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1369 2.81322619695 0 99.331999075 0.5370013874999984
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1370 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1371 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1372 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1373 2.01610051566 0 97.620003 3.104995500000001
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1374 2.50228643329 0 98.237999725 2.1780004125000048
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1375 2.50228643329 0 99.369999825 0.48000026250000616
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1376 3.38717868509 0 99.5664995 0.5235004999999916
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1377 6.30106886729 0 99.4435005 0.6464994999999988
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1378 2.50228643329 0 98.989500525 1.0507492125000013
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1379 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1380 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1381 3.92040413524 0 99.566499725 0.5235002749999978
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1382 3.38717868509 0 99.542499525 0.5475004750000011
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1383 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1384 3.92040413524 0 99.560999575 0.529000425000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1385 6.30106886729 0 99.4365008 0.6534991999999932
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1386 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1387 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1388 6.30106886729 0 99.50550005 0.5844999500000029
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1389 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1390 2.00016617632 0 99.0 1.0349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1391 2.50228643329 0 99.185499625 0.7567505624999882
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1392 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1393 6.30106886729 0 99.257000175 0.649499737499994
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1394 5.02870270579 0 99.2665001 0.6352498499999939
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1395 3.84474688915 0 99.428999625 0.6610003749999948
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1396 2.47124761202 0 99.218499125 0.7072513125000057
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1397 6.10789096832 0 99.3400001 0.5249998500000004
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1398 2.81322619695 0 99.581499675 0.5085003249999943
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1399 6.14799414721 0 99.5084996 0.5815004000000045
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1400 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1401 2.47778695782 0 99.4290001 0.6609999000000016
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1402 2.50228643329 0 99.4385002 0.6514998000000048
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1403 2.50228643329 0 99.01299965 1.0155005250000002
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1404 1.97610564729 0 99.080002 0.9149970000000067
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1405 3.86059861244 0 99.59099995 0.4990000500000008
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1406 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1407 2.47124761202 0 99.321500075 0.5527498874999921
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1408 3.92040413524 0 99.55849965 0.5315003499999961
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1409 2.47778695782 0 99.33599825 0.5310026249999922
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1410 2.44096937877 0 99.022499775 1.0012503374999966
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1411 3.86059861244 0 99.6165006 0.4734994000000029
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1412 2.47778695782 0 99.3005006 0.5842490999999868
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1413 2.81322619695 0 99.5374991 0.5525008999999926
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1414 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1415 1.99590274244 0 99.580002 0.5099980000000045
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1416 5.02870270579 0 99.469500425 0.620499574999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1417 6.14799414721 0 99.461499925 0.6285000749999995
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1418 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1419 2.50228643329 0 99.413499975 0.6765000250000043
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1420 3.92040413524 0 99.541999425 0.5480005749999975
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1421 2.47778695782 0 99.026499675 0.9952504875000017
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1422 6.30106886729 0 99.4355002 0.6544997999999908
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1423 2.81322619695 0 99.46250045 0.6274995500000046
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1424 2.44096937877 0 99.44600045 0.6439995499999981
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1425 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1426 2.00016617632 0 99.379997 0.46500449999999205
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1427 6.14799414721 0 99.55749925 0.5325007499999913
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1428 2.47124761202 0 99.362998825 0.49050176249998856
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1429 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1430 6.14799414721 0 99.418499925 0.6715000749999916
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1431 3.34244261096 0 99.6115011 0.4784988999999996
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1432 2.47778695782 0 99.425000225 0.6649997749999926
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1433 6.30106886729 0 99.464500175 0.625499825
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1434 6.14799414721 0 99.49900035 0.5909996499999949
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1435 2.50228643329 0 99.09000035 0.8999994750000013
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1436 2.47778695782 0 98.9905002 1.0492496999999972
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1437 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1438 6.30106886729 0 99.4660008 0.6239991999999944
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1439 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1440 6.10789096832 0 99.4094999 0.6805000999999976
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1441 3.92040413524 0 99.3284995 0.5422507499999867
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1442 6.30106886729 0 99.515500125 0.5744998749999951
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1443 2.78229733114 0 99.6075006 0.48249940000000324
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1444 2.47124761202 0 99.386499275 0.4552510874999882
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1445 4.93072604433 0 99.42349955 0.6665004499999952
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1446 3.38717868509 0 99.3259999 0.5460001499999976
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1447 3.38717868509 0 99.570499925 0.5195000750000048
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1448 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1449 6.10789096832 0 99.58400005 0.5059999499999975
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1450 3.80166404425 0 99.525999425 0.5640005750000029
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1451 3.7862916372 0 99.4165003 0.6734997000000021
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1452 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1453 6.30106886729 0 99.502499825 0.5875001749999967
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1454 2.47778695782 0 99.323499175 0.5497512375000042
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1455 2.47778695782 0 99.047999525 0.9630007125000049
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1456 6.30106886729 0 99.425499675 0.6645003250000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1457 2.50228643329 0 98.892999075 1.1955013874999878
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1458 2.44096937877 0 99.398499325 0.6915006749999947
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1459 2.81322619695 0 99.590000925 0.4999990749999995
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1460 3.33055390722 0 99.73649975 0.35350025000000473
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1461 2.47778695782 0 99.26500055 0.6374991750000021
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1462 6.14799414721 0 99.4905 0.5995000000000005
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1463 3.92040413524 0 99.54349955 0.5465004499999907
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1464 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1465 2.50228643329 0 99.377499075 0.46875138749999223
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1466 2.00016617632 0 99.0 1.0349999999999966
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1467 2.00016617632 0 98.580002 1.6649970000000067
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1468 2.47124761202 0 99.267000075 0.6344998874999987
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1469 2.50228643329 0 99.283000625 0.6104990624999971
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1470 2.47778695782 0 99.420999375 0.6690006250000039
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1471 2.50228643329 0 99.3724994 0.4762509000000037
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1472 6.14799414721 0 99.413499925 0.6765000750000013
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1473 1.99590274244 0 98.139999 2.325001499999992
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1474 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1475 6.30106886729 0 99.445500575 0.6444994250000008
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1476 6.10789096832 0 99.399999175 0.6900008249999928
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1477 2.50228643329 0 98.23200065 2.1869990249999915
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1478 3.34244261096 0 99.574999975 0.5150000250000005
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1479 2.47124761202 0 99.022999675 1.0005004875000054
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1480 2.78229733114 0 99.5164984 0.5735015999999945
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1481 2.77405457184 0 99.577998975 0.5120010249999979
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1482 5.02870270579 0 99.273000325 0.6254995124999994
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1483 6.30106886729 0 99.44949995 0.6405000499999943
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1484 2.50228643329 0 98.908000625 1.172999062499997
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1485 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1486 2.81322619695 0 99.587999675 0.5020003249999917
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1487 2.00016617632 0 99.660004 0.42999599999999705
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1488 3.85964385182 0 99.2625002 0.6412496999999888
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1489 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1490 2.81322619695 0 99.331499075 0.537751387500002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1491 3.86059861244 0 99.5910002 0.49899980000000144
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1492 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1493 2.47778695782 0 98.999500075 1.0357498874999962
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1494 3.34244261096 0 99.616000475 0.47399952499999076
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1495 3.85964385182 0 99.484999975 0.6050000250000039
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1496 3.92040413524 0 99.5539999 0.536000100000004
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1497 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1498 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1499 2.47778695782 0 99.0249994 0.9975008999999986
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1500 4.90489779833 0 99.41399985 0.6760001500000016
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1501 2.78229733114 0 99.554999075 0.535000925
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1502 5.92620561097 0 99.5504994 0.539500599999991
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1503 1.99590274244 0 99.260002 0.6449969999999965
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1504 2.47124761202 0 99.310500825 0.5692487624999885
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1505 2.81322619695 0 99.538999575 0.5510004249999924
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1506 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1507 6.30106886729 0 99.467000075 0.6229999249999963
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1508 2.47778695782 0 99.39350025 0.6964997499999953
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1509 6.10789096832 0 99.579499625 0.5105003750000009
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1510 4.93072604433 0 99.5169999 0.5730000999999959
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1511 2.50228643329 0 99.3804993 0.46425105000000144
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1512 5.02870270579 0 99.475000625 0.6149993749999908
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1513 2.47778695782 0 98.93350015 1.134749774999996
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1514 6.14799414721 0 99.503000075 0.586999924999995
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1515 5.02870270579 0 99.458999975 0.6310000250000002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1516 2.50228643329 0 99.0304991 0.9892513499999964
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1517 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1518 3.92040413524 0 99.554498975 0.5355010249999964
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1519 3.92040413524 0 99.566999875 0.5230001250000044
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1520 6.30106886729 0 99.474499975 0.6155000249999972
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1521 3.92040413524 0 99.3329993 0.5355010500000006
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1522 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1523 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1524 6.30106886729 0 99.502499275 0.5875007249999925
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1525 6.30106886729 0 99.4525002 0.6374997999999948
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1526 2.50228643329 0 98.3025 2.0812500000000043
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1527 6.30106886729 0 99.253999525 0.6540007125000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1528 2.01610051566 0 97.900002 2.6849969999999956
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1529 2.50228643329 0 99.3794995 0.4657507500000051
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1530 2.81322619695 0 99.3324994 0.5362508999999918
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1531 6.30106886729 0 99.4319996 0.6580004000000003
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1532 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1533 2.50228643329 0 99.4100001 0.6799998999999929
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1534 2.01610051566 0 97.879997 2.715004499999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1535 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1536 5.02870270579 0 99.476500375 0.6134996249999972
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1537 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1538 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1539 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1540 2.81322619695 0 99.5905005 0.4994994999999932
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1541 2.50228643329 0 99.394999125 0.6950008749999995
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1542 2.50228643329 0 97.880498675 2.714251987499999
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1543 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1544 2.50228643329 0 99.3764997 0.47025045000000176
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1545 2.50228643329 0 99.371499825 0.4777502624999954
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1546 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1547 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1548 3.85964385182 0 99.26600075 0.6359988749999914
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1549 2.50228643329 0 97.659501225 3.045748162499997
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1550 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1551 2.50228643329 0 98.23250025 2.186249624999995
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1552 2.50228643329 0 99.00199985 1.0320002249999902
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1553 2.50228643329 0 99.37399865 0.4740020249999901
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1554 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1555 2.50228643329 0 99.102000425 0.8819993624999967
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1556 3.85964385182 0 99.4645003 0.6254997000000003
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1557 2.50228643329 0 99.281000925 0.6134986124999955
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1558 6.30106886729 0 99.4530003 0.6369996999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1559 2.50228643329 0 99.187000725 0.7544989124999901
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1560 2.50228643329 0 98.898499075 1.187251387499991
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1561 2.50228643329 0 98.736500275 1.4302495875000005
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1562 3.38717868509 0 99.573999575 0.5160004249999958
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1563 5.02870270579 0 99.513499725 0.5765002749999951
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1564 2.47778695782 0 98.9680005 1.0829992499999932
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1565 3.33055390722 0 99.737999875 0.3520001249999979
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1566 2.47778695782 0 99.034999825 0.9825002624999968
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1567 2.50228643329 0 99.42649985 0.6635001499999987
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1568 2.78229733114 0 99.512998925 0.5770010749999926
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1569 2.78229733114 0 99.57799995 0.5120000499999918
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1570 4.78704248134 0 99.5660001 0.5239999000000012
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1571 3.85964385182 0 99.475500875 0.6144991250000033
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1572 2.50228643329 0 99.3974997 0.6925003000000004
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1573 6.10789096832 0 99.57150015 0.5184998499999921
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1574 2.81322619695 0 99.542499525 0.5475004750000011
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1575 2.50228643329 0 99.44250095 0.6474990500000019
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1576 6.14799414721 0 99.460000325 0.629999675000002
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1577 2.50228643329 0 99.00200005 1.0319999249999867
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1578 2.47778695782 0 99.050499675 0.9592504875000003
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1579 3.92040413524 0 99.55249935 0.5375006499999927
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1580 6.30106886729 0 99.454000825 0.6359991750000035
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1581 3.92040413524 0 99.5760004 0.5139995999999997
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1582 2.00016617632 0 99.199997 0.7350045000000023
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1583 6.14799414721 0 99.54849945 0.5415005500000035
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1584 2.47124761202 0 99.2154998 0.7117502999999914
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1585 2.81322619695 0 99.57649945 0.5135005499999977
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1586 2.73595882486 0 99.639001225 0.4509987749999965
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1587 2.47778695782 0 99.4405004 0.649499599999993
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1588 2.47124761202 0 99.503500175 0.5864998249999985
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1589 3.80166404425 0 99.47900055 0.6109994500000028
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1590 2.50228643329 0 99.404499675 0.685500325000001
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1591 2.47124761202 0 99.3180001 0.5579998499999874
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1592 3.71567552873 0 99.5499996 0.540000399999991
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1593 2.47124761202 0 99.273500675 0.6247489875000056
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1594 2.50228643329 0 99.026499175 0.9952512374999998
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1595 3.85964385182 0 99.467500875 0.6224991249999988
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1596 3.38717868509 0 99.567999575 0.522000424999996
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1597 3.34244261096 0 99.6130008 0.47699920000000307
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1598 3.80166404425 0 99.52149975 0.5685002499999939
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1599 6.10789096832 0 99.331499675 0.5377504874999914
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1600 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1601 5.02870270579 0 99.5239992 0.566000799999992
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1602 3.77195447337 0 99.628501325 0.46149867499999575
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1603 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1604 3.80166404425 0 99.5234991 0.5665009000000026
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1605 6.14799414721 0 99.500499575 0.5895004249999914
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1606 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1607 2.47124761202 0 99.386499275 0.4552510874999882
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1608 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1609 1.99590274244 0 99.599998 0.4900019999999984
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1610 2.50228643329 0 99.00950015 1.0207497750000059
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1611 2.47778695782 0 99.40549985 0.6845001499999995
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1612 3.85964385182 0 99.473500825 0.6164991749999956
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1613 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1614 3.86059861244 0 99.506499875 0.5835001249999948
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1615 2.47778695782 0 99.397499725 0.6925002749999948
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1616 5.92620561097 0 99.544999775 0.545000225000004
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1617 6.30106886729 0 99.473999525 0.6160004750000013
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1618 3.86059861244 0 99.5965 0.4934999999999917
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1619 6.14799414721 0 99.5010002 0.5889998000000048
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1620 5.02870270579 0 99.4765004 0.6134995999999916
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1621 3.38717868509 0 99.541999425 0.5480005749999975
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1622 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1623 2.78229733114 0 99.615500325 0.47449967499999846
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1624 6.30106886729 0 99.502500325 0.587499674999998
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1625 6.30106886729 0 99.43000005 0.6599999499999939
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1626 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1627 6.30106886729 0 99.26200065 0.6419990249999898
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1628 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1629 4.90489779833 0 99.586500025 0.5034999749999912
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1630 4.93072604433 0 99.510999575 0.5790004249999982
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1631 2.78229733114 0 99.614000375 0.4759996249999944
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1632 3.84474688915 0 99.43100005 0.6589999500000033
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1633 2.47778695782 0 99.2955008 0.5917487999999977
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1634 2.50228643329 0 99.184499825 0.7582502624999918
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1635 2.47778695782 0 99.329499525 0.5407507124999924
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1636 4.93072604433 0 99.52249995 0.567500050000001
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1637 3.33055390722 0 99.576000025 0.5139999749999987
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1638 3.38717868509 0 99.583000075 0.5069999249999967
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1639 3.34244261096 0 99.50749975 0.5825002500000039
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1640 3.92040413524 0 99.558499675 0.5315003250000047
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1641 3.86059861244 0 99.595000075 0.49499992499999623
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1642 2.47778695782 0 99.437500275 0.6524997249999928
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1643 2.50228643329 0 99.373499575 0.47475063750000146
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1644 1.99590274244 0 98.599998 1.6350029999999975
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1645 6.14799414721 0 99.50299975 0.587000249999997
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1646 2.47124761202 0 99.1220011 0.8519983499999881
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1647 2.81322619695 0 99.470500925 0.6194990750000017
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1648 2.47124761202 0 98.3239998 2.049000300000003
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1649 2.00016617632 0 98.980003 1.064995500000002
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1650 2.47778695782 0 99.41799995 0.6720000500000026
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1651 3.71567552873 0 99.553999325 0.5360006749999912
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1652 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1653 2.77405457184 0 99.738499275 0.3515007250000025
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1654 5.02870270579 0 99.255999975 0.6510000375000047
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1655 2.50228643329 0 98.902999675 1.180500487499991
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1656 6.30106886729 0 99.258499925 0.6472501125000036
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1657 3.27579123647 0 99.64500205 0.44499794999999553
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1658 2.47778695782 0 98.93350115 1.1347482749999998
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1659 2.81322619695 0 99.333498825 0.5347517624999867
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1660 6.30106886729 0 99.460500425 0.6294995749999913
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1661 2.50228643329 0 99.365498975 0.4867515375000053
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1662 5.02870270579 0 99.467001175 0.6229988250000048
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1663 3.85964385182 0 99.47449985 0.6155001499999969
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1664 3.92040413524 0 99.479499575 0.6105004249999922
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1665 4.78704248134 0 99.5624994 0.5275006000000048
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1666 3.85964385182 0 99.468500375 0.6214996249999928
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1667 6.30106886729 0 99.4335002 0.6564998000000003
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1668 3.80166404425 0 99.41949975 0.6705002499999978
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1669 2.81322619695 0 99.573000475 0.5169995249999971
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1670 2.47778695782 0 99.38749925 0.4537511249999895
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1671 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1672 3.85964385182 0 99.27349995 0.6247500749999944
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1673 2.50228643329 0 99.28100055 0.6134991749999941
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1674 6.14799414721 0 99.507500275 0.5824997249999996
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1675 6.10789096832 0 99.420499775 0.6695002250000016
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1676 4.90489779833 0 99.34499945 0.517500824999992
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1677 6.10789096832 0 99.3319992 0.5370011999999988
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1678 3.38717868509 0 99.46999995 0.6200000499999959
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1679 2.47124761202 0 98.53199905 1.7370014250000025
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1680 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1681 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1682 2.78229733114 0 99.615001075 0.47499892500000274
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1683 2.47778695782 0 99.47850095 0.6114990500000005
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1684 6.30106886729 0 99.50049995 0.5895000499999924
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1685 2.50228643329 0 99.469001675 0.6209983249999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1686 2.00016617632 0 99.620003 0.4699970000000008
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1687 1.99590274244 0 98.440002 1.8749969999999863
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1688 6.14799414721 0 99.46750035 0.6224996500000032
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1689 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1690 4.93072604433 0 99.4275003 0.6624996999999923
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1691 6.14799414721 0 99.422500325 0.6674996749999963
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1692 3.80166404425 0 99.48150015 0.6084998499999955
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1693 6.30106886729 0 99.465000225 0.6249997750000006
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1694 2.78229733114 0 99.554499175 0.5355008249999941
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1695 2.81322619695 0 99.594500125 0.4954998750000016
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1696 2.50228643329 0 99.28250105 0.6112484250000065
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1697 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1698 3.38717868509 0 99.541999225 0.5480007749999999
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1699 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1700 6.30106886729 0 99.451500025 0.6384999749999963
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1701 3.7862916372 0 99.32999935 0.5400009750000052
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1702 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1703 2.47124761202 0 99.1944995 0.7432507499999872
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1704 2.00016617632 0 98.580002 1.6649970000000067
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1705 2.47124761202 0 98.273000575 2.1254991375000003
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1706 3.80166404425 0 99.573999925 0.5160000750000023
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1707 2.47124761202 0 98.8214997 1.3027504499999907
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1708 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1709 3.38717868509 0 99.33449965 0.5332505249999997
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1710 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1711 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1712 2.50228643329 0 98.914500175 1.1632497374999957
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1713 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1714 6.30106886729 0 99.4310002 0.658999799999998
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1715 2.01610051566 0 98.459999 1.8450015000000022
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1716 2.50228643329 0 99.474000575 0.6159994249999926
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1717 3.92040413524 0 99.478000175 0.6119998249999924
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1718 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1719 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1720 5.02870270579 0 99.51599985 0.5740001499999977
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1721 6.30106886729 0 99.4455001 0.6444998999999939
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1722 2.50228643329 0 99.367498375 0.4837524375000015
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1723 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1724 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1725 2.50228643329 0 99.029999175 0.990001237499996
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1726 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1727 2.81322619695 0 99.4665007 0.6234993000000003
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1728 5.02870270579 0 99.4305001 0.6594998999999945
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1729 2.50228643329 0 99.09350035 0.8947494749999976
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1730 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1731 6.30106886729 0 99.2665001 0.6352498499999939
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1732 2.50228643329 0 98.74949935 1.4107509750000062
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1733 6.30106886729 0 99.467000275 0.622999724999994
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1734 3.38717868509 0 99.47200055 0.6179994499999936
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1735 2.50228643329 0 98.994999875 1.0425001874999893
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1736 2.50228643329 0 98.335499625 2.031750562500001
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1737 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1738 2.50228643329 0 99.402999975 0.6870000249999976
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1739 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1740 3.85964385182 0 99.43049945 0.6595005499999985
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1741 6.30106886729 0 99.4500003 0.6399996999999985
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1742 2.01610051566 0 99.040001 0.974998499999991
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1743 3.92040413524 0 99.53550005 0.5544999500000017
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1744 6.30106886729 0 99.503999575 0.5860004250000032
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf1745 3.38717868509 0 99.5845001 0.5054998999999981
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_promise_confs_batch220_single.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_promise_confs_batch220_single.txt
deleted file mode 100644
index ba559f05472091a191117ec9d1e952d2522be7aa..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/autotuner_data/tuner_promise_confs_batch220_single.txt
+++ /dev/null
@@ -1,5888 +0,0 @@
-+++++
-conf1 1 0 99.69 0
-1 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-2 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-3 gpu mul fp32 1 add fp32 1 tanh fp32 1
-4 gpu mul fp32 1 add fp32 1 tanh fp32 1
-5 gpu softmax fp32 1
------
-+++++
-conf1 2.47778695782 0 99.4405011 0.6494988999999919
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf2 6.7963162944 0 99.247499625 0.6637505624999918
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf3 3.77195447337 0 99.475500875 0.6144991250000033
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf4 3.71656038268 0 99.55999965 0.5300003500000031
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf5 4.4071692756 0 99.52149975 0.5685002499999939
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf6 6.14799414721 0 99.5005001 0.5894999000000013
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf7 2.57685599488 0 99.380999175 0.4635012374999974
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf8 3.13161472572 0 99.57700015 0.5129998499999943
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf9 2.00016617632 0 99.68 0.4099999999999909
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf10 2.57685599488 0 99.097999925 0.8880001125000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf11 3.38717868509 0 99.550999225 0.5390007749999995
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf12 3.84474688915 0 99.72650005 0.36349994999999924
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf13 4.48527898013 0 99.467000825 0.6229991749999982
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf14 3.70186719231 0 99.72250035 0.3674996499999935
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf15 2.47778695782 0 98.99100065 1.048499024999991
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf16 4.62093815126 0 99.3364993 0.5302510499999968
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf17 3.09333654389 0 99.6080005 0.4819994999999949
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf18 2.55088214386 0 99.00499975 1.0275003750000025
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf19 3.97649090032 0 99.429000025 0.6609999750000043
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf20 5.92620561097 0 99.556000075 0.5339999249999977
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf21 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf22 5.22888975029 0 99.508999675 0.5810003249999994
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf23 3.13161472572 0 99.4715006 0.6184993999999989
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf24 5.98028404553 0 99.533499775 0.5565002250000021
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf25 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf26 3.84474688915 0 99.566499875 0.5235001249999925
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf27 6.7963162944 0 99.44900035 0.640999649999992
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf28 3.09333654389 0 99.5589995 0.531000499999999
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf29 3.77195447337 0 99.5525002 0.5374998000000005
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf30 5.33920664205 0 99.434000525 0.6559994749999959
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf31 6.61857279171 0 99.493500625 0.5964993750000019
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf32 2.55088214386 0 99.48100075 0.6089992499999909
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf33 6.14799414721 0 99.46299985 0.627000149999995
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf34 2.47778695782 0 99.255999775 0.6510003374999869
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf35 2.55088214386 0 99.405999975 0.6840000249999975
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf36 3.38717868509 0 99.47850045 0.6114995499999992
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf37 4.93072604433 0 99.52249925 0.5675007500000021
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf38 4.48527898013 0 99.4800001 0.6099998999999997
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf39 2.57685599488 0 99.172500625 0.7762490624999998
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf40 4.73066277039 0 99.453000075 0.6369999249999921
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf41 2.55088214386 0 99.25799985 0.6480002249999899
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf42 6.10789096832 0 99.576499825 0.5135001749999987
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf43 3.85964385182 0 99.4670006 0.622999399999992
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf44 2.44096937877 0 99.3809992 0.46350119999998896
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf45 2.57685599488 0 99.419500025 0.6704999749999928
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf46 1.99590274244 0 99.459999 0.6300010000000015
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf47 2.47778695782 0 99.38649995 0.45525007499999504
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf48 2.5439518228 0 99.1235002 0.8497497000000038
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf49 3.71656038268 0 99.572999425 0.5170005749999916
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf50 2.47778695782 0 99.4265002 0.6634997999999911
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf51 4.38652335485 0 99.335499625 0.531750562500001
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf52 2.47778695782 0 99.419999975 0.6700000250000017
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf53 2.50228643329 0 99.034499525 0.983250712499995
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf54 3.97649090032 0 99.570999775 0.5190002249999935
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf55 5.33920664205 0 99.457999875 0.632000124999999
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf56 3.95967525105 0 99.33649965 0.5302505250000067
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf57 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf58 2.47778695782 0 99.3020012 0.5819981999999868
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf59 5.92620561097 0 99.4655009 0.6244991000000027
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf60 4.64385542353 0 99.468000075 0.6219999249999916
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf61 2.57685599488 0 99.355498525 0.5017522124999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf62 4.73066277039 0 99.4225003 0.6674997000000019
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf63 1.99590274244 0 99.639999 0.45000099999999466
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf64 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf65 3.38717868509 0 99.333499175 0.5347512374999965
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf66 5.92620561097 0 99.476000125 0.613999874999999
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf67 2.81322619695 0 99.580499825 0.5095001749999938
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf68 2.78229733114 0 99.52199845 0.5680015499999996
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf69 3.34244261096 0 99.6135014 0.47649859999999367
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf70 3.97649090032 0 99.51250005 0.5774999499999979
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf71 6.61857279171 0 99.5040001 0.5859998999999988
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf72 6.61857279171 0 99.420500525 0.6694994750000035
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf73 6.61857279171 0 99.504999975 0.5850000249999937
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf74 3.63433700317 0 99.652501475 0.43749852500000375
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf75 6.10789096832 0 99.3409999 0.5235001499999967
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf76 4.4071692756 0 99.478000575 0.6119994250000019
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf77 2.50228643329 0 99.40099985 0.6890001499999926
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf78 3.77195447337 0 99.3255004 0.546749400000003
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf79 3.80166404425 0 99.565500025 0.524499974999992
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf80 6.57211871555 0 99.333000125 0.5354998124999995
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf81 2.50228643329 0 99.47350135 0.6164986499999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf82 5.79060658268 0 99.519000125 0.5709998749999926
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf83 2.50228643329 0 99.381999275 0.46200108749999913
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf84 2.47778695782 0 99.1835005 0.7597492500000058
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf85 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf86 2.55088214386 0 99.39199985 0.6980001499999929
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf87 3.85964385182 0 99.4795001 0.6104999000000021
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf88 4.38652335485 0 99.41799955 0.6720004499999931
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf89 4.93072604433 0 99.51499965 0.5750003500000048
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf90 3.13161472572 0 99.574500425 0.5154995750000012
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf91 3.09333654389 0 99.6145003 0.47549969999999464
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf92 3.92040413524 0 99.578000175 0.5119998249999981
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf93 5.33920664205 0 99.44499995 0.6450000500000016
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf94 2.47778695782 0 99.45300095 0.6369990499999943
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf95 2.50228643329 0 99.36299905 0.49050142499999794
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf96 5.02870270579 0 99.458500175 0.6314998250000002
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf97 5.75501684906 0 99.346999025 0.5145014624999931
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf98 2.57685599488 0 99.436500375 0.6534996250000035
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf99 3.33055390722 0 99.4209998 0.6690001999999936
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf100 5.59344058403 0 99.55649965 0.5335003499999914
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf101 5.79060658268 0 99.556999575 0.5330004249999917
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf102 3.7862916372 0 99.3334994 0.5347509000000059
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf103 6.30106886729 0 99.5175 0.5724999999999995
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf104 5.06758777035 0 99.552499325 0.5375006749999983
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf105 6.14799414721 0 99.499999525 0.5900004749999909
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf106 2.51187737029 0 99.4014999 0.6885000999999932
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf107 2.55088214386 0 99.39649945 0.6935005500000045
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf108 2.47124761202 0 99.1929994 0.745500899999989
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf109 4.03997047176 0 99.52149955 0.5685004499999963
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf110 3.70186719231 0 99.42099935 0.6690006499999953
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf111 2.47778695782 0 99.404999575 0.6850004249999927
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf112 3.97649090032 0 99.4600001 0.6299998999999957
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf113 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf114 3.86059861244 0 99.50650005 0.5834999499999981
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf115 2.57685599488 0 99.460000575 0.6299994250000026
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf116 5.33920664205 0 99.2685007 0.6322489499999904
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf117 5.02870270579 0 99.468000425 0.6219995749999981
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf118 4.4071692756 0 99.56599955 0.524000449999997
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf119 5.02870270579 0 99.4325 0.6574999999999932
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf120 6.61857279171 0 99.457500525 0.6324994749999974
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf121 2.00016617632 0 99.080002 0.9149970000000067
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf122 2.50228643329 0 99.4199998 0.6700001999999984
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf123 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf124 6.16535217595 0 99.58050025 0.5094997499999977
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf125 6.30106886729 0 99.45700045 0.6329995500000024
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf126 2.57685599488 0 99.407999525 0.6820004750000038
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf127 3.77195447337 0 99.6320011 0.4579989000000012
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf128 6.57211871555 0 99.3999996 0.6900003999999967
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf129 6.36224047437 0 99.264500075 0.6382498874999953
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf130 4.48527898013 0 99.52299915 0.5670008499999938
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf131 5.79060658268 0 99.416500475 0.6734995249999912
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf132 2.5439518228 0 99.32149995 0.5527500749999916
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf133 2.55088214386 0 99.4905002 0.5994997999999981
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf134 3.95967525105 0 99.4149999 0.6750000999999998
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf135 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf136 3.80166404425 0 99.421499725 0.6685002749999939
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf137 3.7862916372 0 99.419999575 0.6700004249999921
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf138 3.77195447337 0 99.570499675 0.5195003250000042
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf139 3.86059861244 0 99.6145001 0.475499899999997
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf140 2.78229733114 0 99.609500425 0.4804995750000046
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf141 5.02870270579 0 99.446999675 0.643000324999997
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf142 3.77195447337 0 99.540499625 0.5495003750000024
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf143 4.90489779833 0 99.588500425 0.5014995749999912
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf144 5.75501684906 0 99.570999975 0.5190000249999912
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf145 2.5439518228 0 99.37649915 0.4702512749999954
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf146 6.16535217595 0 99.336499425 0.5302508624999973
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf147 5.33920664205 0 99.46600045 0.6239995500000021
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf148 2.47124761202 0 99.125500425 0.8467493624999989
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf149 4.03997047176 0 99.44900065 0.6409993499999956
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf150 4.48527898013 0 99.268500375 0.6322494374999934
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf151 3.08315119118 0 99.7369988 0.3530012000000028
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf152 2.55088214386 0 99.406000225 0.6839997749999981
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf153 6.36224047437 0 99.46550055 0.6244994499999962
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf154 4.73066277039 0 99.46849975 0.6215002499999912
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf155 3.38717868509 0 99.5730001 0.5169998999999962
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf156 6.10789096832 0 99.4119995 0.6780005000000046
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf157 3.08315119118 0 99.426000325 0.6639996749999938
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf158 4.93072604433 0 99.431000325 0.6589996749999983
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf159 5.79060658268 0 99.47600065 0.6139993499999946
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf160 6.36224047437 0 99.54099985 0.549000149999992
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf161 2.50228643329 0 99.3779992 0.4680011999999891
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf162 6.7963162944 0 99.4620004 0.627999600000004
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf163 2.57685599488 0 99.37699935 0.46950097499998833
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf164 6.20621598565 0 99.471000525 0.618999475000004
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf165 6.30106886729 0 99.439 0.6510000000000048
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf166 6.36224047437 0 99.440499925 0.6495000750000003
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf167 4.29202279061 0 99.5565002 0.5334997999999956
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf168 2.57685599488 0 98.9975002 1.0387496999999897
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf169 3.85964385182 0 99.483499875 0.606500124999991
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf170 2.50228643329 0 99.2815005 0.612749249999986
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf171 6.36224047437 0 99.457000375 0.6329996249999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf172 6.20621598565 0 99.55249975 0.5375002500000022
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf173 3.33055390722 0 99.583999875 0.5060001249999942
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf174 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf175 5.75501684906 0 99.41749995 0.6725000499999908
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf176 6.20621598565 0 99.503500175 0.5864998249999985
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf177 3.85964385182 0 99.4360005 0.653999499999992
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf178 2.47778695782 0 99.3329996 0.535500600000006
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf179 2.55088214386 0 99.409999625 0.6800003750000002
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf180 2.57685599488 0 99.010999225 1.0185011624999873
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf181 4.64385542353 0 99.567499925 0.5225000749999907
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf182 2.47778695782 0 99.4029989 0.6870010999999977
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf183 3.38717868509 0 99.57399985 0.5160001499999908
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf184 2.77405457184 0 99.4234996 0.6665003999999982
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf185 2.50228643329 0 99.379499125 0.4657513125000037
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf186 6.14799414721 0 99.4990005 0.5909995000000038
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf187 6.7963162944 0 99.43399975 0.6560002499999996
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf188 5.33920664205 0 99.51449955 0.5755004500000013
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf189 6.30106886729 0 99.266500125 0.6352498125000068
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf190 4.93072604433 0 99.56199985 0.5280001499999912
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf191 4.73066277039 0 99.51799975 0.5720002499999964
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf192 2.57685599488 0 99.285000425 0.6074993624999863
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf193 2.5439518228 0 99.1979999 0.7380001499999977
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf194 5.92620561097 0 99.44250075 0.6474992500000042
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf195 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf196 2.47778695782 0 99.0264997 0.9952504499999932
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf197 4.48527898013 0 99.449500675 0.6404993250000018
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf198 4.64385542353 0 99.5164996 0.5735003999999947
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf199 5.19985255986 0 99.3364995 0.5302507499999933
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf200 3.34244261096 0 99.608000925 0.48199907499999883
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf201 4.73066277039 0 99.265000525 0.6374992124999892
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf202 3.97649090032 0 99.51849965 0.5715003500000023
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf203 3.97649090032 0 99.52049955 0.569500450000001
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf204 5.22888975029 0 99.508000225 0.5819997749999942
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf205 4.90489779833 0 99.42149985 0.6685001499999942
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf206 2.5439518228 0 99.492999825 0.5970001749999995
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf207 4.03997047176 0 99.46600075 0.6239992499999915
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf208 2.81322619695 0 99.589000375 0.5009996250000001
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf209 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf210 5.22888975029 0 99.5105 0.5795000000000045
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf211 2.55088214386 0 99.42599955 0.6640004499999975
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf212 2.81322619695 0 99.542999675 0.5470003249999934
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf213 2.47778695782 0 99.05800035 0.947999474999996
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf214 2.55088214386 0 99.39599955 0.6940004499999987
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf215 4.93072604433 0 99.472500675 0.6174993249999915
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf216 5.02870270579 0 99.270500225 0.629249662499987
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf217 3.86059861244 0 99.590000025 0.4999999750000029
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf218 3.88250959671 0 99.55349975 0.5365002499999975
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf219 2.50228643329 0 99.365499425 0.48675086250000277
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf220 2.55088214386 0 98.99799995 1.0380000750000065
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf221 3.80166404425 0 99.53449915 0.5555008499999957
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf222 2.00016617632 0 99.239998 0.6750029999999967
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf223 2.00016617632 0 99.519997 0.5700029999999942
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf224 2.51187737029 0 99.024499825 0.9982502624999867
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf225 3.86059861244 0 99.57049935 0.519500649999992
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf226 2.47778695782 0 99.4985004 0.5914996000000002
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf227 3.71656038268 0 99.508999525 0.5810004750000047
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf228 3.71656038268 0 99.607000725 0.48299927499999173
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf229 2.47778695782 0 99.324499325 0.5482510124999891
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf230 6.14799414721 0 99.5609996 0.5290003999999954
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf231 3.77195447337 0 99.5870001 0.5029999000000004
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf232 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf233 3.92040413524 0 99.545499775 0.5445002250000016
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf234 3.92040413524 0 99.57699935 0.5130006500000036
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf235 2.55088214386 0 98.987999875 1.0530001874999968
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf236 2.57685599488 0 99.363999075 0.48900138750000366
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf237 4.48527898013 0 99.4369996 0.6530004000000048
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf238 5.79060658268 0 99.5149995 0.5750004999999959
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf239 2.81322619695 0 99.463000675 0.6269993249999942
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf240 4.64385542353 0 99.523000025 0.566999974999996
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf241 2.81322619695 0 99.33849865 0.5272520249999886
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf242 3.95967525105 0 99.6014996 0.48850040000000094
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf243 6.36224047437 0 99.4400002 0.6499997999999977
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf244 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf245 2.78229733114 0 99.57849985 0.5115001499999977
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf246 3.92040413524 0 99.554999725 0.5350002749999959
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf247 2.50228643329 0 98.990500375 1.049249437500002
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf248 2.57685599488 0 99.272500225 0.626249662499994
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf249 2.00016617632 0 99.339996 0.5250059999999976
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf250 2.57685599488 0 99.4725001 0.6174998999999929
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf251 2.55088214386 0 99.3259999 0.5460001499999976
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf252 2.73595882486 0 99.64500115 0.44499884999999895
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf253 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf254 6.14799414721 0 99.418500325 0.6714996750000012
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf255 3.92040413524 0 99.3274997 0.5437504499999903
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf256 5.92620561097 0 99.256500075 0.6502498874999887
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf257 2.47778695782 0 99.4835009 0.6064991000000021
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf258 2.57685599488 0 99.441500975 0.648499025000001
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf259 3.86059861244 0 99.615001125 0.4749988749999915
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf260 2.57685599488 0 99.02799945 0.9930008250000029
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf261 3.85964385182 0 99.522499925 0.5675000749999924
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf262 6.61857279171 0 99.545499925 0.5445000749999963
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf263 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf264 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf265 4.90489779833 0 99.343498975 0.5197515374999924
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf266 2.55088214386 0 99.449500125 0.6404998749999976
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf267 3.38717868509 0 99.56699955 0.5230004499999922
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf268 6.16535217595 0 99.40699995 0.6830000499999983
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf269 3.13161472572 0 99.577999975 0.5120000250000004
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf270 5.02870270579 0 99.5194997 0.5705003000000005
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf271 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf272 4.03997047176 0 99.270000125 0.629999812500003
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf273 2.50228643329 0 99.436000225 0.653999774999997
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf274 6.30106886729 0 99.4565001 0.6334998999999982
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf275 4.64385542353 0 99.520499675 0.5695003250000014
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf276 6.20621598565 0 99.51049995 0.5795000500000015
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf277 5.22888975029 0 99.561499175 0.5285008250000033
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf278 2.50228643329 0 99.100999975 0.8835000375000064
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf279 6.20621598565 0 99.50749955 0.5825004499999921
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf280 2.50228643329 0 99.408499875 0.6815001249999938
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf281 2.44096937877 0 99.442000325 0.6479996750000027
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf282 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf283 4.78704248134 0 99.559999825 0.5300001749999922
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf284 6.7963162944 0 99.50250015 0.5874998499999947
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf285 4.93072604433 0 99.514499925 0.5755000750000022
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf286 2.50228643329 0 99.4350005 0.6549994999999967
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf287 4.51618813067 0 99.55749945 0.5325005500000032
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf288 5.22888975029 0 99.41699995 0.6730000499999932
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf289 4.4071692756 0 99.51849985 0.57150015
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf290 2.5439518228 0 99.19599945 0.7410008249999933
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf291 3.85964385182 0 99.27150005 0.6277499249999963
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf292 3.86059861244 0 99.5890004 0.5009995999999944
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf293 2.57685599488 0 99.377499425 0.4687508625000021
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf294 3.71656038268 0 99.59550035 0.49449965000000307
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf295 2.57685599488 0 99.360999575 0.4935006375000057
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf296 5.19985255986 0 99.40499985 0.6850001500000019
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf297 4.03997047176 0 99.44049995 0.6495000499999947
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf298 2.5439518228 0 99.282001325 0.6119980125000026
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf299 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf300 2.47778695782 0 98.968000625 1.0829990624999937
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf301 3.71656038268 0 99.624000875 0.46599912500000473
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf302 3.70186719231 0 99.567000175 0.5229998249999938
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf303 5.79060658268 0 99.507000675 0.5829993249999973
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf304 4.03997047176 0 99.4725003 0.6174997000000048
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf305 6.20621598565 0 99.42449955 0.6655004500000047
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf306 2.55088214386 0 99.171000825 0.778498762500007
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf307 3.71567552873 0 99.566999925 0.5230000749999931
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf308 2.00016617632 0 99.599998 0.4900019999999984
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf309 2.51187737029 0 99.449501 0.6404989999999998
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf310 2.47778695782 0 99.409999625 0.6800003750000002
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf311 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf312 3.92040413524 0 99.4805003 0.609499699999995
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf313 3.7862916372 0 99.593500375 0.4964996249999928
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf314 2.5439518228 0 99.2214994 0.7027508999999981
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf315 2.47778695782 0 98.999999825 1.0350002624999917
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf316 2.00016617632 0 99.360001 0.49499850000000123
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf317 3.13161472572 0 99.53799935 0.5520006499999909
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf318 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf319 2.5439518228 0 99.353998375 0.5040024374999916
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf320 2.00016617632 0 99.019997 1.0050044999999912
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf321 5.92620561097 0 99.510499825 0.5795001750000012
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf322 6.7963162944 0 99.430000375 0.6599996249999919
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf323 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf324 2.50228643329 0 99.288500125 0.6022498124999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf325 3.13161472572 0 99.335998525 0.531002212500006
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf326 6.36224047437 0 99.513500075 0.5764999250000017
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf327 2.55088214386 0 99.386498775 0.4552518374999863
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf328 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf329 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf330 6.57211871555 0 99.56999995 0.5200000500000016
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf331 5.92620561097 0 99.4315001 0.6584999000000039
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf332 6.30106886729 0 99.432499925 0.6575000749999959
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf333 2.55088214386 0 99.500499575 0.5895004249999914
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf334 6.57211871555 0 99.3380004 0.5279993999999988
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf335 6.30106886729 0 99.4234996 0.6665003999999982
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf336 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf337 2.47778695782 0 99.0089999 1.0215001499999872
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf338 4.73066277039 0 99.511499475 0.578500525000004
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf339 5.92620561097 0 99.42850015 0.6614998499999928
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf340 6.10789096832 0 99.337999325 0.528001012499999
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf341 2.00016617632 0 99.639999 0.45000099999999466
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf342 3.77195447337 0 99.642001075 0.4479989250000017
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf343 5.98028404553 0 99.551499675 0.5385003249999954
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf344 2.47778695782 0 99.443499975 0.6465000250000031
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf345 4.62093815126 0 99.58099945 0.5090005500000047
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf346 3.80166404425 0 99.565000275 0.524999724999995
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf347 2.50228643329 0 99.4395002 0.6504998000000001
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf348 2.00016617632 0 98.419998 1.9050029999999865
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf349 2.5439518228 0 99.21349975 0.7147503750000013
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf350 6.57211871555 0 99.5695004 0.5204996000000023
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf351 2.47778695782 0 99.02399955 0.9990006749999978
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf352 2.81322619695 0 99.337498225 0.5287526624999899
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf353 4.48527898013 0 99.4734996 0.6165004000000011
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf354 2.78229733114 0 99.551499625 0.5385003749999925
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf355 4.93072604433 0 99.473499625 0.6165003749999954
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf356 3.84474688915 0 99.427999575 0.6620004249999966
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf357 3.95967525105 0 99.333499625 0.534750562499994
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf358 3.80166404425 0 99.4210003 0.6689996999999949
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf359 6.30106886729 0 99.4224998 0.6675002000000007
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf360 3.7862916372 0 99.329999175 0.5400012375000003
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf361 2.81322619695 0 99.46900045 0.620999550000002
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf362 4.38652335485 0 99.335999375 0.5310009374999964
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf363 2.55088214386 0 99.264999825 0.6375002624999908
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf364 6.61857279171 0 99.55200015 0.53799985
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf365 5.79060658268 0 99.471500275 0.6184997250000009
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf366 2.5439518228 0 99.48699985 0.6030001499999941
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf367 3.77195447337 0 99.55600025 0.533999750000001
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf368 6.36224047437 0 99.253000075 0.6554998874999924
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf369 5.02870270579 0 99.4630002 0.6269998000000016
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf370 6.7963162944 0 99.447499725 0.6425002749999976
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf371 6.10789096832 0 99.574500175 0.5154998250000006
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf372 2.50228643329 0 99.382000175 0.461999737499994
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf373 3.34244261096 0 99.613501175 0.4764988250000016
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf374 6.14799414721 0 99.4234998 0.6665001999999959
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf375 2.5439518228 0 98.316499775 2.060250337500001
-1 gpu conv samp 35 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf376 3.92040413524 0 99.54199925 0.5480007499999943
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf377 5.22888975029 0 99.508000375 0.5819996250000031
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf378 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf379 4.03997047176 0 99.4290005 0.660999499999997
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf380 3.77195447337 0 99.579999825 0.5100001749999962
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf381 3.85964385182 0 99.46100045 0.6289995499999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf382 4.4071692756 0 99.519999425 0.5700005750000031
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf383 3.63433700317 0 99.644001375 0.44599862499999576
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf384 6.61857279171 0 99.49999985 0.590000150000003
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf385 2.5439518228 0 99.35599865 0.5010020249999911
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf386 6.61857279171 0 99.503999925 0.5860000749999955
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf387 6.16535217595 0 99.412499275 0.6775007249999959
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf388 3.97649090032 0 99.555499475 0.5345005249999929
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf389 5.33920664205 0 99.46450045 0.625499549999995
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf390 2.47124761202 0 99.383499 0.45975149999999587
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf391 3.77195447337 0 99.335499475 0.5317507874999876
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf392 6.61857279171 0 99.460500025 0.629499974999996
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf393 6.36224047437 0 99.441499775 0.6485002250000008
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf394 5.59344058403 0 99.55299965 0.5370003499999939
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf395 6.36224047437 0 99.5040001 0.5859998999999988
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf396 3.08315119118 0 99.56949995 0.520500050000004
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf397 4.93072604433 0 99.556999875 0.5330001249999953
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf398 2.50228643329 0 99.284500025 0.6082499624999969
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf399 2.47124761202 0 99.31950005 0.5557499249999935
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf400 6.10789096832 0 99.412999875 0.6770001250000007
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf401 2.5439518228 0 99.284500375 0.6082494375000067
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf402 2.55088214386 0 98.27499985 2.122500224999996
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf403 3.34244261096 0 99.51049965 0.5795003499999979
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf404 5.22888975029 0 99.512500025 0.5774999750000035
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf405 5.92620561097 0 99.272500625 0.626249062499987
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf406 2.55088214386 0 99.416999825 0.6730001749999929
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf407 2.50228643329 0 98.888500375 1.2022494374999866
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf408 3.97649090032 0 99.417999375 0.672000625000004
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf409 3.85964385182 0 99.437500625 0.6524993749999993
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf410 2.50228643329 0 99.46800095 0.6219990499999938
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf411 4.93072604433 0 99.516499975 0.5735000249999956
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf412 4.64385542353 0 99.558999325 0.5310006749999957
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf413 2.50228643329 0 99.366999125 0.4845013124999866
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf414 4.48527898013 0 99.27900015 0.6164997749999941
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf415 5.75501684906 0 99.582499775 0.5075002249999955
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf416 6.14799414721 0 99.503999875 0.5860001249999925
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf417 4.73066277039 0 99.42850035 0.6614996500000047
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf418 5.79060658268 0 99.5514997 0.538500300000004
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf419 2.50228643329 0 98.90149975 1.1827503749999977
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf420 1.99590274244 0 99.440002 0.6499979999999909
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf421 2.5439518228 0 99.380999675 0.4635004874999993
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf422 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf423 2.55088214386 0 99.040499575 0.9742506374999991
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf424 2.5439518228 0 99.119001075 0.8564983874999967
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf425 6.30106886729 0 99.4704999 0.6195001000000048
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf426 3.97649090032 0 99.463000875 0.6269991249999919
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf427 5.02870270579 0 99.279499875 0.615750187499998
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf428 3.86059861244 0 99.55900015 0.5309998499999949
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf429 2.55088214386 0 99.40249965 0.687500350000002
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf430 2.47778695782 0 99.033499525 0.9847507125000021
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf431 1.99590274244 0 99.400002 0.6899979999999971
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf432 2.81322619695 0 99.5774999 0.5125000999999912
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf433 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf434 3.38717868509 0 99.569500275 0.520499725000002
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf435 2.55088214386 0 98.984499925 1.058250112500005
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf436 6.57211871555 0 99.41049985 0.6795001500000041
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf437 2.57685599488 0 98.3014998 2.0827502999999936
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf438 3.92040413524 0 99.48750085 0.6024991499999942
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf439 4.73066277039 0 99.268000275 0.6329995874999881
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf440 4.90489779833 0 99.42150015 0.6684998499999978
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf441 2.5439518228 0 99.314000025 0.5639999624999987
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf442 2.51187737029 0 99.0054997 1.0267504499999944
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf443 6.14799414721 0 99.55700005 0.5329999499999986
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf444 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf445 2.57685599488 0 99.2825003 0.6112495500000037
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf446 2.47124761202 0 98.8115005 1.3177492500000056
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf447 2.78229733114 0 99.60900025 0.4809997500000037
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf448 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf449 2.57685599488 0 99.0224999 1.001250149999997
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf450 3.97649090032 0 99.51849985 0.57150015
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf451 3.80166404425 0 99.481500675 0.6084993249999912
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf452 2.47778695782 0 99.476501075 0.6134989249999961
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf453 2.57685599488 0 99.40400015 0.6859998499999961
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf454 6.16535217595 0 99.57800005 0.5119999499999978
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf455 6.7963162944 0 99.43149955 0.6585004499999997
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf456 6.16535217595 0 99.3334992 0.5347511999999881
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf457 2.57685599488 0 98.3189993 2.0565010499999943
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf458 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf459 2.51187737029 0 99.4385002 0.6514998000000048
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf460 4.48527898013 0 99.527499525 0.5625004750000017
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf461 6.20621598565 0 99.499999475 0.5900005250000021
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf462 2.5439518228 0 98.809000625 1.3214990625000027
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf463 4.90489779833 0 99.3339999 0.5340001500000042
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf464 3.84474688915 0 99.57100005 0.5189999500000028
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf465 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf466 6.7963162944 0 99.2584997 0.6472504499999943
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf467 6.61857279171 0 99.43000025 0.6599997499999916
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf468 5.22888975029 0 99.51450005 0.5754999500000025
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf469 2.57685599488 0 99.277500725 0.6187489125000027
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf470 2.55088214386 0 98.95650025 1.1002496249999894
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf471 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf472 5.02870270579 0 99.47649985 0.6135001500000016
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf473 6.20621598565 0 99.456000575 0.6339994249999933
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf474 5.79060658268 0 99.4119998 0.678000199999994
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf475 6.20621598565 0 99.4235003 0.6664996999999971
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf476 2.00016617632 0 99.559998 0.5300020000000046
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf477 2.50228643329 0 99.391498725 0.6985012749999925
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf478 2.55088214386 0 99.321500125 0.5527498124999966
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf479 3.92040413524 0 99.574499775 0.515500224999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf480 6.7963162944 0 99.50149975 0.5885002500000042
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf481 2.78229733114 0 99.61500085 0.4749991499999965
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf482 4.64385542353 0 99.51899995 0.5710000500000035
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf483 3.86059861244 0 99.604000675 0.4859993250000031
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf484 5.19985255986 0 99.580500375 0.509499624999998
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf485 2.47124761202 0 99.2139993 0.7140010500000002
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf486 2.50228643329 0 98.319499875 2.0557501874999886
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf487 2.57685599488 0 99.026999275 0.9945010875000051
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf488 3.85964385182 0 99.267500325 0.6337495124999961
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf489 1.99590274244 0 98.940002 1.1249969999999863
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf490 2.57685599488 0 99.3614989 0.4927516499999953
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf491 2.47778695782 0 98.26250005 2.141249924999997
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf492 3.95967525105 0 99.5879999 0.502000099999998
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf493 3.92040413524 0 99.561499525 0.5285004749999956
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf494 4.93072604433 0 99.5169992 0.573000799999997
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf495 2.57685599488 0 98.72399965 1.4490005250000024
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf496 4.03997047176 0 99.26750035 0.6337494749999877
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf497 2.00016617632 0 99.379997 0.46500449999999205
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf498 2.5439518228 0 99.20499985 0.7275002250000071
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf499 3.84474688915 0 99.72549965 0.3645003499999945
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf500 4.51618813067 0 99.5604993 0.5295006999999942
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf501 3.95967525105 0 99.411999625 0.6780003749999907
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf502 5.33920664205 0 99.450000925 0.6399990750000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf503 3.92040413524 0 99.562499325 0.5275006749999932
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf504 2.55088214386 0 99.474500675 0.6154993249999962
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf505 6.30106886729 0 99.268999325 0.6315010125000029
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf506 3.86059861244 0 99.612500925 0.47749907499999156
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf507 3.86059861244 0 99.50949945 0.5805005499999908
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf508 5.33920664205 0 99.26700055 0.6344991749999878
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf509 2.55088214386 0 98.9395005 1.1257492500000055
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf510 2.57685599488 0 99.3634994 0.4897509000000042
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf511 2.47778695782 0 98.987000525 1.054499212499998
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf512 6.30106886729 0 99.5064999 0.5835001000000034
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf513 4.03997047176 0 99.463000375 0.6269996250000048
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf514 6.14799414721 0 99.493500275 0.5964997249999954
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf515 6.20621598565 0 99.51799935 0.5720006500000011
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf516 2.50228643329 0 98.747499825 1.4137502624999883
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf517 5.06758777035 0 99.539499625 0.5505003749999929
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf518 5.33920664205 0 99.474000775 0.6159992250000045
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf519 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf520 2.47778695782 0 99.42150005 0.6684999499999918
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf521 3.38717868509 0 99.3224999 0.5512501500000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf522 4.62093815126 0 99.338999375 0.5265009374999963
-1 gpu conv samp 34 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf523 2.57685599488 0 99.097500525 0.8887492124999952
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf524 2.50228643329 0 99.008999525 1.021500712500007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf525 2.47778695782 0 99.1829998 0.7605002999999897
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf526 5.92620561097 0 99.543499475 0.5465005249999934
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf527 6.61857279171 0 99.49699995 0.5930000499999949
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf528 3.80166404425 0 99.515499425 0.5745005749999962
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf529 2.47778695782 0 99.042499675 0.9712504874999937
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf530 2.50228643329 0 99.37299885 0.47550172499999377
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf531 4.64385542353 0 99.424999925 0.6650000750000032
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf532 2.50228643329 0 99.372999525 0.4755007125000006
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf533 1.99590274244 0 98.599998 1.6350029999999975
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf534 5.02870270579 0 99.449499375 0.6405006249999957
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf535 3.88250959671 0 99.554000025 0.5359999750000043
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf536 3.08315119118 0 99.72599995 0.3640000499999957
-1 gpu conv samp 33 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf537 4.78704248134 0 99.564499975 0.5255000249999938
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf538 2.50228643329 0 99.092500375 0.8962494374999963
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf539 6.36224047437 0 99.5414994 0.5485005999999913
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf540 2.55088214386 0 99.173000725 0.7754989125000051
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf541 2.55088214386 0 98.207499625 2.223750562500001
-1 gpu conv perf 23 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf542 2.5439518228 0 99.0289995 0.9915007500000002
-1 gpu conv samp 36 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf543 3.85964385182 0 99.462500375 0.627499624999993
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf544 5.79060658268 0 99.508000025 0.5819999749999966
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf545 4.93072604433 0 99.42049995 0.6695000499999907
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf546 4.29202279061 0 99.5639995 0.5260005000000035
-1 gpu conv fp16 1 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf547 2.55088214386 0 99.298499575 0.5872506375000057
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf548 3.86059861244 0 99.570500025 0.5194999749999966
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf549 6.7963162944 0 99.459000275 0.6309997250000038
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf550 6.20621598565 0 99.5074999 0.5825000999999986
-1 gpu conv perf 25 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf551 6.14799414721 0 99.508500275 0.5814997249999948
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf552 6.7963162944 0 99.42750015 0.6624998499999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf553 6.20621598565 0 99.5584997 0.531500299999999
-1 gpu conv perf 29 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf554 2.55088214386 0 99.388499675 0.4522504874999882
-1 gpu conv perf 24 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf555 3.92040413524 0 99.324499525 0.5482507125000069
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf556 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf557 3.86059861244 0 99.583500325 0.5064996749999949
-1 gpu conv perf 30 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf558 2.78229733114 0 99.51749825 0.572501749999995
-1 gpu conv perf 28 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf559 4.48527898013 0 99.4650002 0.624999799999992
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf560 3.13161472572 0 99.329499575 0.5407506374999969
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf561 2.57685599488 0 99.369498875 0.4807516874999891
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf562 2.81322619695 0 99.597000425 0.49299957499999325
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf563 5.33920664205 0 99.4605002 0.6294997999999993
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf564 6.7963162944 0 99.454500075 0.6354999249999992
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf565 4.73066277039 0 99.520499175 0.5695008250000001
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf566 2.50228643329 0 97.89149975 2.6977503750000054
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf567 2.50228643329 0 99.444000275 0.6459997250000044
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf568 2.57685599488 0 98.99899945 1.0365008249999974
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf569 2.01610051566 0 99.0 1.0349999999999966
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf570 3.92040413524 0 99.573499575 0.5165004249999982
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf571 6.36224047437 0 99.441499825 0.6485001750000038
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf572 3.77195447337 0 99.31999955 0.5550006749999881
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf573 2.01610051566 0 99.519997 0.5700029999999942
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf574 2.01610051566 0 98.0 2.5349999999999966
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf575 2.50228643329 0 99.37149915 0.4777512749999886
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf576 2.50228643329 0 99.2860005 0.6059992499999964
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf577 2.50228643329 0 99.44100045 0.6489995499999935
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf578 2.81322619695 0 99.469000975 0.6209990249999976
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf579 6.36224047437 0 99.4460002 0.6439997999999975
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf580 2.01610051566 0 99.099998 0.8850029999999975
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf581 2.01610051566 0 99.32 0.5550000000000068
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf582 3.38717868509 0 99.5824997 0.5075002999999981
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf583 3.85964385182 0 99.47850095 0.6114990500000005
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf584 5.33920664205 0 99.473500525 0.616499474999992
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf585 2.57685599488 0 99.4610008 0.6289992000000041
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf586 2.50228643329 0 97.649001025 3.0614984624999906
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf587 2.50228643329 0 98.9994999 1.0357501499999913
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf588 3.38717868509 0 99.585500725 0.5044992749999949
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf589 2.01610051566 0 97.760002 2.8949969999999965
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf590 2.01610051566 0 97.900002 2.6849969999999956
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf591 2.57685599488 0 99.0359988 0.9810017999999943
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf592 2.57685599488 0 99.439000625 0.6509993749999922
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf593 2.01610051566 0 97.620003 3.104995500000001
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf594 2.01610051566 0 99.620003 0.4699970000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf595 2.50228643329 0 98.7414999 1.422750150000006
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf596 2.01610051566 0 97.82 2.805000000000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf597 5.33920664205 0 99.43200015 0.6579998500000045
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf598 5.92620561097 0 99.445 0.6450000000000046
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf599 5.02870270579 0 99.4440004 0.6459996000000047
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf600 6.36224047437 0 99.470000675 0.6199993250000034
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf601 2.50228643329 0 99.41950015 0.6704998499999931
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf602 4.73066277039 0 99.446999975 0.6430000250000006
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf603 4.48527898013 0 99.4805003 0.609499699999995
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf604 3.13161472572 0 99.57349995 0.5165000499999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf605 6.30106886729 0 99.4230005 0.6669994999999972
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf606 2.57685599488 0 99.472000525 0.6179994749999992
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf607 4.73066277039 0 99.472 0.6180000000000035
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf608 5.02870270579 0 99.520999475 0.5690005250000013
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf609 2.01610051566 0 99.400002 0.6899979999999971
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf610 4.73066277039 0 99.26550005 0.6367499249999966
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf611 2.01610051566 0 99.220001 0.7049985000000021
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf612 3.92040413524 0 99.5585006 0.5314993999999956
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf613 5.33920664205 0 99.257 0.6494999999999891
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf614 2.57685599488 0 99.019500225 1.0057496624999942
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf615 4.03997047176 0 99.473000425 0.6169995750000027
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf616 4.48527898013 0 99.4760001 0.6139999000000046
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf617 5.02870270579 0 99.470500125 0.6194998749999968
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf618 5.02870270579 0 99.469500375 0.6204996250000022
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf619 2.57685599488 0 99.3729995 0.4755007499999877
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf620 6.7963162944 0 99.26299995 0.6405000750000056
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf621 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf622 2.57685599488 0 99.4455 0.6445000000000022
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf623 2.01610051566 0 99.580002 0.5099980000000045
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf624 2.57685599488 0 98.894499925 1.1932501124999888
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf625 6.30106886729 0 99.453500225 0.6364997749999987
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf626 2.81322619695 0 99.5449997 0.5450002999999924
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf627 2.50228643329 0 99.40899965 0.6810003499999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf628 6.30106886729 0 99.460500625 0.6294993750000032
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf629 2.57685599488 0 98.8919993 1.1970010500000043
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf630 3.92040413524 0 99.545499225 0.5445007749999974
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf631 5.92620561097 0 99.266500125 0.6352498125000068
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf632 3.38717868509 0 99.3304993 0.5392510499999972
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf633 2.50228643329 0 99.37649925 0.4702511250000043
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf634 2.50228643329 0 99.18549985 0.7567502249999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf635 2.50228643329 0 97.9579998 2.5980003000000025
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf636 2.01610051566 0 98.480003 1.814995500000002
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf637 2.50228643329 0 99.386499425 0.4552508625000016
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf638 2.01610051566 0 98.839996 1.2750059999999976
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf639 5.02870270579 0 99.437000225 0.6529997749999922
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf640 2.81322619695 0 99.578500325 0.5114996750000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf641 2.50228643329 0 98.3239996 2.0490006000000065
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf642 6.30106886729 0 99.498499875 0.5915001250000046
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf643 4.03997047176 0 99.4390005 0.6509994999999918
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf644 3.92040413524 0 99.316999875 0.5595001875000065
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf645 2.01610051566 0 99.480003 0.6099970000000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf646 2.50228643329 0 99.27950065 0.6157490249999924
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf647 2.01610051566 0 99.459999 0.6300010000000015
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf648 2.57685599488 0 97.878499025 2.717251462500002
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf649 6.36224047437 0 99.46100015 0.6289998499999939
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf650 2.01610051566 0 97.699997 2.9850045000000023
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf651 2.01610051566 0 99.540001 0.549998999999994
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf652 2.01610051566 0 99.599998 0.4900019999999984
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf653 2.01610051566 0 98.959999 1.0950015000000022
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf654 5.92620561097 0 99.4569999 0.6330000999999982
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf655 2.57685599488 0 99.266500325 0.6352495125000033
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf656 3.13161472572 0 99.579499825 0.5105001749999986
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf657 2.01610051566 0 98.18 2.2649999999999864
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf658 2.57685599488 0 98.2215007 2.202748949999986
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf659 2.81322619695 0 99.590000575 0.49999942499999295
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf660 2.57685599488 0 97.950000075 2.6099998874999883
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf661 2.57685599488 0 99.175999825 0.7710002624999888
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf662 2.57685599488 0 99.3644998 0.48825029999999003
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf663 2.01610051566 0 99.559998 0.5300020000000046
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf664 2.57685599488 0 98.337999575 2.0280006375
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf665 2.57685599488 0 99.3804991 0.46425135000000495
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf666 6.7963162944 0 99.49299965 0.5970003499999962
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf667 5.92620561097 0 99.513500075 0.5764999250000017
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf668 4.48527898013 0 99.524999925 0.5650000749999947
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf669 3.85964385182 0 99.473000375 0.6169996249999997
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf670 4.03997047176 0 99.4490007 0.6409992999999986
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf671 3.85964385182 0 99.53549905 0.5545009499999992
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf672 4.03997047176 0 99.47100035 0.6189996500000007
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf673 3.85964385182 0 99.4680003 0.6219996999999978
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf674 3.77195447337 0 99.56099965 0.5290003499999983
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf675 4.73066277039 0 99.45050015 0.6394998500000014
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf676 3.38717868509 0 99.545499325 0.5445006750000033
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf677 3.13161472572 0 99.4750006 0.6149993999999964
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf678 2.57685599488 0 97.62400035 3.0989994749999923
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf679 2.50228643329 0 99.47150095 0.6184990499999913
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf680 2.50228643329 0 98.297999825 2.088000262499989
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf681 2.57685599488 0 99.417500325 0.6724996749999917
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf682 2.01610051566 0 98.440002 1.8749969999999863
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf683 4.48527898013 0 99.4639998 0.6260002000000014
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf684 2.50228643329 0 99.473501175 0.6164988250000022
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf685 2.50228643329 0 99.368 0.4830000000000041
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf686 2.57685599488 0 98.73399925 1.4340011250000018
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf687 3.85964385182 0 99.269000825 0.6314987624999873
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf688 5.33920664205 0 99.5154996 0.5745003999999995
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf689 3.38717868509 0 99.4760001 0.6139999000000046
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf690 6.30106886729 0 99.44300025 0.6469997500000005
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf691 4.73066277039 0 99.45850055 0.6314994500000012
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf692 3.77195447337 0 99.582999775 0.5070002249999931
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf693 2.50228643329 0 99.03049945 0.9892508250000063
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf694 2.01610051566 0 98.900002 1.1849969999999956
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf695 2.57685599488 0 99.3689987 0.48150194999998774
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf696 6.7963162944 0 99.43299975 0.6570002500000044
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf697 3.38717868509 0 99.5629995 0.5270004999999941
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf698 4.48527898013 0 99.428500425 0.661499575000002
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf699 2.01610051566 0 99.080002 0.9149970000000067
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf700 2.50228643329 0 98.90549945 1.1767508250000063
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf701 2.81322619695 0 99.334498375 0.5332524375000034
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf702 4.03997047176 0 99.526499175 0.5635008249999999
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf703 2.01610051566 0 98.540001 1.724998499999991
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf704 3.85964385182 0 99.437500375 0.6524996249999987
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf705 5.92620561097 0 99.46749985 0.6225001500000019
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf706 3.77195447337 0 99.54699895 0.5430010499999952
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf707 2.01610051566 0 98.120003 2.354995500000001
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf708 6.30106886729 0 99.265 0.6374999999999957
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf709 2.01610051566 0 97.879997 2.715004499999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf710 3.13161472572 0 99.591500275 0.4984997249999964
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf711 6.36224047437 0 99.26650015 0.6352497749999984
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf712 3.13161472572 0 99.543499225 0.5465007749999927
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf713 2.01610051566 0 99.160004 0.7949939999999955
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf714 2.50228643329 0 99.097500225 0.8887496624999898
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf715 5.92620561097 0 99.471999375 0.618000625000002
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf716 2.01610051566 0 99.68 0.4099999999999909
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf717 2.50228643329 0 99.0050001 1.027499849999991
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf718 2.57685599488 0 98.3044998 2.0782502999999934
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf719 4.03997047176 0 99.2690006 0.6314990999999992
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 7
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf720 3.13161472572 0 99.339998875 0.5250016874999872
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf721 2.50228643329 0 98.887998975 1.2030015374999934
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf722 6.36224047437 0 99.50550005 0.5844999500000029
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf723 2.57685599488 0 98.899499525 1.1857507125000026
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf724 3.77195447337 0 99.58400025 0.5059997499999952
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 4
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf725 5.33920664205 0 99.4505002 0.6394998000000044
-1 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf726 2.57685599488 0 99.397999825 0.6920001749999983
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf727 4.48527898013 0 99.2640007 0.6389989500000013
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 6
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf728 5.02870270579 0 99.26750035 0.6337494749999877
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 5
-3 promise swing_level 7
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf729 6.7963162944 0 99.4540009 0.6359991000000008
-1 gpu conv perf 22 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf730 2.01610051566 0 99.660004 0.42999599999999705
-1 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf731 6.7963162944 0 99.429999925 0.6600000749999936
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf732 2.57685599488 0 99.281500125 0.6127498125000059
-1 gpu conv samp 31 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv samp 32 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf733 2.57685599488 0 99.0864994 0.9052509000000057
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 gpu conv perf 21 add fp16 1 tanh fp16 1 pool_max fp16 1
-3 promise swing_level 6
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf734 3.92040413524 0 99.556999775 0.5330002250000035
-1 gpu conv perf 27 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
-+++++
-conf735 3.92040413524 0 99.47550035 0.6144996499999934
-1 gpu conv perf 26 add fp16 1 tanh fp16 1 pool_max fp16 1
-2 promise swing_level 3
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/promise_flags b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/promise_flags
deleted file mode 100644
index 4926d750802949bb084400efb5b0ae39a2003d57..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/promise_flags
+++ /dev/null
@@ -1,5 +0,0 @@
-7
-7
-7
-7
-7
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/quant_ranges.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/quant_ranges.txt
deleted file mode 100644
index ad8fa364abaa7bb6f17efd3179d4a9f873cf2547..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/quant_ranges.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/quant_ranges_rt.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/quant_ranges_rt.txt
deleted file mode 100644
index 535066863d6100c48a757af3a4c6a92a7458ec65..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/quant_ranges_rt.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-1 0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-2 0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-3 0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-4 0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-5 0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
-6 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/tuner_confs.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/tuner_confs.txt
deleted file mode 100644
index 3417bc4ff1e344809431d98582dced3f5fa84bc4..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/tuner_confs.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-+++++
-conf1 1.5 90
-1 promise swing_level 5
-2 promise swing_level 7
-3 gpu conv perf 1 add fp16 1 relu fp16 1
-4 gpu mul fp16 1 add fp32 1 relu fp32 1
-5 gpu mul fp16 1 add fp16 1 relu fp16 1
-6 gpu softmax fp32 1
------
-+++++
-conf1 1.5 90
-1 promise swing_level 5
-2 gpu conv perf 2 add fp16 1 relu fp16 1
-3 gpu conv perf 1 add fp16 1 relu fp16 1
-4 gpu mul fp16 1 add fp32 1 relu fp32 1
-5 gpu mul fp16 1 add fp16 1 relu fp16 1
-6 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/tuner_confs_base.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/tuner_confs_base.txt
deleted file mode 100644
index 36b4d8bcd26563a1f398df34800ad2b70f24a670..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/data/tuner_confs_base.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-+++++
-conf1 1 0 98.9 0
-1 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-2 gpu conv fp32 1 add fp32 1 pool_max fp32 1 tanh fp32 1
-3 gpu mul fp32 1 add fp32 1 tanh fp32 1
-4 gpu mul fp32 1 add fp32 1 tanh fp32 1
-5 gpu softmax fp32 1
------
-+++++
-conf2 1.5 0 98.9 0
-1 gpu conv fp16 1 add fp16 1 pool_max fp16 1 tanh fp16 1
-2 gpu conv fp16 1 add fp16 1 pool_max fp16 1 tanh fp16 1
-3 gpu mul fp16 1 add fp16 1 tanh fp16 1
-4 gpu mul fp16 1 add fp16 1 tanh fp16 1
-5 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/.#fcl.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/.#fcl.cpp
deleted file mode 120000
index 2024cd179053642170a67ac93731296f36596129..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/.#fcl.cpp
+++ /dev/null
@@ -1 +0,0 @@
-hsharif3@tyler.cs.illinois.edu.16991:1541049775
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/lenet.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/lenet.cpp
deleted file mode 100644
index 81bd920de2ee5452f9f7197d62b4361276a06194..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/lenet.cpp
+++ /dev/null
@@ -1,374 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(11, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 18, 2, 0);
- __visc__bindIn(var_13, 19, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 20, 2, 0);
- __visc__bindIn(var_14, 21, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- __visc__bindOut(var_16, 0, 0, 0);
- __visc__bindOut(var_16, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/lenet_relu/");
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
- std::string labels_path = dir_prefix + std::string("labels.bin");
- uint8_t* labels = readLabels(labels_path.c_str(),10000);
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 10000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/lenet_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/lenet_promise.cpp
deleted file mode 100644
index 0e263f1b0e4cba09c7c50df283efe87737651de7..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet/src/lenet_promise.cpp
+++ /dev/null
@@ -1,374 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(11, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 18, 2, 0);
- __visc__bindIn(var_13, 19, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 20, 2, 0);
- __visc__bindIn(var_14, 21, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- __visc__bindOut(var_16, 0, 0, 0);
- __visc__bindOut(var_16, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/lenet_relu/");
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
- std::string labels_path = dir_prefix + std::string("labels.bin");
- uint8_t* labels = readLabels(labels_path.c_str(),10000);
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 10000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/Makefile
deleted file mode 100644
index fca5a3b2f96e8d646f7d1e69ec623bf5bdd3e03b..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/Makefile
+++ /dev/null
@@ -1,58 +0,0 @@
-# NOTE: $LLVM_SRC_ROOT and $HPVM_BUILD_ROOT have to be set
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_hpvm/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-# NOTE: Change to the name of your benchmark
-APP = lenet
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_LIB_PATH = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -lpthread -lcudart -lcurand -lcudnn -lcublas -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-CONF_FILE_PATH=$(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks/benchmarks/lenet_base/data/tuner_confs.txt
-# NOTE: Needs proper handling in the WRAPPER backend because Quant range not needed for IMAGE Benchmarks
-WRAPPER_API_QUANT_FILE_PATH=$(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks/benchmarks/lenet_base/data/quant_ranges_rt.txt
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_WrapperAPI.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMFuseHPVMTensorNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -hpvm-fuse -dfg2llvm-wrapperapi -quantization-levels-filename=$(WRAPPER_API_QUANT_FILE_PATH) -configuration-inputs-filename=$(CONF_FILE_PATH) -dfg2llvm-x86 -clearDFG
-
-
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm src/$(APP).cpp -S -o $(BUILD_DIR)/$(APP).ll
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP).ll -S -o $(BUILD_DIR)/$(APP).visc.ll
- $(OPT) $(VISC_OPTFLAGS) $(BUILD_DIR)/$(APP).visc.ll -o $(BUILD_DIR)/$(APP)_wrapper.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_wrapper.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_wrapper_linked.bc
- $(CC) $(BUILD_DIR)/$(APP)_wrapper_linked.bc $(TENSOR_LIB_PATH) -o $(BUILD_DIR)/lenet_final $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/promise_flags b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/promise_flags
deleted file mode 100644
index 4926d750802949bb084400efb5b0ae39a2003d57..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/promise_flags
+++ /dev/null
@@ -1,5 +0,0 @@
-7
-7
-7
-7
-7
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/quant_ranges.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/quant_ranges.txt
deleted file mode 100644
index ad8fa364abaa7bb6f17efd3179d4a9f873cf2547..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/quant_ranges.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/quant_ranges_rt.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/quant_ranges_rt.txt
deleted file mode 100644
index 535066863d6100c48a757af3a4c6a92a7458ec65..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/quant_ranges_rt.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-1 0.0 1.0 -0.3 0.3 -0.041063767 0.031912163 0.0 1.5512946
-2 0.0 1.5512946 -0.15580177 0.1533 -0.041385915 0.05869476 0.0 4.916329
-3 0.0 4.916329 -0.20324017 0.18275258 -0.039915435 0.04589232 0.0 9.447418
-4 0.0 9.447418 -0.10757191 0.123126 -0.025070198 0.027000334 0.0 9.926857
-5 0.0 9.926857 -0.18867673 0.16425411 -0.012622595 0.04586973 0.0 42.018578
-6 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/tuner_confs.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/tuner_confs.txt
deleted file mode 100644
index 6d896a39c1b4c1da48e684505478ff6d7839a366..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/data/tuner_confs.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-+++++
-conf1 1.5 90
-1 promise swing_level 5
-2 promise swing_level 7
-3 gpu conv fp16 1 add fp16 1 relu fp16 1
-4 gpu mul fp16 1 add fp32 1 relu fp32 1
-5 gpu mul fp16 1 add fp16 1 relu fp16 1
-6 gpu softmax fp32 1
------
-+++++
-conf1 1.5 90
-1 promise swing_level 5
-2 gpu conv fp16 2 add fp16 1 relu fp16 1
-3 gpu conv fp16 1 add fp16 1 relu fp16 1
-4 gpu mul fp16 1 add fp32 1 relu fp32 1
-5 gpu mul fp16 1 add fp16 1 relu fp16 1
-6 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/src/lenet.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/src/lenet.cpp
deleted file mode 100644
index 0e263f1b0e4cba09c7c50df283efe87737651de7..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_base/src/lenet.cpp
+++ /dev/null
@@ -1,374 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(11, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 18, 2, 0);
- __visc__bindIn(var_13, 19, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 20, 2, 0);
- __visc__bindIn(var_14, 21, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- __visc__bindOut(var_16, 0, 0, 0);
- __visc__bindOut(var_16, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/lenet_relu/");
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
- std::string labels_path = dir_prefix + std::string("labels.bin");
- uint8_t* labels = readLabels(labels_path.c_str(),10000);
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 10000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_batchnorm/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_batchnorm/Makefile
deleted file mode 100644
index bf3ee06bfdb4b732d7692b2e04ad1af8defde8ce..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_batchnorm/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-# NOTE: can configure build directory
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_hpvm/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = lenet
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_LIB_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a
-TENSOR_AUTOTUNER_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_autotuner.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -lpthread -lcudart -lcurand -lcudnn -lcublas -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_CUDNN.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -dfg2llvm-cudnn -dfg2llvm-x86 -clearDFG
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm -S -o $@ $<
-
-#-visc-timers-gen
-$(BUILD_DIR)/%.visc.ll: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $< -S -o $@
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.visc.ll
- $(OPT) $(VISC_OPTFLAGS) $< -o $@
- $(LLVM_LINK) $@ $(VISC_RT_PATH) -o $(BUILD_DIR)/lenet_linked.bc
- $(CC) $(BUILD_DIR)/lenet_linked.bc $(TENSOR_LIB_DIR) -o $(BUILD_DIR)/lenet_linked $(LINKER_FLAGS)
- $(CC) $(BUILD_DIR)/lenet_linked.bc $(TENSOR_AUTOTUNER_DIR) -o $(BUILD_DIR)/lenet_tune $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_batchnorm/src/lenet.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_batchnorm/src/lenet.cpp
deleted file mode 100644
index 15eda60b0b8d1513b93cc560f3370dafdc73b256..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_batchnorm/src/lenet.cpp
+++ /dev/null
@@ -1,415 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 32);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* batch_normalization_1_gamma, size_t batch_normalization_1_gamma_bytes,
- void* batch_normalization_1_beta, size_t batch_normalization_1_beta_bytes,
- void* batch_normalization_1_mean, size_t batch_normalization_1_mean_bytes,
- void* batch_normalization_1_variance, size_t batch_normalization_1_variance_bytes,
- void* depthwise_conv2d_1_w, size_t depthwise_conv2d_1_w_bytes,
- void* depthwise_conv2d_1_b, size_t depthwise_conv2d_1_b_bytes,
- void* batch_normalization_2_gamma, size_t batch_normalization_2_gamma_bytes,
- void* batch_normalization_2_beta, size_t batch_normalization_2_beta_bytes,
- void* batch_normalization_2_mean, size_t batch_normalization_2_mean_bytes,
- void* batch_normalization_2_variance, size_t batch_normalization_2_variance_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(17, input, conv2d_1_w, conv2d_1_b, batch_normalization_1_gamma, batch_normalization_1_beta, batch_normalization_1_mean, batch_normalization_1_variance, depthwise_conv2d_1_w, depthwise_conv2d_1_b, batch_normalization_2_gamma, batch_normalization_2_beta, batch_normalization_2_mean, batch_normalization_2_variance, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
- __visc__bindIn(var_3, 8, 4, 0);
- __visc__bindIn(var_3, 9, 5, 0);
- __visc__bindIn(var_3, 10, 6, 0);
- __visc__bindIn(var_3, 11, 7, 0);
- __visc__bindIn(var_3, 12, 8, 0);
- __visc__bindIn(var_3, 13, 9, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 14, 2, 0);
- __visc__bindIn(var_5, 15, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
- __visc__bindIn(var_6, 16, 2, 0);
- __visc__bindIn(var_6, 17, 3, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 18, 2, 0);
- __visc__bindIn(var_8, 19, 3, 0);
- __visc__bindIn(var_8, 20, 4, 0);
- __visc__bindIn(var_8, 21, 5, 0);
- __visc__bindIn(var_8, 22, 6, 0);
- __visc__bindIn(var_8, 23, 7, 0);
- __visc__bindIn(var_8, 24, 8, 0);
- __visc__bindIn(var_8, 25, 9, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 26, 2, 0);
- __visc__bindIn(var_9, 27, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 28, 2, 0);
- __visc__bindIn(var_10, 29, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 30, 2, 0);
- __visc__bindIn(var_12, 31, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 32, 2, 0);
- __visc__bindIn(var_13, 33, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
-
- __visc__bindOut(var_15, 0, 0, 0);
- __visc__bindOut(var_15, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* batch_normalization_1_gamma;
- size_t batch_normalization_1_gamma_bytes;
- void* batch_normalization_1_beta;
- size_t batch_normalization_1_beta_bytes;
- void* batch_normalization_1_mean;
- size_t batch_normalization_1_mean_bytes;
- void* batch_normalization_1_variance;
- size_t batch_normalization_1_variance_bytes;
- void* depthwise_conv2d_1_w;
- size_t depthwise_conv2d_1_w_bytes;
- void* depthwise_conv2d_1_b;
- size_t depthwise_conv2d_1_b_bytes;
- void* batch_normalization_2_gamma;
- size_t batch_normalization_2_gamma_bytes;
- void* batch_normalization_2_beta;
- size_t batch_normalization_2_beta_bytes;
- void* batch_normalization_2_mean;
- size_t batch_normalization_2_mean_bytes;
- void* batch_normalization_2_variance;
- size_t batch_normalization_2_variance_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/depthwise_batchnorm2/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_gamma_path = dir_prefix + std::string("batch_normalization_1_gamma.bin");
- void* batch_normalization_1_gamma = readTrainedWeights(batch_normalization_1_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_beta_path = dir_prefix + std::string("batch_normalization_1_beta.bin");
- void* batch_normalization_1_beta = readTrainedWeights(batch_normalization_1_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_mean_path = dir_prefix + std::string("batch_normalization_1_mean.bin");
- void* batch_normalization_1_mean = readTrainedWeights(batch_normalization_1_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_variance_path = dir_prefix + std::string("batch_normalization_1_variance.bin");
- void* batch_normalization_1_variance = readTrainedWeights(batch_normalization_1_variance_path.c_str(), 0,1,32,1,1);
- std::string depthwise_conv2d_1_w_path = dir_prefix + std::string("depthwise_conv2d_1_w.bin");
- void* depthwise_conv2d_1_w = readTrainedWeights(depthwise_conv2d_1_w_path.c_str(), 0,32,1,3,3);
- std::string depthwise_conv2d_1_b_path = dir_prefix + std::string("depthwise_conv2d_1_b.bin");
- void* depthwise_conv2d_1_b = readTrainedWeights(depthwise_conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_gamma_path = dir_prefix + std::string("batch_normalization_2_gamma.bin");
- void* batch_normalization_2_gamma = readTrainedWeights(batch_normalization_2_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_beta_path = dir_prefix + std::string("batch_normalization_2_beta.bin");
- void* batch_normalization_2_beta = readTrainedWeights(batch_normalization_2_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_mean_path = dir_prefix + std::string("batch_normalization_2_mean.bin");
- void* batch_normalization_2_mean = readTrainedWeights(batch_normalization_2_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_variance_path = dir_prefix + std::string("batch_normalization_2_variance.bin");
- void* batch_normalization_2_variance = readTrainedWeights(batch_normalization_2_variance_path.c_str(), 0,1,32,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,6272,1024);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
- uint8_t* labels = readLabels(labels_path.c_str(),10000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->batch_normalization_1_gamma = batch_normalization_1_gamma;
- args->batch_normalization_1_gamma_bytes = 0;
- args->batch_normalization_1_beta = batch_normalization_1_beta;
- args->batch_normalization_1_beta_bytes = 0;
- args->batch_normalization_1_mean = batch_normalization_1_mean;
- args->batch_normalization_1_mean_bytes = 0;
- args->batch_normalization_1_variance = batch_normalization_1_variance;
- args->batch_normalization_1_variance_bytes = 0;
- args->depthwise_conv2d_1_w = depthwise_conv2d_1_w;
- args->depthwise_conv2d_1_w_bytes = 0;
- args->depthwise_conv2d_1_b = depthwise_conv2d_1_b;
- args->depthwise_conv2d_1_b_bytes = 0;
- args->batch_normalization_2_gamma = batch_normalization_2_gamma;
- args->batch_normalization_2_gamma_bytes = 0;
- args->batch_normalization_2_beta = batch_normalization_2_beta;
- args->batch_normalization_2_beta_bytes = 0;
- args->batch_normalization_2_mean = batch_normalization_2_mean;
- args->batch_normalization_2_mean_bytes = 0;
- args->batch_normalization_2_variance = batch_normalization_2_variance;
- args->batch_normalization_2_variance_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 10000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/Makefile
deleted file mode 100644
index 578cfc713eef378bfb23222b4ed3e8b1abd7e7d9..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/Makefile
+++ /dev/null
@@ -1,79 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-# NOTE: CHANGE to your BUILD DIRECTORY
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_dsoc/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = lenet
-
-define \n
-
-
-endef
-
-COMMON_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-DNN_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/dnn_sources/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_RT_SRC_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/src
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(DNN_INCLUDE_DIR) -I $(COMMON_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-LINKER_FLAGS = -lpthread -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-OPTFLAGS1 = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/ReplaceIntrinsics.so -load $(HPVM_LIB_DIR)/DFG2LLVM_X86_dsoc.so -load $(HPVM_LIB_DIR)/ExtractHPVMLeafNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -replace-intrinsics -dfg2llvm-x86-dsoc -hpvm-extract-leaf-gen -clearDFG
-
-OPTFLAGS2 = -load $(HPVM_LIB_DIR)/InlineTensorCalls.so -inline-tensor-calls
-
-TARGET = $(BUILD_DIR)/$(APP).final.bc
-
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/projects/visc-cpu-rt/visc-rt.ll
-
-
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm -S -o $@ $<
-
-#-visc-timers-gen
-$(BUILD_DIR)/%.visc.ll: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $< -S -o $@
-
-
-expanded_modules:= $(wildcard *_module.ll)
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.visc.ll
- $(OPT) $(OPTFLAGS1) $< -o $@
-
-
-$(BUILD_DIR)/%.linked.bc: $(BUILD_DIR)/%.opt.bc
- $(CC) -emit-llvm -c $(TENSOR_RT_SRC_DIR)/tensor_cpu_runtime.cc -o $(BUILD_DIR)/tensor_cpu_runtime.bc
- $(OPT) -always-inline $(BUILD_DIR)/tensor_cpu_runtime.bc -o $(BUILD_DIR)/tensor_cpu_runtime.bc
- $(LLVM_LINK) $< $(shell find ./build -name "*module.ll") $(BUILD_DIR)/tensor_cpu_runtime.bc $(VISC_RT_PATH) -o $@
-
-
-$(BUILD_DIR)/%.final.bc: $(BUILD_DIR)/%.linked.bc
- $(OPT) $(OPTFLAGS2) $< -o $@
- $(CC) $@ -o $(BUILD_DIR)/$(APP)_final $(LINKER_FLAGS)
- $(foreach module, $(expanded_modules), $(LLVM_LINK) $(module) $(BUILD_DIR)/tensor_cpu_runtime.bc -o $(BUILD_DIR)/$(module)_linked ${\n} $(OPT) $(OPTFLAGS2) $(BUILD_DIR)/$(module)_linked -o $(BUILD_DIR)/$(module)_inline ${\n} )
-
-
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
-
-
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/approxhpvm_src.cc b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/approxhpvm_src.cc
deleted file mode 100644
index 96b24a0409ae15f708bd7b6897edca08e52d82bb..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/approxhpvm_src.cc
+++ /dev/null
@@ -1,373 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(11, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 18, 2, 0);
- __visc__bindIn(var_13, 19, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 20, 2, 0);
- __visc__bindIn(var_14, 21, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- __visc__bindOut(var_16, 0, 0, 0);
- __visc__bindOut(var_16, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
-std::string dir_prefix = std::string("lenet_hpvm/");
-std::string input_path = dir_prefix + std::string("input.bin");
-void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
-std::string labels_path = dir_prefix + std::string("labels.bin");
-uint8_t* labels = readLabels(labels_path.c_str(),10000);
-std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
-void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
-std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
-void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
-void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
-std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
-void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
-std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
-void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
-std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
-void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
-std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
-void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
-std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
-void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
-std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
-void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
-std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
-void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
-__visc__init();
-RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
-args->input = input;
-args->input_bytes = 0;
-args->conv2d_1_w = conv2d_1_w;
-args->conv2d_1_w_bytes = 0;
-args->conv2d_1_b = conv2d_1_b;
-args->conv2d_1_b_bytes = 0;
-args->conv2d_2_w = conv2d_2_w;
-args->conv2d_2_w_bytes = 0;
-args->conv2d_2_b = conv2d_2_b;
-args->conv2d_2_b_bytes = 0;
-args->conv2d_3_w = conv2d_3_w;
-args->conv2d_3_w_bytes = 0;
-args->conv2d_3_b = conv2d_3_b;
-args->conv2d_3_b_bytes = 0;
-args->dense_1_w = dense_1_w;
-args->dense_1_w_bytes = 0;
-args->dense_1_b = dense_1_b;
-args->dense_1_b_bytes = 0;
-args->dense_2_w = dense_2_w;
-args->dense_2_w_bytes = 0;
-args->dense_2_b = dense_2_b;
-args->dense_2_b_bytes = 0;
-
-void* dfg = __visc__launch(0, root, (void*) args);
-
-__visc__wait(dfg);
-
-void *result = static_cast<RootIn*>(args)->input;
-hpvm_request_tensor(result, 0);
-
-__visc__cleanup();
- computeAccuracy2(labels, 10000, result);
-return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_1_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_1_b.bin
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_1_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_1_w.bin
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index f1cabdb56c1275f03b226c9636b546382a3accc3..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_2_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_2_b.bin
deleted file mode 100644
index 2232a48e41b564a7583ef74acfdc0637856a45f7..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_2_b.bin
+++ /dev/null
@@ -1,2 +0,0 @@
-7Dà<Þå<– ^=À©Š=p =˜<Y-¼ Rž= é<¦:ï;
-cƒ<- =&= "=áx´;Ñu<¼ö·F=t_; 9=ûSO¼²vŸ;G¨»éM8=+¦x½`žŒ<RªŒ:ßPP;/®™<Ûè¼ø®ä; ^Ð<'´9¼43û:ÙË;eø<AÖ#½ Ò»‹±e<••<ó¯==Ÿ¨<À´b<»0à<4È< Óö;\§<#t
<}¨½ƒp¼¬=:s"½p#¨¼v'™¼ð^;@Ç<ë8\¼É‡à<ëþ¾¼`ýa»Î€^¼`‚û;sjÉ<w”L=üÙ«¼
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_2_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/conv2d_2_w.bin
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/dense_2_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/dense_2_b.bin
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/input.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/input.bin
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/labels.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/labels.bin
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/promise_src.cc b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/promise_src.cc
deleted file mode 100644
index 46f4637460485f6d1686901c099d77929099b823..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/promise_src.cc
+++ /dev/null
@@ -1,58 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <string.h>
-#include "../../../tensor_runtime/include/tensor_runtime.h"
-#include "../../include/utils.h"
-
-int main(){
-
-llvm_hpvm_initTensorRt(0);
-
-
-
-std::string dir_prefix = std::string("lenet_hpvm/");
-std::string input_path = dir_prefix + std::string("input.bin");
-void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
-std::string labels_path = dir_prefix + std::string("labels.bin");
-uint8_t* labels = readLabels(labels_path.c_str(),10000);
-std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
-void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
-std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
-void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
-void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
-std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
-void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
-std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
-void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
-std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
-void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
-std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
-void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
-std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
-void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
-std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
-void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
-std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
-void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
-
-void* var_0 = ConvLayer_PROMISE(input, 0.0, 1.0, conv2d_1_w, -0.23503187, 0.22027442, conv2d_1_b, -0.059452552, 0.05141998, 2, 2, 1, 1, 0, 2, 1, 0.0, 1.4499073, 9);
-void* var_1 = ConvLayer_PROMISE(var_0, 0.0, 1.4499073, conv2d_2_w, -0.16616209, 0.1624253, conv2d_2_b, -0.060705345, 0.07730491, 2, 2, 1, 1, -1, 0, 1, 0.0, 4.394469, 9);
-void* var_2 = ConvLayer_PROMISE(var_1, 0.0, 4.394469, conv2d_3_w, -0.17305803, 0.16375193, conv2d_3_b, -0.01982658, 0.05104504, 1, 1, 2, 2, -1, 0, 1, 0.0, 8.275149, 9);
-void* var_3 = FCLayer_PROMISE(var_2, 0.0, 8.275149, dense_1_w, -0.10478318, 0.10765447, dense_1_b, -0.0300005, 0.03506347, 1, 0.0, 9.308638, 9);
-void* var_4 = FCLayer_PROMISE(var_3, 0.0, 9.308638, dense_2_w, -0.1958274, 0.14691855, dense_2_b, -0.007710449, 0.039741356, 1, 0.0, 36.96972, 9);
-void* var_5 = tensorSoftmax(var_4);
-
-computeAccuracy2(labels,10000,var_5);
-
-llvm_hpvm_cleanupTensorRt();
-
-return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/src.cc b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/src.cc
deleted file mode 100644
index c26e11316b648481518ee3b41d029e03d6860e91..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/data/lenet_hpvm/src.cc
+++ /dev/null
@@ -1,68 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <string.h>
-#include "../../tensor_runtime/include/tensor_runtime.h"
-#include "../include/utils.h"
-
-int main(){
-
-llvm_hpvm_initTensorRt(0);
-
-
-std::string dir_prefix = std::string("lenet_hpvm/");
-std::string input_path = dir_prefix + std::string("input.bin");
-void* input = readTrainedWeights(input_path.c_str(), 0,10000,1,28,28);
-std::string labels_path = dir_prefix + std::string("labels.bin");
-uint8_t* labels = readLabels(labels_path.c_str(),10000);
-std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
-void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
-std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
-void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
-void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
-std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
-void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
-std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
-void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
-std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
-void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
-std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
-void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
-std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
-void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
-std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
-void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
-std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
-void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
-
-void* var_0 = tensorConvolution(input, conv2d_1_w, 2, 2, 1, 1, 1, 0);
-void* var_1 = tensorAdd(var_0, conv2d_1_b);
-void* var_2 = tensorRelu(var_1);
-void* var_3 = tensorPooling(var_2,0,2,2,0,0,2,2);
-void* var_4 = tensorConvolution(var_3, conv2d_2_w, 2, 2, 1, 1, 1, 0);
-void* var_5 = tensorAdd(var_4, conv2d_2_b);
-void* var_6 = tensorRelu(var_5);
-void* var_8 = tensorConvolution(var_6, conv2d_3_w, 1, 1, 2, 2, 1, 0);
-void* var_9 = tensorAdd(var_8, conv2d_3_b);
-void* var_10 = tensorRelu(var_9);
-void* var_12 = tensorGemmGPU(var_10, dense_1_w);
-void* var_13 = tensorAdd(var_12, dense_1_b);
-void* var_14 = tensorRelu(var_13);
-void* var_15 = tensorGemmGPU(var_14, dense_2_w);
-void* var_16 = tensorAdd(var_15, dense_2_b);
-void* var_17 = tensorRelu(var_16);
-void* var_18 = tensorSoftmax(var_17);
-
-computeAccuracy2(labels,10000,var_18);
-
-llvm_hpvm_cleanupTensorRt();
-
-return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/src/.#fcl.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/src/.#fcl.cpp
deleted file mode 120000
index 2024cd179053642170a67ac93731296f36596129..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/src/.#fcl.cpp
+++ /dev/null
@@ -1 +0,0 @@
-hsharif3@tyler.cs.illinois.edu.16991:1541049775
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/src/lenet.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/src/lenet.cpp
deleted file mode 100644
index eb74dc53feeb887e7a3c0fe02cbd23c851d5a6ec..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/lenet_dsoc/src/lenet.cpp
+++ /dev/null
@@ -1,380 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <string.h>
-#include <visc.h>
-
-//#include <tensorTypes.h>
-//#include <tensorUtils.h>
-
-// NOTE: Include file has to be changed for CPU Tensor Runtime
-#include <utils_cpu.h>
-
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(11, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 18, 2, 0);
- __visc__bindIn(var_13, 19, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 20, 2, 0);
- __visc__bindIn(var_14, 21, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- __visc__bindOut(var_16, 0, 0, 0);
- __visc__bindOut(var_16, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../data/lenet_hpvm/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0,500,1,28,28);
- std::string labels_path = dir_prefix + std::string("labels.bin");
- uint8_t* labels = readLabels(labels_path.c_str(),100);
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 100, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/Makefile
deleted file mode 100644
index d1d284a26f2fb089d4c46aef213dc03d471b898e..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/Makefile
+++ /dev/null
@@ -1,79 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-# NOTE: CHANGE to your BUILD DIRECTORY
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_dsoc/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = mini_era_cv
-
-define \n
-
-
-endef
-
-COMMON_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-DNN_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/dnn_sources/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_RT_SRC_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/src
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(DNN_INCLUDE_DIR) -I $(COMMON_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-LINKER_FLAGS = -lpthread -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-OPTFLAGS1 = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/ReplaceIntrinsics.so -load $(HPVM_LIB_DIR)/DFG2LLVM_X86_dsoc.so -load $(HPVM_LIB_DIR)/ExtractHPVMLeafNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -replace-intrinsics -dfg2llvm-x86-dsoc -hpvm-extract-leaf-gen -clearDFG
-
-OPTFLAGS2 = -load $(HPVM_LIB_DIR)/InlineTensorCalls.so -inline-tensor-calls
-
-TARGET = $(BUILD_DIR)/$(APP).final.bc
-
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/projects/visc-cpu-rt/visc-rt.ll
-
-
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm -S -o $@ $<
-
-#-visc-timers-gen
-$(BUILD_DIR)/%.visc.ll: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $< -S -o $@
-
-
-expanded_modules:= $(wildcard *_module.ll)
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.visc.ll
- $(OPT) $(OPTFLAGS1) $< -o $@
-
-
-$(BUILD_DIR)/%.linked.bc: $(BUILD_DIR)/%.opt.bc
- $(CC) -emit-llvm -c $(TENSOR_RT_SRC_DIR)/tensor_cpu_runtime.cc -o $(BUILD_DIR)/tensor_cpu_runtime.bc
- $(OPT) -always-inline $(BUILD_DIR)/tensor_cpu_runtime.bc -o $(BUILD_DIR)/tensor_cpu_runtime.bc
- $(LLVM_LINK) $< $(shell find ./build -name "*module.ll") $(BUILD_DIR)/tensor_cpu_runtime.bc $(VISC_RT_PATH) -o $@
-
-
-$(BUILD_DIR)/%.final.bc: $(BUILD_DIR)/%.linked.bc
- $(OPT) $(OPTFLAGS2) $< -o $@
- $(CC) $@ -o $(BUILD_DIR)/$(APP)_final $(LINKER_FLAGS)
- $(foreach module, $(expanded_modules), $(LLVM_LINK) $(module) $(BUILD_DIR)/tensor_cpu_runtime.bc -o $(BUILD_DIR)/$(module)_linked ${\n} $(OPT) $(OPTFLAGS2) $(BUILD_DIR)/$(module)_linked -o $(BUILD_DIR)/$(module)_inline ${\n} )
-
-
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
-
-
-
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/approxhpvm_src.cc b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/approxhpvm_src.cc
deleted file mode 100644
index d8985397705cf19d5533a7e4a376a71a9f130fb0..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/approxhpvm_src.cc
+++ /dev/null
@@ -1,430 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(13, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 8, 2, 0);
- __visc__bindIn(var_4, 9, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
- __visc__bindIn(var_17, 22, 2, 0);
- __visc__bindIn(var_17, 23, 3, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 24, 2, 0);
- __visc__bindIn(var_18, 25, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
-
- __visc__bindOut(var_19, 0, 0, 0);
- __visc__bindOut(var_19, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
-std::string dir_prefix = std::string("hpvm_mio_4/");
-std::string input_path = dir_prefix + std::string("input.bin");
-std::string labels_path = dir_prefix + std::string("labels.bin");
-std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
-void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
-std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
-void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
-void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,32,32,3,3);
-std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
-void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
-void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,32,3,3);
-std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
-void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
-std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
-void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,64,64,3,3);
-std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
-void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,64,1,1);
-std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
-void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,1600,256);
-std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
-void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,256,1,1);
-std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
-void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,256,5);
-std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
-void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,5,1,1);
-void* input = readTrainedWeights(input_path.c_str(), 0,5000,3,32,32);
-uint32_t* labels = readLabels2(labels_path.c_str(),5000);
-
-__visc__init();
-RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
-args->input = input;
-args->input_bytes = 0;
-args->conv2d_1_w = conv2d_1_w;
-args->conv2d_1_w_bytes = 0;
-args->conv2d_1_b = conv2d_1_b;
-args->conv2d_1_b_bytes = 0;
-args->conv2d_2_w = conv2d_2_w;
-args->conv2d_2_w_bytes = 0;
-args->conv2d_2_b = conv2d_2_b;
-args->conv2d_2_b_bytes = 0;
-args->conv2d_3_w = conv2d_3_w;
-args->conv2d_3_w_bytes = 0;
-args->conv2d_3_b = conv2d_3_b;
-args->conv2d_3_b_bytes = 0;
-args->conv2d_4_w = conv2d_4_w;
-args->conv2d_4_w_bytes = 0;
-args->conv2d_4_b = conv2d_4_b;
-args->conv2d_4_b_bytes = 0;
-args->dense_1_w = dense_1_w;
-args->dense_1_w_bytes = 0;
-args->dense_1_b = dense_1_b;
-args->dense_1_b_bytes = 0;
-args->dense_2_w = dense_2_w;
-args->dense_2_w_bytes = 0;
-args->dense_2_b = dense_2_b;
-args->dense_2_b_bytes = 0;
-
-void* dfg = __visc__launch(0, root, (void*) args);
-
-__visc__wait(dfg);
-
-void *result = static_cast<RootIn*>(args)->input;
-hpvm_request_tensor(result, 0);
-
-__visc__cleanup();
- computeAccuracy3(labels, result);
-return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_1_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_1_b.bin
deleted file mode 100644
index 39c3fbac7f94a6824736f8b21f184b71b3d45a7b..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_1_b.bin
+++ /dev/null
@@ -1,2 +0,0 @@
-αÝ>aŸ¾Ì?N?„œQ¿JÙ%½t ‰¼ªl©=™&¼½œ ¿¿^L8?د > r¾:õö¾
νóù¼š¶?B Y?–;Uì>ç—=€ëh?rXö½ï
-‹=&ç½Ýˆ™½C#S>¥”½7ü¹>vÉ…>ɇ¿ !?
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_1_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_1_w.bin
deleted file mode 100644
index d01508286ed5fddf05790e261efa168847699efd..0000000000000000000000000000000000000000
Binary files a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_1_w.bin and /dev/null differ
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_2_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_2_b.bin
deleted file mode 100644
index 39489675632774a46e0ea704d7d13807b2e4feb5..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_2_b.bin
+++ /dev/null
@@ -1,2 +0,0 @@
-„§Ÿ½æ.î=•·?¾Š¥¿vƒ¿ºS¿Óë†»Þ >
-Qżøæ¼å—8¿ÂVä».I>Æp𼄃;dd=h䈾Ðé¾N½.¾ÓñÍ=/Ú¾ŒÖl¾×;¾ ð4¾6ƒ>cTʾR¶ ¼ê¿¾ô2Í=c_¨¾¾ÚZ¾
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_2_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_2_w.bin
deleted file mode 100644
index 381b72379b85614a79910c9560c6115310da538a..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_3_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_3_b.bin
deleted file mode 100644
index 43fe41a6edcae03a1a531123940e528a71807300..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_3_b.bin
+++ /dev/null
@@ -1 +0,0 @@
-˜Ò½Ê+¥½ò?Š$ù¾méÊ>(>¼½hŠ >qÂB½y²*½‚ì>IÒ¸>»Kˆ?@ ¨¼t\¢?æ H¾
•=ùÔý>…œ;½_å—>Ÿfœ=;┿®Œû>›jÞ¾DâÓ»×Á‰¾šU>·`†? Éc>ÈŽ?Õª?Ÿ·/< #&?—?ôðš¾Dy<Hbf¾lò:?ÑwS¾M
)>}¾«t ¾Ÿt'?ö¥ú¿´$¾<¥!æ½ œ?Ë¡½c’‹<Za¾>E5“>0Jê>p9J¾†žÁ>ÞWð>nèr>e–'?¹+R¿Gž>kæò;·bÆ¿²àR>˜{ÿ>ãš½
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_3_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_3_w.bin
deleted file mode 100644
index a82a9e397918217bf37873c59dd92bee713fa9df..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_4_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_4_b.bin
deleted file mode 100644
index bd29ee60df1f0f0b3a199f1f65adb810a2649a3c..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_4_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/conv2d_4_w.bin
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index 7f6211e76617ee18dac06c9b5449c18183a149de..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_1_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_1_b.bin
deleted file mode 100644
index fae8736fa3da691229c66e73962cb4f0131c2961..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_1_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_1_w.bin
deleted file mode 100644
index 034b84905ae34893f5b57be77033fd91b388a80b..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_2_b.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_2_b.bin
deleted file mode 100644
index 2bb9d3e89f7d35a4e66063ec93baab23ef90b86e..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_2_b.bin
+++ /dev/null
@@ -1 +0,0 @@
-k"õ;(¿¾òë>™¿JÄ@?
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_2_w.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/dense_2_w.bin
deleted file mode 100644
index f3bce42e01c37928d0cd54493835bcda70529bf2..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/input.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/input.bin
deleted file mode 100644
index 0abae55bf84ff5dc8e2d1074c97853331fc5d879..0000000000000000000000000000000000000000
Binary files a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/input.bin and /dev/null differ
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/labels.bin b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/labels.bin
deleted file mode 100644
index effaef8583b30228039ff7f61d9c6be51c020b49..0000000000000000000000000000000000000000
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diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/layer_composition.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/layer_composition.txt
deleted file mode 100644
index 54ef6c9f01517d20355681b1d19c8b865daf514c..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/layer_composition.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-conv add activation
-conv add activation pool
-conv add activation
-conv add activation pool
-dense add activation
-dense add
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/layers.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/layers.txt
deleted file mode 100644
index c0aecb467775babfd4b5c2873abf287905ee11f8..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/layers.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Conv1,5000,3,32,32,32,3,3,3
-Conv2,5000,32,30,30,32,32,3,3
-Conv3,5000,32,14,14,64,32,3,3
-Conv4,5000,64,12,12,64,64,3,3
-FC1,5000,1600,1600,256
-FC2,5000,256,256,5
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/promise_src.cc b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/promise_src.cc
deleted file mode 100644
index fd96ab0878269718c58c52115a22b79e2f62ec99..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/promise_src.cc
+++ /dev/null
@@ -1,93 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <string.h>
-#include "../../../tensor_runtime/include/tensor_runtime.h"
-#include "../../include/utils.h"
-
-int main(){
-
-llvm_hpvm_initTensorRt(0);
-
-int total_runs = 100;
-for (int i = 0 ; i < total_runs; i++){
-
-
-startMemTracking();
-
-int test_input_size = 5000;
-int batch_size = 5000;
-int batch_count = test_input_size / batch_size;
-float final_accuracy = 0.0;
-
-for(int i = 0; i < batch_count; i++){
-
-
-
-std::string dir_prefix = std::string("hpvm_mio_4/");
-std::string input_path = dir_prefix + std::string("input.bin");
-std::string labels_path = dir_prefix + std::string("labels.bin");
-std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
-void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
-std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
-void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
-void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,32,32,3,3);
-std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
-void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,32,1,1);
-std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
-void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,32,3,3);
-std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
-void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
-std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
-void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,64,64,3,3);
-std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
-void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,64,1,1);
-std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
-void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,1600,256);
-std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
-void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,256,1,1);
-std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
-void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,256,5);
-std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
-void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,5,1,1);
-
-
-int start = i * batch_size;
-int end = (i + 1) * batch_size;
-
-void* input = readInputBatch(input_path.c_str(),0,start,end,3,32,32);
-
-void* var_0 = ConvLayer_PROMISE(input, -2.682209e-07, 1.0000002, conv2d_1_w, -1.9097954802513122, 1.849404644250894, conv2d_1_b, -1.4970889, 0.90984344, 0, 0, 1, 1, -1, 0, 1, 0.0, 1.9360680677890976, 9);
-void* var_1 = ConvLayer_PROMISE(var_0, 0.0, 1.9360680677890976, conv2d_2_w, -0.6551046761870384, 0.5357062590122245, conv2d_2_b, -1.2897198, 0.25627556, 0, 0, 1, 1, 0, 2, 1, 0.0, 3.61756298995042, 9);
-void* var_2 = ConvLayer_PROMISE(var_1, 0.0, 3.61756298995042, conv2d_3_w, -0.479531730890274, 0.38338643845919407, conv2d_3_b, -1.9581897, 1.2684464, 0, 0, 1, 1, -1, 0, 1, 0.0, 4.717274737834942, 9);
-void* var_3 = ConvLayer_PROMISE(var_2, 0.0, 4.717274737834942, conv2d_4_w, -0.37545250764489174, 0.3687883540093907, conv2d_4_b, -0.5458527, 0.6755934, 0, 0, 1, 1, 0, 2, 1, 0.0, 6.558154335499082, 9);
-void* var_4 = FCLayer_PROMISE(var_3, 0.0, 6.558154335499082, dense_1_w, -0.19869577795267107, 0.2030584679543994, dense_1_b, -0.1697124, 0.22991186, 1, 0.0, 8.8694415378571, 9);
-void* var_5 = FCLayer_PROMISE(var_4, 0.0, 8.8694415378571, dense_2_w, -0.38784850630164147, 0.387768742352725, dense_2_b, -0.65646386, 0.75299513, -1, -23.875294536590577, 35.08045856094383, 9);
-void* var_6 = tensorSoftmax(var_5);
-
-uint32_t* labels = readLabelsBatch3(labels_path.c_str(),start,end);
-
-float accuracy = computeAccuracy3(labels, var_6);
-final_accuracy += accuracy;
-freeBatchMemory();
-
-}
-
-final_accuracy = final_accuracy / batch_count;
-dumpFinalAccuracy(final_accuracy);
-
-
-}
-
-dumpExecutionAccuracies();
-
-llvm_hpvm_cleanupTensorRt();
-
-return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/src.cc b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/src.cc
deleted file mode 100644
index 70a9a40c7878b4aeb4894acb186524870664fe09..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/data/weights/src.cc
+++ /dev/null
@@ -1,98 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <string.h>
-#include "../../tensor_runtime/include/tensor_runtime.h"
-#include "../include/utils.h"
-
-int main(){
-
- llvm_hpvm_initTensorRt(0);
-
-
- std::string dir_prefix = std::string("hpvm_mio_4/");
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,32,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,1600,256);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,256,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,256,5);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,5,1,1);
-
-
-
- startMemTracking();
-
- int test_input_size = 5000;
- int batch_size = 5000;
- int batch_count = test_input_size / batch_size;
- float final_accuracy = 0.0;
-
- for(int i = 0; i < batch_count; i++){
-
- int start = i * batch_size;
- int end = (i + 1) * batch_size;
-
- void* input = readInputBatch(input_path.c_str(),0,start,end,3,32,32);
-
- void* var_0 = tensorConvolution(input, conv2d_1_w, 0, 0, 1, 1, 1, 1);
- void* var_1 = tensorAdd(var_0, conv2d_1_b);
- void* var_2 = tensorRelu(var_1);
- void* var_3 = tensorConvolution(var_2, conv2d_2_w, 0, 0, 1, 1, 1, 1);
- void* var_4 = tensorAdd(var_3, conv2d_2_b);
- void* var_5 = tensorRelu(var_4);
- void* var_6 = tensorPooling(var_5,0,2,2,0,0,2,2);
- void* var_8 = tensorConvolution(var_6, conv2d_3_w, 0, 0, 1, 1, 1, 1);
- void* var_9 = tensorAdd(var_8, conv2d_3_b);
- void* var_10 = tensorRelu(var_9);
- void* var_11 = tensorConvolution(var_10, conv2d_4_w, 0, 0, 1, 1, 1, 1);
- void* var_12 = tensorAdd(var_11, conv2d_4_b);
- void* var_13 = tensorRelu(var_12);
- void* var_14 = tensorPooling(var_13,0,2,2,0,0,2,2);
- void* var_17 = tensorGemmGPU(var_14, dense_1_w);
- void* var_18 = tensorAdd(var_17, dense_1_b);
- void* var_19 = tensorRelu(var_18);
- void* var_21 = tensorGemmGPU(var_19, dense_2_w);
- void* var_22 = tensorAdd(var_21, dense_2_b);
- void* var_23 = tensorSoftmax(var_22);
-
- uint32_t* labels = readLabelsBatch3(labels_path.c_str(),start,end);
-
- float accuracy = computeAccuracy3(labels, var_23);
- final_accuracy += accuracy;
- freeBatchMemory();
-
- }
-
- final_accuracy = final_accuracy / batch_count;
- dumpFinalAccuracy(final_accuracy);
-
-
- llvm_hpvm_cleanupTensorRt();
-
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/src/mini_era_cv.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/src/mini_era_cv.cpp
deleted file mode 100644
index 9d7f2f76019ba5367d30ee2b00f51110d2ed04ca..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mini_era_cv/src/mini_era_cv.cpp
+++ /dev/null
@@ -1,430 +0,0 @@
-
-#include <visc.h>
-#include <utils_cpu.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(13, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 8, 2, 0);
- __visc__bindIn(var_4, 9, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
- __visc__bindIn(var_17, 22, 2, 0);
- __visc__bindIn(var_17, 23, 3, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 24, 2, 0);
- __visc__bindIn(var_18, 25, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
-
- __visc__bindOut(var_19, 0, 0, 0);
- __visc__bindOut(var_19, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../data/weights/");
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,32,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,1600,256);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,256,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,256,5);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,5,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0,500,3,32,32);
- uint32_t* labels = readLabels3(labels_path.c_str(),500);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy3(labels, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/Makefile
deleted file mode 100644
index b7f7043337175478fc78c07bb0156054a66ec0b2..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/Makefile
+++ /dev/null
@@ -1,63 +0,0 @@
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-# NOTE: can configure build directory
-HPVM_BUILD_DIR = $(LLVM_SRC_ROOT)/../build_hpvm/
-
-CC = $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-APP = mobilenet_shallow
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-TENSOR_LIB_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a
-TENSOR_AUTOTUNER_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_autotuner.a
-
-CC_FLAGS = -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_INCLUDE_PATH) -fno-exceptions -ffast-math -std=c++11 -O3
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -lpthread -lcudart -lcurand -lcudnn -lcublas -lOpenCL
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_CUDNN.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -dfg2llvm-cudnn -dfg2llvm-x86 -clearDFG
-
-
-VISC_OPTFLAGS2 = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_PROMISE.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMFuseHPVMTensorNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -hpvm-fuse -dfg2llvm-promise -dfg2llvm-x86 -clearDFG
-
-
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp
- $(CC) $(CC_FLAGS) -emit-llvm src/$(APP).cpp -S -o $(BUILD_DIR)/$(APP).ll
- #$(CC) $(CC_FLAGS) -emit-llvm src/$(APP)_promise.cpp -S -o $(BUILD_DIR)/$(APP)_promise.ll
-
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP).ll -S -o $(BUILD_DIR)/$(APP).visc.ll
- #$(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP)_promise.ll -S -o $(BUILD_DIR)/$(APP)_promise.visc.ll
- $(OPT) $(VISC_OPTFLAGS) $(BUILD_DIR)/$(APP).visc.ll -o $(BUILD_DIR)/$(APP)_cudnn.bc
- #$(OPT) $(VISC_OPTFLAGS2) $(BUILD_DIR)/$(APP)_promise.visc.ll -o $(BUILD_DIR)/$(APP)_promise.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_cudnn.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_cudnn_linked.bc
- #$(LLVM_LINK) $(BUILD_DIR)/$(APP)_promise.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_promise_linked.bc
- $(CC) $(BUILD_DIR)/$(APP)_cudnn_linked.bc $(TENSOR_LIB_DIR) -o $(BUILD_DIR)/$(APP)_cudnn_linked $(LINKER_FLAGS)
- #$(CC) $(BUILD_DIR)/$(APP)_promise_linked.bc $(TENSOR_LIB_DIR) -o $(BUILD_DIR)/$(APP)_promise_linked $(LINKER_FLAGS)
- #$(CC) $(BUILD_DIR)/$(APP)_cudnn_linked.bc $(TENSOR_AUTOTUNER_DIR) -o $(BUILD_DIR)/lenet_tune $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_confs_batch220.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_confs_batch220.txt
deleted file mode 100644
index 49958d61f5d7b6b814062b35c67acae526196c61..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_confs_batch220.txt
+++ /dev/null
@@ -1,1755 +0,0 @@
-+++++
-conf1 1 0 87.93 0
-1 gpu conv fp32 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp32 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp32 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp32 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp32 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp32 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp32 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp32 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf1 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf2 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf3 1.575539289 0 87.259995 1.005007500000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf4 1.53684197237 0 87.099998 1.2450030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf5 1.6287834325 0 86.639999 1.9350015000000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf6 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf7 1.6287834325 0 86.639999 1.9350015000000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf8 1.575539289 0 87.039993 1.335010500000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf9 1.575539289 0 87.259995 1.005007500000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf10 1.575539289 0 86.699997 1.845004500000016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 28
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf11 1.575539289 0 87.039993 1.335010500000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf12 1.575539289 0 86.68 1.875
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 29
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf13 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf14 1.51532509832 0 86.979996 1.4250060000000104
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf15 1.575539289 0 87.159996 1.1550060000000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf16 1.575539289 0 86.699997 1.845004500000016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 28
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf17 1.53684197237 0 86.819992 1.6650120000000115
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf18 1.6287834325 0 86.680008 1.874988000000009
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 22
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf19 1.53684197237 0 87.059998 1.3050030000000206
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf20 1.575539289 0 86.68 1.875
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 29
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf21 1.61623572141 0 86.0 2.8950000000000102
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf22 1.64686885056 0 86.139999 2.6850015000000056
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf23 1.53684197237 0 86.68 1.875
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf24 1.575539289 0 87.259995 1.005007500000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf25 1.59245548594 0 86.440002 2.234997
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf26 1.53684197237 0 86.720009 1.8149865000000034
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 24
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf27 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf28 1.53684197237 0 87.059998 1.3050030000000206
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf29 1.51532509832 0 86.720001 1.8149985000000157
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf30 1.61623572141 0 86.0 2.8950000000000102
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf31 1.53684197237 0 86.840004 1.6349940000000203
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf32 1.64686885056 0 86.259995 2.505007500000005
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf33 1.575539289 0 87.039993 1.335010500000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf34 1.53684197237 0 87.099998 1.2450030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf35 1.61623572141 0 86.120003 2.7149955000000148
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf36 1.61623572141 0 86.18 2.625
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf37 1.61623572141 0 86.280006 2.47499100000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf38 1.6287834325 0 86.639999 1.9350015000000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_pareto_confs_batch220.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_pareto_confs_batch220.txt
deleted file mode 100644
index 1481dbaecd58b48534e79c60dba1e221a6d42f33..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_pareto_confs_batch220.txt
+++ /dev/null
@@ -1,1395 +0,0 @@
-+++++
-conf1 1 0 87.93 0
-1 gpu conv fp32 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp32 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp32 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp32 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp32 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp32 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp32 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp32 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf1 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf2 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf3 1.575539289 0 87.259995 1.005007500000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf4 1.53684197237 0 87.099998 1.2450030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf5 1.6287834325 0 86.639999 1.9350015000000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf6 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf7 1.6287834325 0 86.639999 1.9350015000000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf8 1.575539289 0 87.039993 1.335010500000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf9 1.575539289 0 87.259995 1.005007500000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf10 1.575539289 0 87.039993 1.335010500000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf11 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf12 1.575539289 0 87.159996 1.1550060000000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf13 1.53684197237 0 86.819992 1.6650120000000115
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf14 1.6287834325 0 86.680008 1.874988000000009
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 22
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf15 1.53684197237 0 87.059998 1.3050030000000206
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf16 1.61623572141 0 86.0 2.8950000000000102
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf17 1.64686885056 0 86.139999 2.6850015000000056
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf18 1.575539289 0 87.259995 1.005007500000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf19 1.59245548594 0 86.440002 2.234997
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf20 1.5 0 87.919998 0.4100020000000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf21 1.53684197237 0 87.059998 1.3050030000000206
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf22 1.61623572141 0 86.0 2.8950000000000102
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf23 1.53684197237 0 86.840004 1.6349940000000203
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf24 1.64686885056 0 86.259995 2.505007500000005
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf25 1.575539289 0 87.039993 1.335010500000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf26 1.53684197237 0 87.099998 1.2450030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf27 1.61623572141 0 86.120003 2.7149955000000148
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf28 1.61623572141 0 86.18 2.625
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf29 1.61623572141 0 86.280006 2.47499100000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf30 1.6287834325 0 86.639999 1.9350015000000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_multi.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_multi.txt
deleted file mode 100644
index edff080259e803df3a68ec84f1a1f59aabc606af..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_multi.txt
+++ /dev/null
@@ -1,5717 +0,0 @@
-+++++
-conf1 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf2 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf3 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf4 1.91497253508 0 86.889999375 1.560000937500007
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf5 1.86955057246 0 87.236666875 1.0399996875000141
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf6 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf7 1.82459847832 0 87.2891663 0.9612505500000026
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf8 1.76108240404 0 87.29416665 0.9537500250000193
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf9 1.85810616915 0 87.267499425 0.9937508625000149
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf10 1.92713044929 0 86.775000325 1.73249951250002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf11 1.8120835937 0 86.1258333 2.7062500500000155
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf12 2.26676790856 0 86.239167575 2.536248637500016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf13 1.64686885056 0 86.433342 2.244987000000016
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf14 1.8120835937 0 86.783333525 1.7199997125000053
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf15 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf16 1.8120835937 0 86.242499475 2.5312507875000065
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf17 1.91497253508 0 86.88666565 1.5650015250000138
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf18 1.91497253508 0 86.624999825 1.9575002625000053
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf19 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf20 1.53684197237 0 86.733337 1.7949945000000014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf21 1.91497253508 0 86.063334275 2.7999985875000064
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf22 1.85810616915 0 87.24666645 1.0250003250000006
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf23 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf24 1.76108240404 0 87.311666475 0.9275002875000169
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf25 1.82459847832 0 87.3283339 0.9024991500000041
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf26 1.8794021204 0 86.918332925 1.5175006125000081
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf27 1.86955057246 0 87.284166775 0.9687498375000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf28 1.92713044929 0 86.83166565 1.6475015250000027
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf29 1.575539289 0 86.666664 1.8950040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf30 1.82459847832 0 87.3241679 0.908748150000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf31 2.44970704202 0 86.158333975 2.6574990375000027
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf32 1.89341712619 0 86.63583385 1.9412492250000142
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf33 1.92713044929 0 86.372500975 2.336248537500019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf34 1.84732414374 0 86.6783331 1.8775003500000054
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf35 1.92713044929 0 86.0374994 2.838750900000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf36 2.44970704202 0 86.150000175 2.6699997375000066
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf37 1.51532509832 0 87.200005 1.0949925000000036
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf38 2.53989918743 0 86.17916675 2.6262498750000205
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf39 1.92713044929 0 86.79166795 1.7074980750000037
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf40 2.3805433517 0 86.058333575 2.807499637500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf41 1.76108240404 0 87.299999975 0.9450000375000016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf42 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf43 1.79865007488 0 87.34833265 0.8725010250000054
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf44 1.85188328957 0 86.9683334 1.4424999000000014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf45 1.76108240404 0 87.280833725 0.9737494125000197
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf46 1.575539289 0 86.666664 1.8950040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf47 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf48 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf49 1.91497253508 0 86.857499875 1.6087501875000072
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf50 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf51 1.86955057246 0 87.275000075 0.982499887500019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf52 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf53 1.8120835937 0 86.9333332 1.4950001999999998
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf54 1.79865007488 0 87.27083365 0.98874952500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf55 1.92713044929 0 86.77000015 1.7399997750000082
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf56 1.85810616915 0 87.296666375 0.9500004375000088
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf57 1.6287834325 0 86.366669 2.3449965000000077
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf58 1.85188328957 0 86.117499325 2.7187510125000145
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf59 1.86955057246 0 87.32000105 0.9149984250000074
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf60 1.92713044929 0 86.784165925 1.7187511125000157
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf61 1.85810616915 0 87.3066651 0.9350023500000049
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf62 2.56133143265 0 86.082499875 2.7712501875000157
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf63 1.51532509832 0 87.200005 1.0949925000000036
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf64 1.92713044929 0 86.05083405 2.8187489250000013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf65 1.82459847832 0 87.3058339 0.9362491500000161
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf66 1.76108240404 0 87.304999475 0.9375007875000065
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf67 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf68 1.6287834325 0 86.366669 2.3449965000000077
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf69 1.8794021204 0 86.8958327 1.5512509500000107
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf70 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf71 1.8120835937 0 86.989999975 1.410000037500005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf72 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf73 1.91497253508 0 86.847501625 1.6237475625000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf74 1.92713044929 0 86.81583275 1.6712508750000126
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf75 1.6287834325 0 86.366669 2.3449965000000077
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf76 1.92713044929 0 86.441666825 2.2324997625000123
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf77 1.92713044929 0 86.17749975 2.628750375000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf78 2.49809300707 0 86.127499 2.70375150000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf79 1.91497253508 0 86.658334175 1.9074987375000205
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf80 1.78224422756 0 86.676666275 1.8800005875000068
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf81 2.44970704202 0 86.089999125 2.760001312500002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf82 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf83 2.41847778534 0 86.2258335 2.5562497500000205
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf84 2.44970704202 0 86.255832625 2.5112510625000155
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf85 2.37309882107 0 86.251666225 2.5175006625000194
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf86 2.3805433517 0 86.198333375 2.597499937500004
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf87 2.49809300707 0 86.043332925 2.830000612500008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf88 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf89 1.76108240404 0 87.301665775 0.9425013375000049
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf90 1.79865007488 0 87.2949999 0.9525001500000201
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf91 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf92 1.91497253508 0 86.886665975 1.5650010375000107
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf93 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf94 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf95 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf96 1.91497253508 0 86.656666625 1.9100000625000106
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf97 1.85188328957 0 86.419167025 2.2662494625000207
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf98 2.37309882107 0 86.22833235 2.552501475000007
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf99 2.44970704202 0 86.206666125 2.585000812500013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf100 2.49809300707 0 86.1725 2.636250000000011
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf101 2.43009500005 0 86.2274992 2.553751200000015
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf102 1.8794021204 0 86.936667075 1.4899993875000064
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf103 1.92713044929 0 86.216666 2.570001000000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf104 1.8120835937 0 86.196668575 2.5999971375000044
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf105 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf106 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf107 1.8120835937 0 86.568333825 2.042499262500016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf108 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf109 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf110 1.92713044929 0 86.35999975 2.35500037500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf111 1.92713044929 0 86.162498825 2.65125176250001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf112 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf113 1.92713044929 0 86.401667325 2.292499012500002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf114 1.82459847832 0 87.32833315 0.9025002750000013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf115 1.92713044929 0 86.784167825 1.7187482625000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf116 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf117 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf118 1.53684197237 0 86.733337 1.7949945000000014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf119 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf120 1.92713044929 0 86.8250003 1.6574995500000114
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf121 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf122 1.79865007488 0 87.325833725 0.9062494125000171
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf123 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf124 1.8120835937 0 86.9791668 1.426249800000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf125 1.85188328957 0 86.9275005 1.5037492500000198
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf126 1.92713044929 0 86.343332825 2.3800007625000035
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf127 2.3805433517 0 86.2050007 2.587498950000011
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf128 1.8120835937 0 86.0024996 2.8912506000000207
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_multi2.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_multi2.txt
deleted file mode 100644
index 41b4b560ff300494af75cb3b085199cf4e2d3223..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_multi2.txt
+++ /dev/null
@@ -1,7875 +0,0 @@
-+++++
-conf1 1 0 87.93 0
-1 gpu conv fp32 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp32 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp32 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp32 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp32 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp32 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp32 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp32 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf1 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf2 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf3 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf4 1.91497253508 0 86.889999375 1.560000937500007
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf5 1.86955057246 0 87.236666875 1.0399996875000141
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf6 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf7 1.82459847832 0 87.2891663 0.9612505500000026
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf8 1.76108240404 0 87.29416665 0.9537500250000193
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf9 1.85810616915 0 87.267499425 0.9937508625000149
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf10 1.92713044929 0 86.775000325 1.73249951250002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf11 1.8120835937 0 86.1258333 2.7062500500000155
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf12 2.26676790856 0 86.239167575 2.536248637500016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf13 1.64686885056 0 86.433342 2.244987000000016
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf14 1.8120835937 0 86.783333525 1.7199997125000053
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf15 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf16 1.8120835937 0 86.242499475 2.5312507875000065
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf17 1.91497253508 0 86.88666565 1.5650015250000138
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf18 1.91497253508 0 86.624999825 1.9575002625000053
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf19 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf20 1.53684197237 0 86.733337 1.7949945000000014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf21 1.91497253508 0 86.063334275 2.7999985875000064
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf22 1.85810616915 0 87.24666645 1.0250003250000006
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf23 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf24 1.76108240404 0 87.311666475 0.9275002875000169
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf25 1.82459847832 0 87.3283339 0.9024991500000041
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf26 1.8794021204 0 86.918332925 1.5175006125000081
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf27 1.86955057246 0 87.284166775 0.9687498375000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf28 1.92713044929 0 86.83166565 1.6475015250000027
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf29 1.575539289 0 86.666664 1.8950040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf30 1.82459847832 0 87.3241679 0.908748150000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf31 2.44970704202 0 86.158333975 2.6574990375000027
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf32 1.89341712619 0 86.63583385 1.9412492250000142
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf33 1.92713044929 0 86.372500975 2.336248537500019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf34 1.84732414374 0 86.6783331 1.8775003500000054
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf35 1.92713044929 0 86.0374994 2.838750900000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf36 2.44970704202 0 86.150000175 2.6699997375000066
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf37 1.51532509832 0 87.200005 1.0949925000000036
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf38 2.53989918743 0 86.17916675 2.6262498750000205
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf39 1.92713044929 0 86.79166795 1.7074980750000037
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf40 2.3805433517 0 86.058333575 2.807499637500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf41 1.76108240404 0 87.299999975 0.9450000375000016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf42 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf43 1.79865007488 0 87.34833265 0.8725010250000054
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf44 1.85188328957 0 86.9683334 1.4424999000000014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf45 1.76108240404 0 87.280833725 0.9737494125000197
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf46 1.575539289 0 86.666664 1.8950040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf47 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf48 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf49 1.91497253508 0 86.857499875 1.6087501875000072
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf50 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf51 1.86955057246 0 87.275000075 0.982499887500019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf52 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf53 1.8120835937 0 86.9333332 1.4950001999999998
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf54 1.79865007488 0 87.27083365 0.98874952500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf55 1.92713044929 0 86.77000015 1.7399997750000082
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf56 1.85810616915 0 87.296666375 0.9500004375000088
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf57 1.6287834325 0 86.366669 2.3449965000000077
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf58 1.85188328957 0 86.117499325 2.7187510125000145
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf59 1.86955057246 0 87.32000105 0.9149984250000074
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf60 1.92713044929 0 86.784165925 1.7187511125000157
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf61 1.85810616915 0 87.3066651 0.9350023500000049
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf62 2.56133143265 0 86.082499875 2.7712501875000157
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf63 1.51532509832 0 87.200005 1.0949925000000036
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf64 1.92713044929 0 86.05083405 2.8187489250000013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf65 1.82459847832 0 87.3058339 0.9362491500000161
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf66 1.76108240404 0 87.304999475 0.9375007875000065
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf67 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf68 1.6287834325 0 86.366669 2.3449965000000077
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf69 1.8794021204 0 86.8958327 1.5512509500000107
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf70 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf71 1.8120835937 0 86.989999975 1.410000037500005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf72 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf73 1.91497253508 0 86.847501625 1.6237475625000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf74 1.92713044929 0 86.81583275 1.6712508750000126
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf75 1.6287834325 0 86.366669 2.3449965000000077
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 21
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf76 1.92713044929 0 86.441666825 2.2324997625000123
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf77 1.92713044929 0 86.17749975 2.628750375000017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf78 2.49809300707 0 86.127499 2.70375150000001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf79 1.91497253508 0 86.658334175 1.9074987375000205
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf80 1.78224422756 0 86.676666275 1.8800005875000068
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf81 2.44970704202 0 86.089999125 2.760001312500002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf82 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf83 2.41847778534 0 86.2258335 2.5562497500000205
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf84 2.44970704202 0 86.255832625 2.5112510625000155
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf85 2.37309882107 0 86.251666225 2.5175006625000194
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf86 2.3805433517 0 86.198333375 2.597499937500004
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf87 2.49809300707 0 86.043332925 2.830000612500008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf88 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf89 1.76108240404 0 87.301665775 0.9425013375000049
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf90 1.79865007488 0 87.2949999 0.9525001500000201
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf91 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf92 1.91497253508 0 86.886665975 1.5650010375000107
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf93 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf94 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf95 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf96 1.91497253508 0 86.656666625 1.9100000625000106
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf97 1.85188328957 0 86.419167025 2.2662494625000207
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf98 2.37309882107 0 86.22833235 2.552501475000007
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf99 2.44970704202 0 86.206666125 2.585000812500013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf100 2.49809300707 0 86.1725 2.636250000000011
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf101 2.43009500005 0 86.2274992 2.553751200000015
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf102 1.8794021204 0 86.936667075 1.4899993875000064
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf103 1.92713044929 0 86.216666 2.570001000000005
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf104 1.8120835937 0 86.196668575 2.5999971375000044
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf105 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf106 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf107 1.8120835937 0 86.568333825 2.042499262500016
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf108 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf109 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf110 1.92713044929 0 86.35999975 2.35500037500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf111 1.92713044929 0 86.162498825 2.65125176250001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf112 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf113 1.92713044929 0 86.401667325 2.292499012500002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf114 1.82459847832 0 87.32833315 0.9025002750000013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf115 1.92713044929 0 86.784167825 1.7187482625000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf116 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf117 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf118 1.53684197237 0 86.733337 1.7949945000000014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf119 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf120 1.92713044929 0 86.8250003 1.6574995500000114
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf121 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf122 1.79865007488 0 87.325833725 0.9062494125000171
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf123 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf124 1.8120835937 0 86.9791668 1.426249800000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf125 1.85188328957 0 86.9275005 1.5037492500000198
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf126 1.92713044929 0 86.343332825 2.3800007625000035
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf127 2.3805433517 0 86.2050007 2.587498950000011
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf128 1.8120835937 0 86.0024996 2.8912506000000207
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf129 1.92713044929 0 86.818333975 1.6674990375000078
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf130 1.61623572141 0 86.0 2.8950000000000102
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf131 1.91497253508 0 86.2116658 2.5775013000000015
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf132 1.59245548594 0 86.799995 1.6950075000000169
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf133 1.91497253508 0 86.89500025 1.5524996250000171
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf134 1.78224422756 0 86.8916666 1.55750010000002
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf135 2.53989918743 0 86.14666615 2.675000775000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf136 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf137 1.92713044929 0 86.249166925 2.5212496125000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf138 1.8120835937 0 86.821665525 1.6625017125000099
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf139 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf140 1.82459847832 0 87.3533325 0.8650012500000201
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf141 1.82459847832 0 87.378332275 0.8275015875000022
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf142 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf143 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf144 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf145 1.51532509832 0 86.933327 1.4950095000000019
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf146 1.8207300425 0 86.67083325 1.8887501250000085
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf147 1.85188328957 0 86.68999935 1.8600009750000197
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf148 1.8120835937 0 86.950833225 1.4687501625000152
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf149 1.92713044929 0 86.790000575 1.70999913750002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf150 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf151 1.85188328957 0 86.42916705 2.2512494250000046
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf152 1.86955057246 0 87.285832675 0.9662509875000183
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf153 1.85188328957 0 86.089165225 2.761252162500007
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf154 1.76108240404 0 87.30166615 0.9425007750000063
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf155 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf156 1.91497253508 0 86.837498825 1.6387517625000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf157 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf158 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf159 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf160 1.92713044929 0 86.11166575 2.72750137500001
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf161 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf162 1.86955057246 0 87.292499425 0.9562508625000063
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf163 1.76108240404 0 87.304999725 0.9375004125000075
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf164 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf165 1.8794021204 0 86.90916665 1.5312500250000056
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf166 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf167 1.86955057246 0 87.23416675 1.0437498750000103
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf168 1.92713044929 0 86.08583335 2.766249975000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf169 1.8794021204 0 86.127499425 2.7037508625000157
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf170 1.91497253508 0 86.24750085 2.5237487250000186
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf171 1.53684197237 0 86.433327 2.245009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf172 1.92713044929 0 86.61416705 1.9737494250000012
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf173 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf174 1.85188328957 0 86.0566666 2.8100001000000105
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp32 1
-42 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_single.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_single.txt
deleted file mode 100644
index 26158f5d4f9d4b098243186f1dfe43795961dd66..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/autotuner_data/tuner_promise_confs_batch220_single.txt
+++ /dev/null
@@ -1,2250 +0,0 @@
-+++++
-conf1 1 0 87.93 0
-1 gpu conv fp32 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp32 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp32 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp32 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp32 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp32 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp32 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp32 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf1 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf2 1.85188328957 0 86.93166605 1.4975009250000042
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf3 1.53684197237 0 86.599998 1.9950030000000112
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 25
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf4 1.5 0 87.700005 0.6299950000000024
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf5 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf6 1.8120835937 0 86.9866658 1.4150013000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf7 1.53684197237 0 87.200005 1.0949925000000036
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf8 1.86955057246 0 87.21583265 1.0712510250000165
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf9 1.85810616915 0 87.304165475 0.9387517875000029
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf10 1.8794021204 0 86.891667625 1.5574985625000153
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf11 1.92713044929 0 86.768333375 1.742499937500014
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf12 1.76108240404 0 87.2933327 0.95500095000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf13 1.82459847832 0 87.313334375 0.9249984375000153
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf14 1.575539289 0 86.666664 1.8950040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf15 1.91497253508 0 86.847500875 1.6237486875000187
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf16 1.575539289 0 86.766663 1.745005500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf17 1.53684197237 0 86.833336 1.6449960000000061
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf18 1.8794021204 0 86.15416655 2.663750175000011
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf19 1.59245548594 0 86.5 2.1450000000000102
-1 gpu conv perf 28
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf20 1.92713044929 0 86.310000175 2.4299997375000117
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf21 1.8120835937 0 86.0424991 2.8312513500000094
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf22 1.92713044929 0 86.097501 2.748748500000019
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 29
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf23 1.8120835937 0 86.256665775 2.5100013375000074
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf24 1.88167957812 0 86.67750015 1.87874977500001
-1 gpu conv perf 29
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf25 1.61623572141 0 86.066673 2.7949905000000186
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf26 2.53989918743 0 86.17916635 2.626250475000006
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf27 1.61623572141 0 86.333336 2.394996000000006
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf28 1.8794021204 0 86.873333375 1.5849999375000081
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 5
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf29 1.91497253508 0 86.65500045 1.912499325000006
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf30 1.91497253508 0 86.86833325 1.5925001250000008
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 4
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf31 1.91497253508 0 86.270834325 2.488748512500017
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 4
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf32 1.85188328957 0 86.74000035 1.7849994750000064
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf33 1.61623572141 0 85.933327 2.995009500000002
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 24
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf34 1.61623572141 0 85.900002 3.0449970000000093
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 25
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf35 1.85188328957 0 86.0941667 2.7537499500000067
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf36 1.92713044929 0 86.5866669 2.0149996500000142
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 28
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf37 1.92713044929 0 86.339167225 2.3862491625000146
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf38 2.20742339042 0 86.2999987 2.4450019500000053
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf39 1.8794021204 0 86.205 2.587500000000013
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf40 1.92713044929 0 86.79999965 1.6950005250000046
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf41 1.86955057246 0 87.21333425 1.0749986250000063
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf42 2.58312845625 0 86.0200018 2.864997300000006
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 3
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf43 1.85188328957 0 86.948332525 1.4725012125000134
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf44 1.8120835937 0 86.98166695 1.4224995750000033
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 30
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 7
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf45 2.3805433517 0 86.05916625 2.806250625000004
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 7
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf46 2.32939142346 0 86.2841656 2.4687516000000187
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 6
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 6
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf47 1.92713044929 0 86.3524993 2.3662510500000025
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf48 2.49809300707 0 86.02583295 2.8562505750000184
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv perf 23
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 promise swing_level 5
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 promise swing_level 3
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
-+++++
-conf49 1.575539289 0 87.166664 1.1450040000000143
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv perf 23
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp16 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/quant_ranges.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/quant_ranges.txt
deleted file mode 100644
index 2b3c537c5fbe845dbf9c97e24e8841e45ed3084f..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/quant_ranges.txt
+++ /dev/null
@@ -1,8 +0,0 @@
--1.9892114 2.126797 -1.51646211648 1.64720817745 -9.86898064232 10.5609560184
-0.0 6.82138112736 -1.18343908739 1.27315966272 -9.87599849701 7.51305247974
-0.0 4.82606745577 -0.599876856983 0.681207345724 -5.63328983307 5.17789223576
-0.0 4.02646304417 -0.455596786201 0.494261391461 -5.31680394173 4.60585025024
-0.0 4.53264906311 -0.356576155901 0.338216508806 -6.1012511816 4.36305006886
-0.0 3.98747043872 -0.285027833283 0.286046403348 -4.24385170364 3.48625040674
-0.0 6.56306590176 -0.189464023232 0.190123907179 -4.93811571312 3.53836347675
-0.0 1.89083880007 -0.351403944016 0.422872786462 -0.23878151 0.26507422 -14.6308162231 27.2725212326
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/quant_ranges_rt.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/quant_ranges_rt.txt
deleted file mode 100644
index 3a83ec095ec99c762d5ff05e2749db13db47909a..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/quant_ranges_rt.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-1 -1.9892114 2.126797 -1.51646211648 1.64720817745 -9.86898064232 10.5609560184
-2 0.0 6.82138112736 -1.18343908739 1.27315966272 -9.87599849701 7.51305247974
-3 0.0 4.82606745577 -0.599876856983 0.681207345724 -5.63328983307 5.17789223576
-4 0.0 4.02646304417 -0.455596786201 0.494261391461 -5.31680394173 4.60585025024
-5 0.0 4.53264906311 -0.356576155901 0.338216508806 -6.1012511816 4.36305006886
-6 0.0 3.98747043872 -0.285027833283 0.286046403348 -4.24385170364 3.48625040674
-7 0.0 6.56306590176 -0.189464023232 0.190123907179 -4.93811571312 3.53836347675
-8 0.0 1.89083880007 -0.351403944016 0.422872786462 -0.23878151 0.26507422 -14.6308162231 27.2725212326
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/tuner_confs_base.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/tuner_confs_base.txt
deleted file mode 100644
index 501dfcc5e76d637d4e4136ac1c2486b6b4cbe639..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/data/tuner_confs_base.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-+++++
-conf1 1 0 87.59 0
-1 gpu conv fp32 1
-2 gpu batchnorm fp32 1
-3 gpu relu fp32 1
-4 gpu group_conv fp32 1
-5 gpu batchnorm fp32 1
-6 gpu relu fp32 1
-7 gpu conv fp32 1
-8 gpu batchnorm fp32 1
-9 gpu relu fp32 1
-10 gpu group_conv fp32 1
-11 gpu batchnorm fp32 1
-12 gpu relu fp32 1
-13 gpu conv fp32 1
-14 gpu batchnorm fp32 1
-15 gpu relu fp32 1
-16 gpu group_conv fp32 1
-17 gpu batchnorm fp32 1
-18 gpu relu fp32 1
-19 gpu conv fp32 1
-20 gpu batchnorm fp32 1
-21 gpu relu fp32 1
-22 gpu group_conv fp32 1
-23 gpu batchnorm fp32 1
-24 gpu relu fp32 1
-25 gpu conv fp32 1
-26 gpu batchnorm fp32 1
-27 gpu relu fp32 1
-28 gpu group_conv fp32 1
-29 gpu batchnorm fp32 1
-30 gpu relu fp32 1
-31 gpu conv fp32 1
-32 gpu batchnorm fp32 1
-33 gpu relu fp32 1
-34 gpu group_conv fp32 1
-35 gpu batchnorm fp32 1
-36 gpu relu fp32 1
-37 gpu conv fp32 1
-38 gpu batchnorm fp32 1
-39 gpu relu fp32 1
-40 gpu pool_mean fp32 1
-41 gpu mul fp32 1 add fp32 1
-42 gpu softmax fp32 1
------
-+++++
-conf2 1.5 0 87.59 0
-1 gpu conv fp16 1
-2 gpu batchnorm fp16 1
-3 gpu relu fp16 1
-4 gpu group_conv fp16 1
-5 gpu batchnorm fp16 1
-6 gpu relu fp16 1
-7 gpu conv fp16 1
-8 gpu batchnorm fp16 1
-9 gpu relu fp16 1
-10 gpu group_conv fp16 1
-11 gpu batchnorm fp16 1
-12 gpu relu fp16 1
-13 gpu conv fp16 1
-14 gpu batchnorm fp16 1
-15 gpu relu fp16 1
-16 gpu group_conv fp16 1
-17 gpu batchnorm fp16 1
-18 gpu relu fp16 1
-19 gpu conv fp16 1
-20 gpu batchnorm fp16 1
-21 gpu relu fp16 1
-22 gpu group_conv fp16 1
-23 gpu batchnorm fp16 1
-24 gpu relu fp16 1
-25 gpu conv fp16 1
-26 gpu batchnorm fp16 1
-27 gpu relu fp16 1
-28 gpu group_conv fp16 1
-29 gpu batchnorm fp16 1
-30 gpu relu fp16 1
-31 gpu conv fp16 1
-32 gpu batchnorm fp16 1
-33 gpu relu fp16 1
-34 gpu group_conv fp16 1
-35 gpu batchnorm fp16 1
-36 gpu relu fp16 1
-37 gpu conv fp16 1
-38 gpu batchnorm fp16 1
-39 gpu relu fp16 1
-40 gpu pool_mean fp16 1
-41 gpu mul fp16 1 add fp16 1
-42 gpu softmax fp32 1
------
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/src/mobilenet_shallow.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/src/mobilenet_shallow.cpp
deleted file mode 100644
index 1874e84272d180e9a9ef2c2ef2c6a09d61982415..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/src/mobilenet_shallow.cpp
+++ /dev/null
@@ -1,1225 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 32);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 64);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 128);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 128);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_27_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 256);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_28_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_29_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_30_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_31_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_32_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_33_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 256);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_34_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_35_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_36_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_37_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_38_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_39_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_mean(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_40_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_41_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_42_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* batch_normalization_1_gamma, size_t batch_normalization_1_gamma_bytes,
- void* batch_normalization_1_beta, size_t batch_normalization_1_beta_bytes,
- void* batch_normalization_1_mean, size_t batch_normalization_1_mean_bytes,
- void* batch_normalization_1_variance, size_t batch_normalization_1_variance_bytes,
- void* depthwise_conv2d_1_w, size_t depthwise_conv2d_1_w_bytes,
- void* batch_normalization_2_gamma, size_t batch_normalization_2_gamma_bytes,
- void* batch_normalization_2_beta, size_t batch_normalization_2_beta_bytes,
- void* batch_normalization_2_mean, size_t batch_normalization_2_mean_bytes,
- void* batch_normalization_2_variance, size_t batch_normalization_2_variance_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* batch_normalization_3_gamma, size_t batch_normalization_3_gamma_bytes,
- void* batch_normalization_3_beta, size_t batch_normalization_3_beta_bytes,
- void* batch_normalization_3_mean, size_t batch_normalization_3_mean_bytes,
- void* batch_normalization_3_variance, size_t batch_normalization_3_variance_bytes,
- void* depthwise_conv2d_2_w, size_t depthwise_conv2d_2_w_bytes,
- void* batch_normalization_4_gamma, size_t batch_normalization_4_gamma_bytes,
- void* batch_normalization_4_beta, size_t batch_normalization_4_beta_bytes,
- void* batch_normalization_4_mean, size_t batch_normalization_4_mean_bytes,
- void* batch_normalization_4_variance, size_t batch_normalization_4_variance_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* batch_normalization_5_gamma, size_t batch_normalization_5_gamma_bytes,
- void* batch_normalization_5_beta, size_t batch_normalization_5_beta_bytes,
- void* batch_normalization_5_mean, size_t batch_normalization_5_mean_bytes,
- void* batch_normalization_5_variance, size_t batch_normalization_5_variance_bytes,
- void* depthwise_conv2d_3_w, size_t depthwise_conv2d_3_w_bytes,
- void* batch_normalization_6_gamma, size_t batch_normalization_6_gamma_bytes,
- void* batch_normalization_6_beta, size_t batch_normalization_6_beta_bytes,
- void* batch_normalization_6_mean, size_t batch_normalization_6_mean_bytes,
- void* batch_normalization_6_variance, size_t batch_normalization_6_variance_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* batch_normalization_7_gamma, size_t batch_normalization_7_gamma_bytes,
- void* batch_normalization_7_beta, size_t batch_normalization_7_beta_bytes,
- void* batch_normalization_7_mean, size_t batch_normalization_7_mean_bytes,
- void* batch_normalization_7_variance, size_t batch_normalization_7_variance_bytes,
- void* depthwise_conv2d_4_w, size_t depthwise_conv2d_4_w_bytes,
- void* batch_normalization_8_gamma, size_t batch_normalization_8_gamma_bytes,
- void* batch_normalization_8_beta, size_t batch_normalization_8_beta_bytes,
- void* batch_normalization_8_mean, size_t batch_normalization_8_mean_bytes,
- void* batch_normalization_8_variance, size_t batch_normalization_8_variance_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* batch_normalization_9_gamma, size_t batch_normalization_9_gamma_bytes,
- void* batch_normalization_9_beta, size_t batch_normalization_9_beta_bytes,
- void* batch_normalization_9_mean, size_t batch_normalization_9_mean_bytes,
- void* batch_normalization_9_variance, size_t batch_normalization_9_variance_bytes,
- void* depthwise_conv2d_5_w, size_t depthwise_conv2d_5_w_bytes,
- void* batch_normalization_10_gamma, size_t batch_normalization_10_gamma_bytes,
- void* batch_normalization_10_beta, size_t batch_normalization_10_beta_bytes,
- void* batch_normalization_10_mean, size_t batch_normalization_10_mean_bytes,
- void* batch_normalization_10_variance, size_t batch_normalization_10_variance_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* batch_normalization_11_gamma, size_t batch_normalization_11_gamma_bytes,
- void* batch_normalization_11_beta, size_t batch_normalization_11_beta_bytes,
- void* batch_normalization_11_mean, size_t batch_normalization_11_mean_bytes,
- void* batch_normalization_11_variance, size_t batch_normalization_11_variance_bytes,
- void* depthwise_conv2d_6_w, size_t depthwise_conv2d_6_w_bytes,
- void* batch_normalization_12_gamma, size_t batch_normalization_12_gamma_bytes,
- void* batch_normalization_12_beta, size_t batch_normalization_12_beta_bytes,
- void* batch_normalization_12_mean, size_t batch_normalization_12_mean_bytes,
- void* batch_normalization_12_variance, size_t batch_normalization_12_variance_bytes,
- void* conv2d_7_w, size_t conv2d_7_w_bytes,
- void* batch_normalization_13_gamma, size_t batch_normalization_13_gamma_bytes,
- void* batch_normalization_13_beta, size_t batch_normalization_13_beta_bytes,
- void* batch_normalization_13_mean, size_t batch_normalization_13_mean_bytes,
- void* batch_normalization_13_variance, size_t batch_normalization_13_variance_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(68, input, conv2d_1_w, batch_normalization_1_gamma, batch_normalization_1_beta, batch_normalization_1_mean, batch_normalization_1_variance, depthwise_conv2d_1_w, batch_normalization_2_gamma, batch_normalization_2_beta, batch_normalization_2_mean, batch_normalization_2_variance, conv2d_2_w, batch_normalization_3_gamma, batch_normalization_3_beta, batch_normalization_3_mean, batch_normalization_3_variance, depthwise_conv2d_2_w, batch_normalization_4_gamma, batch_normalization_4_beta, batch_normalization_4_mean, batch_normalization_4_variance, conv2d_3_w, batch_normalization_5_gamma, batch_normalization_5_beta, batch_normalization_5_mean, batch_normalization_5_variance, depthwise_conv2d_3_w, batch_normalization_6_gamma, batch_normalization_6_beta, batch_normalization_6_mean, batch_normalization_6_variance, conv2d_4_w, batch_normalization_7_gamma, batch_normalization_7_beta, batch_normalization_7_mean, batch_normalization_7_variance, depthwise_conv2d_4_w, batch_normalization_8_gamma, batch_normalization_8_beta, batch_normalization_8_mean, batch_normalization_8_variance, conv2d_5_w, batch_normalization_9_gamma, batch_normalization_9_beta, batch_normalization_9_mean, batch_normalization_9_variance, depthwise_conv2d_5_w, batch_normalization_10_gamma, batch_normalization_10_beta, batch_normalization_10_mean, batch_normalization_10_variance, conv2d_6_w, batch_normalization_11_gamma, batch_normalization_11_beta, batch_normalization_11_mean, batch_normalization_11_variance, depthwise_conv2d_6_w, batch_normalization_12_gamma, batch_normalization_12_beta, batch_normalization_12_mean, batch_normalization_12_variance, conv2d_7_w, batch_normalization_13_gamma, batch_normalization_13_beta, batch_normalization_13_mean, batch_normalization_13_variance, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
- __visc__bindIn(var_1, 6, 4, 0);
- __visc__bindIn(var_1, 7, 5, 0);
- __visc__bindIn(var_1, 8, 6, 0);
- __visc__bindIn(var_1, 9, 7, 0);
- __visc__bindIn(var_1, 10, 8, 0);
- __visc__bindIn(var_1, 11, 9, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 12, 2, 0);
- __visc__bindIn(var_3, 13, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 14, 2, 0);
- __visc__bindIn(var_4, 15, 3, 0);
- __visc__bindIn(var_4, 16, 4, 0);
- __visc__bindIn(var_4, 17, 5, 0);
- __visc__bindIn(var_4, 18, 6, 0);
- __visc__bindIn(var_4, 19, 7, 0);
- __visc__bindIn(var_4, 20, 8, 0);
- __visc__bindIn(var_4, 21, 9, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
- __visc__bindIn(var_6, 22, 2, 0);
- __visc__bindIn(var_6, 23, 3, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 24, 2, 0);
- __visc__bindIn(var_7, 25, 3, 0);
- __visc__bindIn(var_7, 26, 4, 0);
- __visc__bindIn(var_7, 27, 5, 0);
- __visc__bindIn(var_7, 28, 6, 0);
- __visc__bindIn(var_7, 29, 7, 0);
- __visc__bindIn(var_7, 30, 8, 0);
- __visc__bindIn(var_7, 31, 9, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 32, 2, 0);
- __visc__bindIn(var_9, 33, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 34, 2, 0);
- __visc__bindIn(var_10, 35, 3, 0);
- __visc__bindIn(var_10, 36, 4, 0);
- __visc__bindIn(var_10, 37, 5, 0);
- __visc__bindIn(var_10, 38, 6, 0);
- __visc__bindIn(var_10, 39, 7, 0);
- __visc__bindIn(var_10, 40, 8, 0);
- __visc__bindIn(var_10, 41, 9, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 42, 2, 0);
- __visc__bindIn(var_12, 43, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 44, 2, 0);
- __visc__bindIn(var_13, 45, 3, 0);
- __visc__bindIn(var_13, 46, 4, 0);
- __visc__bindIn(var_13, 47, 5, 0);
- __visc__bindIn(var_13, 48, 6, 0);
- __visc__bindIn(var_13, 49, 7, 0);
- __visc__bindIn(var_13, 50, 8, 0);
- __visc__bindIn(var_13, 51, 9, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 52, 2, 0);
- __visc__bindIn(var_15, 53, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
- __visc__bindIn(var_16, 54, 2, 0);
- __visc__bindIn(var_16, 55, 3, 0);
- __visc__bindIn(var_16, 56, 4, 0);
- __visc__bindIn(var_16, 57, 5, 0);
- __visc__bindIn(var_16, 58, 6, 0);
- __visc__bindIn(var_16, 59, 7, 0);
- __visc__bindIn(var_16, 60, 8, 0);
- __visc__bindIn(var_16, 61, 9, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 62, 2, 0);
- __visc__bindIn(var_18, 63, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
- __visc__bindIn(var_19, 64, 2, 0);
- __visc__bindIn(var_19, 65, 3, 0);
- __visc__bindIn(var_19, 66, 4, 0);
- __visc__bindIn(var_19, 67, 5, 0);
- __visc__bindIn(var_19, 68, 6, 0);
- __visc__bindIn(var_19, 69, 7, 0);
- __visc__bindIn(var_19, 70, 8, 0);
- __visc__bindIn(var_19, 71, 9, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 72, 2, 0);
- __visc__bindIn(var_21, 73, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
- __visc__bindIn(var_22, 74, 2, 0);
- __visc__bindIn(var_22, 75, 3, 0);
- __visc__bindIn(var_22, 76, 4, 0);
- __visc__bindIn(var_22, 77, 5, 0);
- __visc__bindIn(var_22, 78, 6, 0);
- __visc__bindIn(var_22, 79, 7, 0);
- __visc__bindIn(var_22, 80, 8, 0);
- __visc__bindIn(var_22, 81, 9, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 82, 2, 0);
- __visc__bindIn(var_24, 83, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 84, 2, 0);
- __visc__bindIn(var_25, 85, 3, 0);
- __visc__bindIn(var_25, 86, 4, 0);
- __visc__bindIn(var_25, 87, 5, 0);
- __visc__bindIn(var_25, 88, 6, 0);
- __visc__bindIn(var_25, 89, 7, 0);
- __visc__bindIn(var_25, 90, 8, 0);
- __visc__bindIn(var_25, 91, 9, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- void* var_27 = __visc__createNodeND(0, var_27_node);
-
- __visc__edge(var_26, var_27, 1, 0, 0, 0);
- __visc__edge(var_26, var_27, 1, 1, 1, 0);
- __visc__bindIn(var_27, 92, 2, 0);
- __visc__bindIn(var_27, 93, 3, 0);
-
- void* var_28 = __visc__createNodeND(0, var_28_node);
-
- __visc__edge(var_27, var_28, 1, 0, 0, 0);
- __visc__edge(var_27, var_28, 1, 1, 1, 0);
- __visc__bindIn(var_28, 94, 2, 0);
- __visc__bindIn(var_28, 95, 3, 0);
- __visc__bindIn(var_28, 96, 4, 0);
- __visc__bindIn(var_28, 97, 5, 0);
- __visc__bindIn(var_28, 98, 6, 0);
- __visc__bindIn(var_28, 99, 7, 0);
- __visc__bindIn(var_28, 100, 8, 0);
- __visc__bindIn(var_28, 101, 9, 0);
-
- void* var_29 = __visc__createNodeND(0, var_29_node);
-
- __visc__edge(var_28, var_29, 1, 0, 0, 0);
- __visc__edge(var_28, var_29, 1, 1, 1, 0);
-
- void* var_30 = __visc__createNodeND(0, var_30_node);
-
- __visc__edge(var_29, var_30, 1, 0, 0, 0);
- __visc__edge(var_29, var_30, 1, 1, 1, 0);
- __visc__bindIn(var_30, 102, 2, 0);
- __visc__bindIn(var_30, 103, 3, 0);
-
- void* var_31 = __visc__createNodeND(0, var_31_node);
-
- __visc__edge(var_30, var_31, 1, 0, 0, 0);
- __visc__edge(var_30, var_31, 1, 1, 1, 0);
- __visc__bindIn(var_31, 104, 2, 0);
- __visc__bindIn(var_31, 105, 3, 0);
- __visc__bindIn(var_31, 106, 4, 0);
- __visc__bindIn(var_31, 107, 5, 0);
- __visc__bindIn(var_31, 108, 6, 0);
- __visc__bindIn(var_31, 109, 7, 0);
- __visc__bindIn(var_31, 110, 8, 0);
- __visc__bindIn(var_31, 111, 9, 0);
-
- void* var_32 = __visc__createNodeND(0, var_32_node);
-
- __visc__edge(var_31, var_32, 1, 0, 0, 0);
- __visc__edge(var_31, var_32, 1, 1, 1, 0);
-
- void* var_33 = __visc__createNodeND(0, var_33_node);
-
- __visc__edge(var_32, var_33, 1, 0, 0, 0);
- __visc__edge(var_32, var_33, 1, 1, 1, 0);
- __visc__bindIn(var_33, 112, 2, 0);
- __visc__bindIn(var_33, 113, 3, 0);
-
- void* var_34 = __visc__createNodeND(0, var_34_node);
-
- __visc__edge(var_33, var_34, 1, 0, 0, 0);
- __visc__edge(var_33, var_34, 1, 1, 1, 0);
- __visc__bindIn(var_34, 114, 2, 0);
- __visc__bindIn(var_34, 115, 3, 0);
- __visc__bindIn(var_34, 116, 4, 0);
- __visc__bindIn(var_34, 117, 5, 0);
- __visc__bindIn(var_34, 118, 6, 0);
- __visc__bindIn(var_34, 119, 7, 0);
- __visc__bindIn(var_34, 120, 8, 0);
- __visc__bindIn(var_34, 121, 9, 0);
-
- void* var_35 = __visc__createNodeND(0, var_35_node);
-
- __visc__edge(var_34, var_35, 1, 0, 0, 0);
- __visc__edge(var_34, var_35, 1, 1, 1, 0);
-
- void* var_36 = __visc__createNodeND(0, var_36_node);
-
- __visc__edge(var_35, var_36, 1, 0, 0, 0);
- __visc__edge(var_35, var_36, 1, 1, 1, 0);
- __visc__bindIn(var_36, 122, 2, 0);
- __visc__bindIn(var_36, 123, 3, 0);
-
- void* var_37 = __visc__createNodeND(0, var_37_node);
-
- __visc__edge(var_36, var_37, 1, 0, 0, 0);
- __visc__edge(var_36, var_37, 1, 1, 1, 0);
- __visc__bindIn(var_37, 124, 2, 0);
- __visc__bindIn(var_37, 125, 3, 0);
- __visc__bindIn(var_37, 126, 4, 0);
- __visc__bindIn(var_37, 127, 5, 0);
- __visc__bindIn(var_37, 128, 6, 0);
- __visc__bindIn(var_37, 129, 7, 0);
- __visc__bindIn(var_37, 130, 8, 0);
- __visc__bindIn(var_37, 131, 9, 0);
-
- void* var_38 = __visc__createNodeND(0, var_38_node);
-
- __visc__edge(var_37, var_38, 1, 0, 0, 0);
- __visc__edge(var_37, var_38, 1, 1, 1, 0);
-
- void* var_39 = __visc__createNodeND(0, var_39_node);
-
- __visc__edge(var_38, var_39, 1, 0, 0, 0);
- __visc__edge(var_38, var_39, 1, 1, 1, 0);
-
- void* var_40 = __visc__createNodeND(0, var_40_node);
-
- __visc__edge(var_39, var_40, 1, 0, 0, 0);
- __visc__edge(var_39, var_40, 1, 1, 1, 0);
- __visc__bindIn(var_40, 132, 2, 0);
- __visc__bindIn(var_40, 133, 3, 0);
-
- void* var_41 = __visc__createNodeND(0, var_41_node);
-
- __visc__edge(var_40, var_41, 1, 0, 0, 0);
- __visc__edge(var_40, var_41, 1, 1, 1, 0);
- __visc__bindIn(var_41, 134, 2, 0);
- __visc__bindIn(var_41, 135, 3, 0);
-
- void* var_42 = __visc__createNodeND(0, var_42_node);
-
- __visc__edge(var_41, var_42, 1, 0, 0, 0);
- __visc__edge(var_41, var_42, 1, 1, 1, 0);
-
- __visc__bindOut(var_42, 0, 0, 0);
- __visc__bindOut(var_42, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* batch_normalization_1_gamma;
- size_t batch_normalization_1_gamma_bytes;
- void* batch_normalization_1_beta;
- size_t batch_normalization_1_beta_bytes;
- void* batch_normalization_1_mean;
- size_t batch_normalization_1_mean_bytes;
- void* batch_normalization_1_variance;
- size_t batch_normalization_1_variance_bytes;
- void* depthwise_conv2d_1_w;
- size_t depthwise_conv2d_1_w_bytes;
- void* batch_normalization_2_gamma;
- size_t batch_normalization_2_gamma_bytes;
- void* batch_normalization_2_beta;
- size_t batch_normalization_2_beta_bytes;
- void* batch_normalization_2_mean;
- size_t batch_normalization_2_mean_bytes;
- void* batch_normalization_2_variance;
- size_t batch_normalization_2_variance_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* batch_normalization_3_gamma;
- size_t batch_normalization_3_gamma_bytes;
- void* batch_normalization_3_beta;
- size_t batch_normalization_3_beta_bytes;
- void* batch_normalization_3_mean;
- size_t batch_normalization_3_mean_bytes;
- void* batch_normalization_3_variance;
- size_t batch_normalization_3_variance_bytes;
- void* depthwise_conv2d_2_w;
- size_t depthwise_conv2d_2_w_bytes;
- void* batch_normalization_4_gamma;
- size_t batch_normalization_4_gamma_bytes;
- void* batch_normalization_4_beta;
- size_t batch_normalization_4_beta_bytes;
- void* batch_normalization_4_mean;
- size_t batch_normalization_4_mean_bytes;
- void* batch_normalization_4_variance;
- size_t batch_normalization_4_variance_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* batch_normalization_5_gamma;
- size_t batch_normalization_5_gamma_bytes;
- void* batch_normalization_5_beta;
- size_t batch_normalization_5_beta_bytes;
- void* batch_normalization_5_mean;
- size_t batch_normalization_5_mean_bytes;
- void* batch_normalization_5_variance;
- size_t batch_normalization_5_variance_bytes;
- void* depthwise_conv2d_3_w;
- size_t depthwise_conv2d_3_w_bytes;
- void* batch_normalization_6_gamma;
- size_t batch_normalization_6_gamma_bytes;
- void* batch_normalization_6_beta;
- size_t batch_normalization_6_beta_bytes;
- void* batch_normalization_6_mean;
- size_t batch_normalization_6_mean_bytes;
- void* batch_normalization_6_variance;
- size_t batch_normalization_6_variance_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* batch_normalization_7_gamma;
- size_t batch_normalization_7_gamma_bytes;
- void* batch_normalization_7_beta;
- size_t batch_normalization_7_beta_bytes;
- void* batch_normalization_7_mean;
- size_t batch_normalization_7_mean_bytes;
- void* batch_normalization_7_variance;
- size_t batch_normalization_7_variance_bytes;
- void* depthwise_conv2d_4_w;
- size_t depthwise_conv2d_4_w_bytes;
- void* batch_normalization_8_gamma;
- size_t batch_normalization_8_gamma_bytes;
- void* batch_normalization_8_beta;
- size_t batch_normalization_8_beta_bytes;
- void* batch_normalization_8_mean;
- size_t batch_normalization_8_mean_bytes;
- void* batch_normalization_8_variance;
- size_t batch_normalization_8_variance_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* batch_normalization_9_gamma;
- size_t batch_normalization_9_gamma_bytes;
- void* batch_normalization_9_beta;
- size_t batch_normalization_9_beta_bytes;
- void* batch_normalization_9_mean;
- size_t batch_normalization_9_mean_bytes;
- void* batch_normalization_9_variance;
- size_t batch_normalization_9_variance_bytes;
- void* depthwise_conv2d_5_w;
- size_t depthwise_conv2d_5_w_bytes;
- void* batch_normalization_10_gamma;
- size_t batch_normalization_10_gamma_bytes;
- void* batch_normalization_10_beta;
- size_t batch_normalization_10_beta_bytes;
- void* batch_normalization_10_mean;
- size_t batch_normalization_10_mean_bytes;
- void* batch_normalization_10_variance;
- size_t batch_normalization_10_variance_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* batch_normalization_11_gamma;
- size_t batch_normalization_11_gamma_bytes;
- void* batch_normalization_11_beta;
- size_t batch_normalization_11_beta_bytes;
- void* batch_normalization_11_mean;
- size_t batch_normalization_11_mean_bytes;
- void* batch_normalization_11_variance;
- size_t batch_normalization_11_variance_bytes;
- void* depthwise_conv2d_6_w;
- size_t depthwise_conv2d_6_w_bytes;
- void* batch_normalization_12_gamma;
- size_t batch_normalization_12_gamma_bytes;
- void* batch_normalization_12_beta;
- size_t batch_normalization_12_beta_bytes;
- void* batch_normalization_12_mean;
- size_t batch_normalization_12_mean_bytes;
- void* batch_normalization_12_variance;
- size_t batch_normalization_12_variance_bytes;
- void* conv2d_7_w;
- size_t conv2d_7_w_bytes;
- void* batch_normalization_13_gamma;
- size_t batch_normalization_13_gamma_bytes;
- void* batch_normalization_13_beta;
- size_t batch_normalization_13_beta_bytes;
- void* batch_normalization_13_mean;
- size_t batch_normalization_13_mean_bytes;
- void* batch_normalization_13_variance;
- size_t batch_normalization_13_variance_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/mobilenet_shallow/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
- std::string batch_normalization_1_gamma_path = dir_prefix + std::string("batch_normalization_1_gamma.bin");
- void* batch_normalization_1_gamma = readTrainedWeights(batch_normalization_1_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_beta_path = dir_prefix + std::string("batch_normalization_1_beta.bin");
- void* batch_normalization_1_beta = readTrainedWeights(batch_normalization_1_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_mean_path = dir_prefix + std::string("batch_normalization_1_mean.bin");
- void* batch_normalization_1_mean = readTrainedWeights(batch_normalization_1_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_variance_path = dir_prefix + std::string("batch_normalization_1_variance.bin");
- void* batch_normalization_1_variance = readTrainedWeights(batch_normalization_1_variance_path.c_str(), 0,1,32,1,1);
- std::string depthwise_conv2d_1_w_path = dir_prefix + std::string("depthwise_conv2d_1_w.bin");
- void* depthwise_conv2d_1_w = readTrainedWeights(depthwise_conv2d_1_w_path.c_str(), 0,32,1,3,3);
- std::string batch_normalization_2_gamma_path = dir_prefix + std::string("batch_normalization_2_gamma.bin");
- void* batch_normalization_2_gamma = readTrainedWeights(batch_normalization_2_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_beta_path = dir_prefix + std::string("batch_normalization_2_beta.bin");
- void* batch_normalization_2_beta = readTrainedWeights(batch_normalization_2_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_mean_path = dir_prefix + std::string("batch_normalization_2_mean.bin");
- void* batch_normalization_2_mean = readTrainedWeights(batch_normalization_2_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_variance_path = dir_prefix + std::string("batch_normalization_2_variance.bin");
- void* batch_normalization_2_variance = readTrainedWeights(batch_normalization_2_variance_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,1,1);
- std::string batch_normalization_3_gamma_path = dir_prefix + std::string("batch_normalization_3_gamma.bin");
- void* batch_normalization_3_gamma = readTrainedWeights(batch_normalization_3_gamma_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_beta_path = dir_prefix + std::string("batch_normalization_3_beta.bin");
- void* batch_normalization_3_beta = readTrainedWeights(batch_normalization_3_beta_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_mean_path = dir_prefix + std::string("batch_normalization_3_mean.bin");
- void* batch_normalization_3_mean = readTrainedWeights(batch_normalization_3_mean_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_variance_path = dir_prefix + std::string("batch_normalization_3_variance.bin");
- void* batch_normalization_3_variance = readTrainedWeights(batch_normalization_3_variance_path.c_str(), 0,1,64,1,1);
- std::string depthwise_conv2d_2_w_path = dir_prefix + std::string("depthwise_conv2d_2_w.bin");
- void* depthwise_conv2d_2_w = readTrainedWeights(depthwise_conv2d_2_w_path.c_str(), 0,64,1,3,3);
- std::string batch_normalization_4_gamma_path = dir_prefix + std::string("batch_normalization_4_gamma.bin");
- void* batch_normalization_4_gamma = readTrainedWeights(batch_normalization_4_gamma_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_beta_path = dir_prefix + std::string("batch_normalization_4_beta.bin");
- void* batch_normalization_4_beta = readTrainedWeights(batch_normalization_4_beta_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_mean_path = dir_prefix + std::string("batch_normalization_4_mean.bin");
- void* batch_normalization_4_mean = readTrainedWeights(batch_normalization_4_mean_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_variance_path = dir_prefix + std::string("batch_normalization_4_variance.bin");
- void* batch_normalization_4_variance = readTrainedWeights(batch_normalization_4_variance_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,128,64,1,1);
- std::string batch_normalization_5_gamma_path = dir_prefix + std::string("batch_normalization_5_gamma.bin");
- void* batch_normalization_5_gamma = readTrainedWeights(batch_normalization_5_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_beta_path = dir_prefix + std::string("batch_normalization_5_beta.bin");
- void* batch_normalization_5_beta = readTrainedWeights(batch_normalization_5_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_mean_path = dir_prefix + std::string("batch_normalization_5_mean.bin");
- void* batch_normalization_5_mean = readTrainedWeights(batch_normalization_5_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_variance_path = dir_prefix + std::string("batch_normalization_5_variance.bin");
- void* batch_normalization_5_variance = readTrainedWeights(batch_normalization_5_variance_path.c_str(), 0,1,128,1,1);
- std::string depthwise_conv2d_3_w_path = dir_prefix + std::string("depthwise_conv2d_3_w.bin");
- void* depthwise_conv2d_3_w = readTrainedWeights(depthwise_conv2d_3_w_path.c_str(), 0,128,1,3,3);
- std::string batch_normalization_6_gamma_path = dir_prefix + std::string("batch_normalization_6_gamma.bin");
- void* batch_normalization_6_gamma = readTrainedWeights(batch_normalization_6_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_beta_path = dir_prefix + std::string("batch_normalization_6_beta.bin");
- void* batch_normalization_6_beta = readTrainedWeights(batch_normalization_6_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_mean_path = dir_prefix + std::string("batch_normalization_6_mean.bin");
- void* batch_normalization_6_mean = readTrainedWeights(batch_normalization_6_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_variance_path = dir_prefix + std::string("batch_normalization_6_variance.bin");
- void* batch_normalization_6_variance = readTrainedWeights(batch_normalization_6_variance_path.c_str(), 0,1,128,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,128,128,1,1);
- std::string batch_normalization_7_gamma_path = dir_prefix + std::string("batch_normalization_7_gamma.bin");
- void* batch_normalization_7_gamma = readTrainedWeights(batch_normalization_7_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_beta_path = dir_prefix + std::string("batch_normalization_7_beta.bin");
- void* batch_normalization_7_beta = readTrainedWeights(batch_normalization_7_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_mean_path = dir_prefix + std::string("batch_normalization_7_mean.bin");
- void* batch_normalization_7_mean = readTrainedWeights(batch_normalization_7_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_variance_path = dir_prefix + std::string("batch_normalization_7_variance.bin");
- void* batch_normalization_7_variance = readTrainedWeights(batch_normalization_7_variance_path.c_str(), 0,1,128,1,1);
- std::string depthwise_conv2d_4_w_path = dir_prefix + std::string("depthwise_conv2d_4_w.bin");
- void* depthwise_conv2d_4_w = readTrainedWeights(depthwise_conv2d_4_w_path.c_str(), 0,128,1,3,3);
- std::string batch_normalization_8_gamma_path = dir_prefix + std::string("batch_normalization_8_gamma.bin");
- void* batch_normalization_8_gamma = readTrainedWeights(batch_normalization_8_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_beta_path = dir_prefix + std::string("batch_normalization_8_beta.bin");
- void* batch_normalization_8_beta = readTrainedWeights(batch_normalization_8_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_mean_path = dir_prefix + std::string("batch_normalization_8_mean.bin");
- void* batch_normalization_8_mean = readTrainedWeights(batch_normalization_8_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_variance_path = dir_prefix + std::string("batch_normalization_8_variance.bin");
- void* batch_normalization_8_variance = readTrainedWeights(batch_normalization_8_variance_path.c_str(), 0,1,128,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,128,1,1);
- std::string batch_normalization_9_gamma_path = dir_prefix + std::string("batch_normalization_9_gamma.bin");
- void* batch_normalization_9_gamma = readTrainedWeights(batch_normalization_9_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_beta_path = dir_prefix + std::string("batch_normalization_9_beta.bin");
- void* batch_normalization_9_beta = readTrainedWeights(batch_normalization_9_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_mean_path = dir_prefix + std::string("batch_normalization_9_mean.bin");
- void* batch_normalization_9_mean = readTrainedWeights(batch_normalization_9_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_variance_path = dir_prefix + std::string("batch_normalization_9_variance.bin");
- void* batch_normalization_9_variance = readTrainedWeights(batch_normalization_9_variance_path.c_str(), 0,1,256,1,1);
- std::string depthwise_conv2d_5_w_path = dir_prefix + std::string("depthwise_conv2d_5_w.bin");
- void* depthwise_conv2d_5_w = readTrainedWeights(depthwise_conv2d_5_w_path.c_str(), 0,256,1,3,3);
- std::string batch_normalization_10_gamma_path = dir_prefix + std::string("batch_normalization_10_gamma.bin");
- void* batch_normalization_10_gamma = readTrainedWeights(batch_normalization_10_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_beta_path = dir_prefix + std::string("batch_normalization_10_beta.bin");
- void* batch_normalization_10_beta = readTrainedWeights(batch_normalization_10_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_mean_path = dir_prefix + std::string("batch_normalization_10_mean.bin");
- void* batch_normalization_10_mean = readTrainedWeights(batch_normalization_10_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_variance_path = dir_prefix + std::string("batch_normalization_10_variance.bin");
- void* batch_normalization_10_variance = readTrainedWeights(batch_normalization_10_variance_path.c_str(), 0,1,256,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,256,256,1,1);
- std::string batch_normalization_11_gamma_path = dir_prefix + std::string("batch_normalization_11_gamma.bin");
- void* batch_normalization_11_gamma = readTrainedWeights(batch_normalization_11_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_beta_path = dir_prefix + std::string("batch_normalization_11_beta.bin");
- void* batch_normalization_11_beta = readTrainedWeights(batch_normalization_11_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_mean_path = dir_prefix + std::string("batch_normalization_11_mean.bin");
- void* batch_normalization_11_mean = readTrainedWeights(batch_normalization_11_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_variance_path = dir_prefix + std::string("batch_normalization_11_variance.bin");
- void* batch_normalization_11_variance = readTrainedWeights(batch_normalization_11_variance_path.c_str(), 0,1,256,1,1);
- std::string depthwise_conv2d_6_w_path = dir_prefix + std::string("depthwise_conv2d_6_w.bin");
- void* depthwise_conv2d_6_w = readTrainedWeights(depthwise_conv2d_6_w_path.c_str(), 0,256,1,3,3);
- std::string batch_normalization_12_gamma_path = dir_prefix + std::string("batch_normalization_12_gamma.bin");
- void* batch_normalization_12_gamma = readTrainedWeights(batch_normalization_12_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_beta_path = dir_prefix + std::string("batch_normalization_12_beta.bin");
- void* batch_normalization_12_beta = readTrainedWeights(batch_normalization_12_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_mean_path = dir_prefix + std::string("batch_normalization_12_mean.bin");
- void* batch_normalization_12_mean = readTrainedWeights(batch_normalization_12_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_variance_path = dir_prefix + std::string("batch_normalization_12_variance.bin");
- void* batch_normalization_12_variance = readTrainedWeights(batch_normalization_12_variance_path.c_str(), 0,1,256,1,1);
- std::string conv2d_7_w_path = dir_prefix + std::string("conv2d_7_w.bin");
- void* conv2d_7_w = readTrainedWeights(conv2d_7_w_path.c_str(), 0,512,256,1,1);
- std::string batch_normalization_13_gamma_path = dir_prefix + std::string("batch_normalization_13_gamma.bin");
- void* batch_normalization_13_gamma = readTrainedWeights(batch_normalization_13_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_beta_path = dir_prefix + std::string("batch_normalization_13_beta.bin");
- void* batch_normalization_13_beta = readTrainedWeights(batch_normalization_13_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_mean_path = dir_prefix + std::string("batch_normalization_13_mean.bin");
- void* batch_normalization_13_mean = readTrainedWeights(batch_normalization_13_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_variance_path = dir_prefix + std::string("batch_normalization_13_variance.bin");
- void* batch_normalization_13_variance = readTrainedWeights(batch_normalization_13_variance_path.c_str(), 0,1,512,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,2048,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0, 5000,3,32,32);
- uint8_t* labels = readLabels(labels_path.c_str(), 5000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->batch_normalization_1_gamma = batch_normalization_1_gamma;
- args->batch_normalization_1_gamma_bytes = 0;
- args->batch_normalization_1_beta = batch_normalization_1_beta;
- args->batch_normalization_1_beta_bytes = 0;
- args->batch_normalization_1_mean = batch_normalization_1_mean;
- args->batch_normalization_1_mean_bytes = 0;
- args->batch_normalization_1_variance = batch_normalization_1_variance;
- args->batch_normalization_1_variance_bytes = 0;
- args->depthwise_conv2d_1_w = depthwise_conv2d_1_w;
- args->depthwise_conv2d_1_w_bytes = 0;
- args->batch_normalization_2_gamma = batch_normalization_2_gamma;
- args->batch_normalization_2_gamma_bytes = 0;
- args->batch_normalization_2_beta = batch_normalization_2_beta;
- args->batch_normalization_2_beta_bytes = 0;
- args->batch_normalization_2_mean = batch_normalization_2_mean;
- args->batch_normalization_2_mean_bytes = 0;
- args->batch_normalization_2_variance = batch_normalization_2_variance;
- args->batch_normalization_2_variance_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->batch_normalization_3_gamma = batch_normalization_3_gamma;
- args->batch_normalization_3_gamma_bytes = 0;
- args->batch_normalization_3_beta = batch_normalization_3_beta;
- args->batch_normalization_3_beta_bytes = 0;
- args->batch_normalization_3_mean = batch_normalization_3_mean;
- args->batch_normalization_3_mean_bytes = 0;
- args->batch_normalization_3_variance = batch_normalization_3_variance;
- args->batch_normalization_3_variance_bytes = 0;
- args->depthwise_conv2d_2_w = depthwise_conv2d_2_w;
- args->depthwise_conv2d_2_w_bytes = 0;
- args->batch_normalization_4_gamma = batch_normalization_4_gamma;
- args->batch_normalization_4_gamma_bytes = 0;
- args->batch_normalization_4_beta = batch_normalization_4_beta;
- args->batch_normalization_4_beta_bytes = 0;
- args->batch_normalization_4_mean = batch_normalization_4_mean;
- args->batch_normalization_4_mean_bytes = 0;
- args->batch_normalization_4_variance = batch_normalization_4_variance;
- args->batch_normalization_4_variance_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->batch_normalization_5_gamma = batch_normalization_5_gamma;
- args->batch_normalization_5_gamma_bytes = 0;
- args->batch_normalization_5_beta = batch_normalization_5_beta;
- args->batch_normalization_5_beta_bytes = 0;
- args->batch_normalization_5_mean = batch_normalization_5_mean;
- args->batch_normalization_5_mean_bytes = 0;
- args->batch_normalization_5_variance = batch_normalization_5_variance;
- args->batch_normalization_5_variance_bytes = 0;
- args->depthwise_conv2d_3_w = depthwise_conv2d_3_w;
- args->depthwise_conv2d_3_w_bytes = 0;
- args->batch_normalization_6_gamma = batch_normalization_6_gamma;
- args->batch_normalization_6_gamma_bytes = 0;
- args->batch_normalization_6_beta = batch_normalization_6_beta;
- args->batch_normalization_6_beta_bytes = 0;
- args->batch_normalization_6_mean = batch_normalization_6_mean;
- args->batch_normalization_6_mean_bytes = 0;
- args->batch_normalization_6_variance = batch_normalization_6_variance;
- args->batch_normalization_6_variance_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->batch_normalization_7_gamma = batch_normalization_7_gamma;
- args->batch_normalization_7_gamma_bytes = 0;
- args->batch_normalization_7_beta = batch_normalization_7_beta;
- args->batch_normalization_7_beta_bytes = 0;
- args->batch_normalization_7_mean = batch_normalization_7_mean;
- args->batch_normalization_7_mean_bytes = 0;
- args->batch_normalization_7_variance = batch_normalization_7_variance;
- args->batch_normalization_7_variance_bytes = 0;
- args->depthwise_conv2d_4_w = depthwise_conv2d_4_w;
- args->depthwise_conv2d_4_w_bytes = 0;
- args->batch_normalization_8_gamma = batch_normalization_8_gamma;
- args->batch_normalization_8_gamma_bytes = 0;
- args->batch_normalization_8_beta = batch_normalization_8_beta;
- args->batch_normalization_8_beta_bytes = 0;
- args->batch_normalization_8_mean = batch_normalization_8_mean;
- args->batch_normalization_8_mean_bytes = 0;
- args->batch_normalization_8_variance = batch_normalization_8_variance;
- args->batch_normalization_8_variance_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->batch_normalization_9_gamma = batch_normalization_9_gamma;
- args->batch_normalization_9_gamma_bytes = 0;
- args->batch_normalization_9_beta = batch_normalization_9_beta;
- args->batch_normalization_9_beta_bytes = 0;
- args->batch_normalization_9_mean = batch_normalization_9_mean;
- args->batch_normalization_9_mean_bytes = 0;
- args->batch_normalization_9_variance = batch_normalization_9_variance;
- args->batch_normalization_9_variance_bytes = 0;
- args->depthwise_conv2d_5_w = depthwise_conv2d_5_w;
- args->depthwise_conv2d_5_w_bytes = 0;
- args->batch_normalization_10_gamma = batch_normalization_10_gamma;
- args->batch_normalization_10_gamma_bytes = 0;
- args->batch_normalization_10_beta = batch_normalization_10_beta;
- args->batch_normalization_10_beta_bytes = 0;
- args->batch_normalization_10_mean = batch_normalization_10_mean;
- args->batch_normalization_10_mean_bytes = 0;
- args->batch_normalization_10_variance = batch_normalization_10_variance;
- args->batch_normalization_10_variance_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->batch_normalization_11_gamma = batch_normalization_11_gamma;
- args->batch_normalization_11_gamma_bytes = 0;
- args->batch_normalization_11_beta = batch_normalization_11_beta;
- args->batch_normalization_11_beta_bytes = 0;
- args->batch_normalization_11_mean = batch_normalization_11_mean;
- args->batch_normalization_11_mean_bytes = 0;
- args->batch_normalization_11_variance = batch_normalization_11_variance;
- args->batch_normalization_11_variance_bytes = 0;
- args->depthwise_conv2d_6_w = depthwise_conv2d_6_w;
- args->depthwise_conv2d_6_w_bytes = 0;
- args->batch_normalization_12_gamma = batch_normalization_12_gamma;
- args->batch_normalization_12_gamma_bytes = 0;
- args->batch_normalization_12_beta = batch_normalization_12_beta;
- args->batch_normalization_12_beta_bytes = 0;
- args->batch_normalization_12_mean = batch_normalization_12_mean;
- args->batch_normalization_12_mean_bytes = 0;
- args->batch_normalization_12_variance = batch_normalization_12_variance;
- args->batch_normalization_12_variance_bytes = 0;
- args->conv2d_7_w = conv2d_7_w;
- args->conv2d_7_w_bytes = 0;
- args->batch_normalization_13_gamma = batch_normalization_13_gamma;
- args->batch_normalization_13_gamma_bytes = 0;
- args->batch_normalization_13_beta = batch_normalization_13_beta;
- args->batch_normalization_13_beta_bytes = 0;
- args->batch_normalization_13_mean = batch_normalization_13_mean;
- args->batch_normalization_13_mean_bytes = 0;
- args->batch_normalization_13_variance = batch_normalization_13_variance;
- args->batch_normalization_13_variance_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 5000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/src/mobilenet_shallow_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/src/mobilenet_shallow_promise.cpp
deleted file mode 100644
index 361fa0c1c44151cbefc98b6c983d17303d254eef..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/mobilenet_shallow/src/mobilenet_shallow_promise.cpp
+++ /dev/null
@@ -1,1225 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 32);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 64);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 128);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 128);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_27_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 256);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_28_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_29_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_30_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_31_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_32_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_33_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 256);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_34_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_35_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_36_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_37_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_38_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_39_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_mean(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_40_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_41_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_42_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* batch_normalization_1_gamma, size_t batch_normalization_1_gamma_bytes,
- void* batch_normalization_1_beta, size_t batch_normalization_1_beta_bytes,
- void* batch_normalization_1_mean, size_t batch_normalization_1_mean_bytes,
- void* batch_normalization_1_variance, size_t batch_normalization_1_variance_bytes,
- void* depthwise_conv2d_1_w, size_t depthwise_conv2d_1_w_bytes,
- void* batch_normalization_2_gamma, size_t batch_normalization_2_gamma_bytes,
- void* batch_normalization_2_beta, size_t batch_normalization_2_beta_bytes,
- void* batch_normalization_2_mean, size_t batch_normalization_2_mean_bytes,
- void* batch_normalization_2_variance, size_t batch_normalization_2_variance_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* batch_normalization_3_gamma, size_t batch_normalization_3_gamma_bytes,
- void* batch_normalization_3_beta, size_t batch_normalization_3_beta_bytes,
- void* batch_normalization_3_mean, size_t batch_normalization_3_mean_bytes,
- void* batch_normalization_3_variance, size_t batch_normalization_3_variance_bytes,
- void* depthwise_conv2d_2_w, size_t depthwise_conv2d_2_w_bytes,
- void* batch_normalization_4_gamma, size_t batch_normalization_4_gamma_bytes,
- void* batch_normalization_4_beta, size_t batch_normalization_4_beta_bytes,
- void* batch_normalization_4_mean, size_t batch_normalization_4_mean_bytes,
- void* batch_normalization_4_variance, size_t batch_normalization_4_variance_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* batch_normalization_5_gamma, size_t batch_normalization_5_gamma_bytes,
- void* batch_normalization_5_beta, size_t batch_normalization_5_beta_bytes,
- void* batch_normalization_5_mean, size_t batch_normalization_5_mean_bytes,
- void* batch_normalization_5_variance, size_t batch_normalization_5_variance_bytes,
- void* depthwise_conv2d_3_w, size_t depthwise_conv2d_3_w_bytes,
- void* batch_normalization_6_gamma, size_t batch_normalization_6_gamma_bytes,
- void* batch_normalization_6_beta, size_t batch_normalization_6_beta_bytes,
- void* batch_normalization_6_mean, size_t batch_normalization_6_mean_bytes,
- void* batch_normalization_6_variance, size_t batch_normalization_6_variance_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* batch_normalization_7_gamma, size_t batch_normalization_7_gamma_bytes,
- void* batch_normalization_7_beta, size_t batch_normalization_7_beta_bytes,
- void* batch_normalization_7_mean, size_t batch_normalization_7_mean_bytes,
- void* batch_normalization_7_variance, size_t batch_normalization_7_variance_bytes,
- void* depthwise_conv2d_4_w, size_t depthwise_conv2d_4_w_bytes,
- void* batch_normalization_8_gamma, size_t batch_normalization_8_gamma_bytes,
- void* batch_normalization_8_beta, size_t batch_normalization_8_beta_bytes,
- void* batch_normalization_8_mean, size_t batch_normalization_8_mean_bytes,
- void* batch_normalization_8_variance, size_t batch_normalization_8_variance_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* batch_normalization_9_gamma, size_t batch_normalization_9_gamma_bytes,
- void* batch_normalization_9_beta, size_t batch_normalization_9_beta_bytes,
- void* batch_normalization_9_mean, size_t batch_normalization_9_mean_bytes,
- void* batch_normalization_9_variance, size_t batch_normalization_9_variance_bytes,
- void* depthwise_conv2d_5_w, size_t depthwise_conv2d_5_w_bytes,
- void* batch_normalization_10_gamma, size_t batch_normalization_10_gamma_bytes,
- void* batch_normalization_10_beta, size_t batch_normalization_10_beta_bytes,
- void* batch_normalization_10_mean, size_t batch_normalization_10_mean_bytes,
- void* batch_normalization_10_variance, size_t batch_normalization_10_variance_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* batch_normalization_11_gamma, size_t batch_normalization_11_gamma_bytes,
- void* batch_normalization_11_beta, size_t batch_normalization_11_beta_bytes,
- void* batch_normalization_11_mean, size_t batch_normalization_11_mean_bytes,
- void* batch_normalization_11_variance, size_t batch_normalization_11_variance_bytes,
- void* depthwise_conv2d_6_w, size_t depthwise_conv2d_6_w_bytes,
- void* batch_normalization_12_gamma, size_t batch_normalization_12_gamma_bytes,
- void* batch_normalization_12_beta, size_t batch_normalization_12_beta_bytes,
- void* batch_normalization_12_mean, size_t batch_normalization_12_mean_bytes,
- void* batch_normalization_12_variance, size_t batch_normalization_12_variance_bytes,
- void* conv2d_7_w, size_t conv2d_7_w_bytes,
- void* batch_normalization_13_gamma, size_t batch_normalization_13_gamma_bytes,
- void* batch_normalization_13_beta, size_t batch_normalization_13_beta_bytes,
- void* batch_normalization_13_mean, size_t batch_normalization_13_mean_bytes,
- void* batch_normalization_13_variance, size_t batch_normalization_13_variance_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(68, input, conv2d_1_w, batch_normalization_1_gamma, batch_normalization_1_beta, batch_normalization_1_mean, batch_normalization_1_variance, depthwise_conv2d_1_w, batch_normalization_2_gamma, batch_normalization_2_beta, batch_normalization_2_mean, batch_normalization_2_variance, conv2d_2_w, batch_normalization_3_gamma, batch_normalization_3_beta, batch_normalization_3_mean, batch_normalization_3_variance, depthwise_conv2d_2_w, batch_normalization_4_gamma, batch_normalization_4_beta, batch_normalization_4_mean, batch_normalization_4_variance, conv2d_3_w, batch_normalization_5_gamma, batch_normalization_5_beta, batch_normalization_5_mean, batch_normalization_5_variance, depthwise_conv2d_3_w, batch_normalization_6_gamma, batch_normalization_6_beta, batch_normalization_6_mean, batch_normalization_6_variance, conv2d_4_w, batch_normalization_7_gamma, batch_normalization_7_beta, batch_normalization_7_mean, batch_normalization_7_variance, depthwise_conv2d_4_w, batch_normalization_8_gamma, batch_normalization_8_beta, batch_normalization_8_mean, batch_normalization_8_variance, conv2d_5_w, batch_normalization_9_gamma, batch_normalization_9_beta, batch_normalization_9_mean, batch_normalization_9_variance, depthwise_conv2d_5_w, batch_normalization_10_gamma, batch_normalization_10_beta, batch_normalization_10_mean, batch_normalization_10_variance, conv2d_6_w, batch_normalization_11_gamma, batch_normalization_11_beta, batch_normalization_11_mean, batch_normalization_11_variance, depthwise_conv2d_6_w, batch_normalization_12_gamma, batch_normalization_12_beta, batch_normalization_12_mean, batch_normalization_12_variance, conv2d_7_w, batch_normalization_13_gamma, batch_normalization_13_beta, batch_normalization_13_mean, batch_normalization_13_variance, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
- __visc__bindIn(var_1, 6, 4, 0);
- __visc__bindIn(var_1, 7, 5, 0);
- __visc__bindIn(var_1, 8, 6, 0);
- __visc__bindIn(var_1, 9, 7, 0);
- __visc__bindIn(var_1, 10, 8, 0);
- __visc__bindIn(var_1, 11, 9, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 12, 2, 0);
- __visc__bindIn(var_3, 13, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 14, 2, 0);
- __visc__bindIn(var_4, 15, 3, 0);
- __visc__bindIn(var_4, 16, 4, 0);
- __visc__bindIn(var_4, 17, 5, 0);
- __visc__bindIn(var_4, 18, 6, 0);
- __visc__bindIn(var_4, 19, 7, 0);
- __visc__bindIn(var_4, 20, 8, 0);
- __visc__bindIn(var_4, 21, 9, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
- __visc__bindIn(var_6, 22, 2, 0);
- __visc__bindIn(var_6, 23, 3, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 24, 2, 0);
- __visc__bindIn(var_7, 25, 3, 0);
- __visc__bindIn(var_7, 26, 4, 0);
- __visc__bindIn(var_7, 27, 5, 0);
- __visc__bindIn(var_7, 28, 6, 0);
- __visc__bindIn(var_7, 29, 7, 0);
- __visc__bindIn(var_7, 30, 8, 0);
- __visc__bindIn(var_7, 31, 9, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 32, 2, 0);
- __visc__bindIn(var_9, 33, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 34, 2, 0);
- __visc__bindIn(var_10, 35, 3, 0);
- __visc__bindIn(var_10, 36, 4, 0);
- __visc__bindIn(var_10, 37, 5, 0);
- __visc__bindIn(var_10, 38, 6, 0);
- __visc__bindIn(var_10, 39, 7, 0);
- __visc__bindIn(var_10, 40, 8, 0);
- __visc__bindIn(var_10, 41, 9, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 42, 2, 0);
- __visc__bindIn(var_12, 43, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 44, 2, 0);
- __visc__bindIn(var_13, 45, 3, 0);
- __visc__bindIn(var_13, 46, 4, 0);
- __visc__bindIn(var_13, 47, 5, 0);
- __visc__bindIn(var_13, 48, 6, 0);
- __visc__bindIn(var_13, 49, 7, 0);
- __visc__bindIn(var_13, 50, 8, 0);
- __visc__bindIn(var_13, 51, 9, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 52, 2, 0);
- __visc__bindIn(var_15, 53, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
- __visc__bindIn(var_16, 54, 2, 0);
- __visc__bindIn(var_16, 55, 3, 0);
- __visc__bindIn(var_16, 56, 4, 0);
- __visc__bindIn(var_16, 57, 5, 0);
- __visc__bindIn(var_16, 58, 6, 0);
- __visc__bindIn(var_16, 59, 7, 0);
- __visc__bindIn(var_16, 60, 8, 0);
- __visc__bindIn(var_16, 61, 9, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 62, 2, 0);
- __visc__bindIn(var_18, 63, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
- __visc__bindIn(var_19, 64, 2, 0);
- __visc__bindIn(var_19, 65, 3, 0);
- __visc__bindIn(var_19, 66, 4, 0);
- __visc__bindIn(var_19, 67, 5, 0);
- __visc__bindIn(var_19, 68, 6, 0);
- __visc__bindIn(var_19, 69, 7, 0);
- __visc__bindIn(var_19, 70, 8, 0);
- __visc__bindIn(var_19, 71, 9, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 72, 2, 0);
- __visc__bindIn(var_21, 73, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
- __visc__bindIn(var_22, 74, 2, 0);
- __visc__bindIn(var_22, 75, 3, 0);
- __visc__bindIn(var_22, 76, 4, 0);
- __visc__bindIn(var_22, 77, 5, 0);
- __visc__bindIn(var_22, 78, 6, 0);
- __visc__bindIn(var_22, 79, 7, 0);
- __visc__bindIn(var_22, 80, 8, 0);
- __visc__bindIn(var_22, 81, 9, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 82, 2, 0);
- __visc__bindIn(var_24, 83, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 84, 2, 0);
- __visc__bindIn(var_25, 85, 3, 0);
- __visc__bindIn(var_25, 86, 4, 0);
- __visc__bindIn(var_25, 87, 5, 0);
- __visc__bindIn(var_25, 88, 6, 0);
- __visc__bindIn(var_25, 89, 7, 0);
- __visc__bindIn(var_25, 90, 8, 0);
- __visc__bindIn(var_25, 91, 9, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- void* var_27 = __visc__createNodeND(0, var_27_node);
-
- __visc__edge(var_26, var_27, 1, 0, 0, 0);
- __visc__edge(var_26, var_27, 1, 1, 1, 0);
- __visc__bindIn(var_27, 92, 2, 0);
- __visc__bindIn(var_27, 93, 3, 0);
-
- void* var_28 = __visc__createNodeND(0, var_28_node);
-
- __visc__edge(var_27, var_28, 1, 0, 0, 0);
- __visc__edge(var_27, var_28, 1, 1, 1, 0);
- __visc__bindIn(var_28, 94, 2, 0);
- __visc__bindIn(var_28, 95, 3, 0);
- __visc__bindIn(var_28, 96, 4, 0);
- __visc__bindIn(var_28, 97, 5, 0);
- __visc__bindIn(var_28, 98, 6, 0);
- __visc__bindIn(var_28, 99, 7, 0);
- __visc__bindIn(var_28, 100, 8, 0);
- __visc__bindIn(var_28, 101, 9, 0);
-
- void* var_29 = __visc__createNodeND(0, var_29_node);
-
- __visc__edge(var_28, var_29, 1, 0, 0, 0);
- __visc__edge(var_28, var_29, 1, 1, 1, 0);
-
- void* var_30 = __visc__createNodeND(0, var_30_node);
-
- __visc__edge(var_29, var_30, 1, 0, 0, 0);
- __visc__edge(var_29, var_30, 1, 1, 1, 0);
- __visc__bindIn(var_30, 102, 2, 0);
- __visc__bindIn(var_30, 103, 3, 0);
-
- void* var_31 = __visc__createNodeND(0, var_31_node);
-
- __visc__edge(var_30, var_31, 1, 0, 0, 0);
- __visc__edge(var_30, var_31, 1, 1, 1, 0);
- __visc__bindIn(var_31, 104, 2, 0);
- __visc__bindIn(var_31, 105, 3, 0);
- __visc__bindIn(var_31, 106, 4, 0);
- __visc__bindIn(var_31, 107, 5, 0);
- __visc__bindIn(var_31, 108, 6, 0);
- __visc__bindIn(var_31, 109, 7, 0);
- __visc__bindIn(var_31, 110, 8, 0);
- __visc__bindIn(var_31, 111, 9, 0);
-
- void* var_32 = __visc__createNodeND(0, var_32_node);
-
- __visc__edge(var_31, var_32, 1, 0, 0, 0);
- __visc__edge(var_31, var_32, 1, 1, 1, 0);
-
- void* var_33 = __visc__createNodeND(0, var_33_node);
-
- __visc__edge(var_32, var_33, 1, 0, 0, 0);
- __visc__edge(var_32, var_33, 1, 1, 1, 0);
- __visc__bindIn(var_33, 112, 2, 0);
- __visc__bindIn(var_33, 113, 3, 0);
-
- void* var_34 = __visc__createNodeND(0, var_34_node);
-
- __visc__edge(var_33, var_34, 1, 0, 0, 0);
- __visc__edge(var_33, var_34, 1, 1, 1, 0);
- __visc__bindIn(var_34, 114, 2, 0);
- __visc__bindIn(var_34, 115, 3, 0);
- __visc__bindIn(var_34, 116, 4, 0);
- __visc__bindIn(var_34, 117, 5, 0);
- __visc__bindIn(var_34, 118, 6, 0);
- __visc__bindIn(var_34, 119, 7, 0);
- __visc__bindIn(var_34, 120, 8, 0);
- __visc__bindIn(var_34, 121, 9, 0);
-
- void* var_35 = __visc__createNodeND(0, var_35_node);
-
- __visc__edge(var_34, var_35, 1, 0, 0, 0);
- __visc__edge(var_34, var_35, 1, 1, 1, 0);
-
- void* var_36 = __visc__createNodeND(0, var_36_node);
-
- __visc__edge(var_35, var_36, 1, 0, 0, 0);
- __visc__edge(var_35, var_36, 1, 1, 1, 0);
- __visc__bindIn(var_36, 122, 2, 0);
- __visc__bindIn(var_36, 123, 3, 0);
-
- void* var_37 = __visc__createNodeND(0, var_37_node);
-
- __visc__edge(var_36, var_37, 1, 0, 0, 0);
- __visc__edge(var_36, var_37, 1, 1, 1, 0);
- __visc__bindIn(var_37, 124, 2, 0);
- __visc__bindIn(var_37, 125, 3, 0);
- __visc__bindIn(var_37, 126, 4, 0);
- __visc__bindIn(var_37, 127, 5, 0);
- __visc__bindIn(var_37, 128, 6, 0);
- __visc__bindIn(var_37, 129, 7, 0);
- __visc__bindIn(var_37, 130, 8, 0);
- __visc__bindIn(var_37, 131, 9, 0);
-
- void* var_38 = __visc__createNodeND(0, var_38_node);
-
- __visc__edge(var_37, var_38, 1, 0, 0, 0);
- __visc__edge(var_37, var_38, 1, 1, 1, 0);
-
- void* var_39 = __visc__createNodeND(0, var_39_node);
-
- __visc__edge(var_38, var_39, 1, 0, 0, 0);
- __visc__edge(var_38, var_39, 1, 1, 1, 0);
-
- void* var_40 = __visc__createNodeND(0, var_40_node);
-
- __visc__edge(var_39, var_40, 1, 0, 0, 0);
- __visc__edge(var_39, var_40, 1, 1, 1, 0);
- __visc__bindIn(var_40, 132, 2, 0);
- __visc__bindIn(var_40, 133, 3, 0);
-
- void* var_41 = __visc__createNodeND(0, var_41_node);
-
- __visc__edge(var_40, var_41, 1, 0, 0, 0);
- __visc__edge(var_40, var_41, 1, 1, 1, 0);
- __visc__bindIn(var_41, 134, 2, 0);
- __visc__bindIn(var_41, 135, 3, 0);
-
- void* var_42 = __visc__createNodeND(0, var_42_node);
-
- __visc__edge(var_41, var_42, 1, 0, 0, 0);
- __visc__edge(var_41, var_42, 1, 1, 1, 0);
-
- __visc__bindOut(var_42, 0, 0, 0);
- __visc__bindOut(var_42, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* batch_normalization_1_gamma;
- size_t batch_normalization_1_gamma_bytes;
- void* batch_normalization_1_beta;
- size_t batch_normalization_1_beta_bytes;
- void* batch_normalization_1_mean;
- size_t batch_normalization_1_mean_bytes;
- void* batch_normalization_1_variance;
- size_t batch_normalization_1_variance_bytes;
- void* depthwise_conv2d_1_w;
- size_t depthwise_conv2d_1_w_bytes;
- void* batch_normalization_2_gamma;
- size_t batch_normalization_2_gamma_bytes;
- void* batch_normalization_2_beta;
- size_t batch_normalization_2_beta_bytes;
- void* batch_normalization_2_mean;
- size_t batch_normalization_2_mean_bytes;
- void* batch_normalization_2_variance;
- size_t batch_normalization_2_variance_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* batch_normalization_3_gamma;
- size_t batch_normalization_3_gamma_bytes;
- void* batch_normalization_3_beta;
- size_t batch_normalization_3_beta_bytes;
- void* batch_normalization_3_mean;
- size_t batch_normalization_3_mean_bytes;
- void* batch_normalization_3_variance;
- size_t batch_normalization_3_variance_bytes;
- void* depthwise_conv2d_2_w;
- size_t depthwise_conv2d_2_w_bytes;
- void* batch_normalization_4_gamma;
- size_t batch_normalization_4_gamma_bytes;
- void* batch_normalization_4_beta;
- size_t batch_normalization_4_beta_bytes;
- void* batch_normalization_4_mean;
- size_t batch_normalization_4_mean_bytes;
- void* batch_normalization_4_variance;
- size_t batch_normalization_4_variance_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* batch_normalization_5_gamma;
- size_t batch_normalization_5_gamma_bytes;
- void* batch_normalization_5_beta;
- size_t batch_normalization_5_beta_bytes;
- void* batch_normalization_5_mean;
- size_t batch_normalization_5_mean_bytes;
- void* batch_normalization_5_variance;
- size_t batch_normalization_5_variance_bytes;
- void* depthwise_conv2d_3_w;
- size_t depthwise_conv2d_3_w_bytes;
- void* batch_normalization_6_gamma;
- size_t batch_normalization_6_gamma_bytes;
- void* batch_normalization_6_beta;
- size_t batch_normalization_6_beta_bytes;
- void* batch_normalization_6_mean;
- size_t batch_normalization_6_mean_bytes;
- void* batch_normalization_6_variance;
- size_t batch_normalization_6_variance_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* batch_normalization_7_gamma;
- size_t batch_normalization_7_gamma_bytes;
- void* batch_normalization_7_beta;
- size_t batch_normalization_7_beta_bytes;
- void* batch_normalization_7_mean;
- size_t batch_normalization_7_mean_bytes;
- void* batch_normalization_7_variance;
- size_t batch_normalization_7_variance_bytes;
- void* depthwise_conv2d_4_w;
- size_t depthwise_conv2d_4_w_bytes;
- void* batch_normalization_8_gamma;
- size_t batch_normalization_8_gamma_bytes;
- void* batch_normalization_8_beta;
- size_t batch_normalization_8_beta_bytes;
- void* batch_normalization_8_mean;
- size_t batch_normalization_8_mean_bytes;
- void* batch_normalization_8_variance;
- size_t batch_normalization_8_variance_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* batch_normalization_9_gamma;
- size_t batch_normalization_9_gamma_bytes;
- void* batch_normalization_9_beta;
- size_t batch_normalization_9_beta_bytes;
- void* batch_normalization_9_mean;
- size_t batch_normalization_9_mean_bytes;
- void* batch_normalization_9_variance;
- size_t batch_normalization_9_variance_bytes;
- void* depthwise_conv2d_5_w;
- size_t depthwise_conv2d_5_w_bytes;
- void* batch_normalization_10_gamma;
- size_t batch_normalization_10_gamma_bytes;
- void* batch_normalization_10_beta;
- size_t batch_normalization_10_beta_bytes;
- void* batch_normalization_10_mean;
- size_t batch_normalization_10_mean_bytes;
- void* batch_normalization_10_variance;
- size_t batch_normalization_10_variance_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* batch_normalization_11_gamma;
- size_t batch_normalization_11_gamma_bytes;
- void* batch_normalization_11_beta;
- size_t batch_normalization_11_beta_bytes;
- void* batch_normalization_11_mean;
- size_t batch_normalization_11_mean_bytes;
- void* batch_normalization_11_variance;
- size_t batch_normalization_11_variance_bytes;
- void* depthwise_conv2d_6_w;
- size_t depthwise_conv2d_6_w_bytes;
- void* batch_normalization_12_gamma;
- size_t batch_normalization_12_gamma_bytes;
- void* batch_normalization_12_beta;
- size_t batch_normalization_12_beta_bytes;
- void* batch_normalization_12_mean;
- size_t batch_normalization_12_mean_bytes;
- void* batch_normalization_12_variance;
- size_t batch_normalization_12_variance_bytes;
- void* conv2d_7_w;
- size_t conv2d_7_w_bytes;
- void* batch_normalization_13_gamma;
- size_t batch_normalization_13_gamma_bytes;
- void* batch_normalization_13_beta;
- size_t batch_normalization_13_beta_bytes;
- void* batch_normalization_13_mean;
- size_t batch_normalization_13_mean_bytes;
- void* batch_normalization_13_variance;
- size_t batch_normalization_13_variance_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/mobilenet_shallow/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
- std::string batch_normalization_1_gamma_path = dir_prefix + std::string("batch_normalization_1_gamma.bin");
- void* batch_normalization_1_gamma = readTrainedWeights(batch_normalization_1_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_beta_path = dir_prefix + std::string("batch_normalization_1_beta.bin");
- void* batch_normalization_1_beta = readTrainedWeights(batch_normalization_1_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_mean_path = dir_prefix + std::string("batch_normalization_1_mean.bin");
- void* batch_normalization_1_mean = readTrainedWeights(batch_normalization_1_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_variance_path = dir_prefix + std::string("batch_normalization_1_variance.bin");
- void* batch_normalization_1_variance = readTrainedWeights(batch_normalization_1_variance_path.c_str(), 0,1,32,1,1);
- std::string depthwise_conv2d_1_w_path = dir_prefix + std::string("depthwise_conv2d_1_w.bin");
- void* depthwise_conv2d_1_w = readTrainedWeights(depthwise_conv2d_1_w_path.c_str(), 0,32,1,3,3);
- std::string batch_normalization_2_gamma_path = dir_prefix + std::string("batch_normalization_2_gamma.bin");
- void* batch_normalization_2_gamma = readTrainedWeights(batch_normalization_2_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_beta_path = dir_prefix + std::string("batch_normalization_2_beta.bin");
- void* batch_normalization_2_beta = readTrainedWeights(batch_normalization_2_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_mean_path = dir_prefix + std::string("batch_normalization_2_mean.bin");
- void* batch_normalization_2_mean = readTrainedWeights(batch_normalization_2_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_variance_path = dir_prefix + std::string("batch_normalization_2_variance.bin");
- void* batch_normalization_2_variance = readTrainedWeights(batch_normalization_2_variance_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,1,1);
- std::string batch_normalization_3_gamma_path = dir_prefix + std::string("batch_normalization_3_gamma.bin");
- void* batch_normalization_3_gamma = readTrainedWeights(batch_normalization_3_gamma_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_beta_path = dir_prefix + std::string("batch_normalization_3_beta.bin");
- void* batch_normalization_3_beta = readTrainedWeights(batch_normalization_3_beta_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_mean_path = dir_prefix + std::string("batch_normalization_3_mean.bin");
- void* batch_normalization_3_mean = readTrainedWeights(batch_normalization_3_mean_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_variance_path = dir_prefix + std::string("batch_normalization_3_variance.bin");
- void* batch_normalization_3_variance = readTrainedWeights(batch_normalization_3_variance_path.c_str(), 0,1,64,1,1);
- std::string depthwise_conv2d_2_w_path = dir_prefix + std::string("depthwise_conv2d_2_w.bin");
- void* depthwise_conv2d_2_w = readTrainedWeights(depthwise_conv2d_2_w_path.c_str(), 0,64,1,3,3);
- std::string batch_normalization_4_gamma_path = dir_prefix + std::string("batch_normalization_4_gamma.bin");
- void* batch_normalization_4_gamma = readTrainedWeights(batch_normalization_4_gamma_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_beta_path = dir_prefix + std::string("batch_normalization_4_beta.bin");
- void* batch_normalization_4_beta = readTrainedWeights(batch_normalization_4_beta_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_mean_path = dir_prefix + std::string("batch_normalization_4_mean.bin");
- void* batch_normalization_4_mean = readTrainedWeights(batch_normalization_4_mean_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_variance_path = dir_prefix + std::string("batch_normalization_4_variance.bin");
- void* batch_normalization_4_variance = readTrainedWeights(batch_normalization_4_variance_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,128,64,1,1);
- std::string batch_normalization_5_gamma_path = dir_prefix + std::string("batch_normalization_5_gamma.bin");
- void* batch_normalization_5_gamma = readTrainedWeights(batch_normalization_5_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_beta_path = dir_prefix + std::string("batch_normalization_5_beta.bin");
- void* batch_normalization_5_beta = readTrainedWeights(batch_normalization_5_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_mean_path = dir_prefix + std::string("batch_normalization_5_mean.bin");
- void* batch_normalization_5_mean = readTrainedWeights(batch_normalization_5_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_variance_path = dir_prefix + std::string("batch_normalization_5_variance.bin");
- void* batch_normalization_5_variance = readTrainedWeights(batch_normalization_5_variance_path.c_str(), 0,1,128,1,1);
- std::string depthwise_conv2d_3_w_path = dir_prefix + std::string("depthwise_conv2d_3_w.bin");
- void* depthwise_conv2d_3_w = readTrainedWeights(depthwise_conv2d_3_w_path.c_str(), 0,128,1,3,3);
- std::string batch_normalization_6_gamma_path = dir_prefix + std::string("batch_normalization_6_gamma.bin");
- void* batch_normalization_6_gamma = readTrainedWeights(batch_normalization_6_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_beta_path = dir_prefix + std::string("batch_normalization_6_beta.bin");
- void* batch_normalization_6_beta = readTrainedWeights(batch_normalization_6_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_mean_path = dir_prefix + std::string("batch_normalization_6_mean.bin");
- void* batch_normalization_6_mean = readTrainedWeights(batch_normalization_6_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_variance_path = dir_prefix + std::string("batch_normalization_6_variance.bin");
- void* batch_normalization_6_variance = readTrainedWeights(batch_normalization_6_variance_path.c_str(), 0,1,128,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,128,128,1,1);
- std::string batch_normalization_7_gamma_path = dir_prefix + std::string("batch_normalization_7_gamma.bin");
- void* batch_normalization_7_gamma = readTrainedWeights(batch_normalization_7_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_beta_path = dir_prefix + std::string("batch_normalization_7_beta.bin");
- void* batch_normalization_7_beta = readTrainedWeights(batch_normalization_7_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_mean_path = dir_prefix + std::string("batch_normalization_7_mean.bin");
- void* batch_normalization_7_mean = readTrainedWeights(batch_normalization_7_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_variance_path = dir_prefix + std::string("batch_normalization_7_variance.bin");
- void* batch_normalization_7_variance = readTrainedWeights(batch_normalization_7_variance_path.c_str(), 0,1,128,1,1);
- std::string depthwise_conv2d_4_w_path = dir_prefix + std::string("depthwise_conv2d_4_w.bin");
- void* depthwise_conv2d_4_w = readTrainedWeights(depthwise_conv2d_4_w_path.c_str(), 0,128,1,3,3);
- std::string batch_normalization_8_gamma_path = dir_prefix + std::string("batch_normalization_8_gamma.bin");
- void* batch_normalization_8_gamma = readTrainedWeights(batch_normalization_8_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_beta_path = dir_prefix + std::string("batch_normalization_8_beta.bin");
- void* batch_normalization_8_beta = readTrainedWeights(batch_normalization_8_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_mean_path = dir_prefix + std::string("batch_normalization_8_mean.bin");
- void* batch_normalization_8_mean = readTrainedWeights(batch_normalization_8_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_variance_path = dir_prefix + std::string("batch_normalization_8_variance.bin");
- void* batch_normalization_8_variance = readTrainedWeights(batch_normalization_8_variance_path.c_str(), 0,1,128,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,128,1,1);
- std::string batch_normalization_9_gamma_path = dir_prefix + std::string("batch_normalization_9_gamma.bin");
- void* batch_normalization_9_gamma = readTrainedWeights(batch_normalization_9_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_beta_path = dir_prefix + std::string("batch_normalization_9_beta.bin");
- void* batch_normalization_9_beta = readTrainedWeights(batch_normalization_9_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_mean_path = dir_prefix + std::string("batch_normalization_9_mean.bin");
- void* batch_normalization_9_mean = readTrainedWeights(batch_normalization_9_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_variance_path = dir_prefix + std::string("batch_normalization_9_variance.bin");
- void* batch_normalization_9_variance = readTrainedWeights(batch_normalization_9_variance_path.c_str(), 0,1,256,1,1);
- std::string depthwise_conv2d_5_w_path = dir_prefix + std::string("depthwise_conv2d_5_w.bin");
- void* depthwise_conv2d_5_w = readTrainedWeights(depthwise_conv2d_5_w_path.c_str(), 0,256,1,3,3);
- std::string batch_normalization_10_gamma_path = dir_prefix + std::string("batch_normalization_10_gamma.bin");
- void* batch_normalization_10_gamma = readTrainedWeights(batch_normalization_10_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_beta_path = dir_prefix + std::string("batch_normalization_10_beta.bin");
- void* batch_normalization_10_beta = readTrainedWeights(batch_normalization_10_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_mean_path = dir_prefix + std::string("batch_normalization_10_mean.bin");
- void* batch_normalization_10_mean = readTrainedWeights(batch_normalization_10_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_variance_path = dir_prefix + std::string("batch_normalization_10_variance.bin");
- void* batch_normalization_10_variance = readTrainedWeights(batch_normalization_10_variance_path.c_str(), 0,1,256,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,256,256,1,1);
- std::string batch_normalization_11_gamma_path = dir_prefix + std::string("batch_normalization_11_gamma.bin");
- void* batch_normalization_11_gamma = readTrainedWeights(batch_normalization_11_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_beta_path = dir_prefix + std::string("batch_normalization_11_beta.bin");
- void* batch_normalization_11_beta = readTrainedWeights(batch_normalization_11_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_mean_path = dir_prefix + std::string("batch_normalization_11_mean.bin");
- void* batch_normalization_11_mean = readTrainedWeights(batch_normalization_11_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_variance_path = dir_prefix + std::string("batch_normalization_11_variance.bin");
- void* batch_normalization_11_variance = readTrainedWeights(batch_normalization_11_variance_path.c_str(), 0,1,256,1,1);
- std::string depthwise_conv2d_6_w_path = dir_prefix + std::string("depthwise_conv2d_6_w.bin");
- void* depthwise_conv2d_6_w = readTrainedWeights(depthwise_conv2d_6_w_path.c_str(), 0,256,1,3,3);
- std::string batch_normalization_12_gamma_path = dir_prefix + std::string("batch_normalization_12_gamma.bin");
- void* batch_normalization_12_gamma = readTrainedWeights(batch_normalization_12_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_beta_path = dir_prefix + std::string("batch_normalization_12_beta.bin");
- void* batch_normalization_12_beta = readTrainedWeights(batch_normalization_12_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_mean_path = dir_prefix + std::string("batch_normalization_12_mean.bin");
- void* batch_normalization_12_mean = readTrainedWeights(batch_normalization_12_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_variance_path = dir_prefix + std::string("batch_normalization_12_variance.bin");
- void* batch_normalization_12_variance = readTrainedWeights(batch_normalization_12_variance_path.c_str(), 0,1,256,1,1);
- std::string conv2d_7_w_path = dir_prefix + std::string("conv2d_7_w.bin");
- void* conv2d_7_w = readTrainedWeights(conv2d_7_w_path.c_str(), 0,512,256,1,1);
- std::string batch_normalization_13_gamma_path = dir_prefix + std::string("batch_normalization_13_gamma.bin");
- void* batch_normalization_13_gamma = readTrainedWeights(batch_normalization_13_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_beta_path = dir_prefix + std::string("batch_normalization_13_beta.bin");
- void* batch_normalization_13_beta = readTrainedWeights(batch_normalization_13_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_mean_path = dir_prefix + std::string("batch_normalization_13_mean.bin");
- void* batch_normalization_13_mean = readTrainedWeights(batch_normalization_13_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_variance_path = dir_prefix + std::string("batch_normalization_13_variance.bin");
- void* batch_normalization_13_variance = readTrainedWeights(batch_normalization_13_variance_path.c_str(), 0,1,512,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,2048,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0, 5000,3,32,32);
- uint8_t* labels = readLabels(labels_path.c_str(), 5000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->batch_normalization_1_gamma = batch_normalization_1_gamma;
- args->batch_normalization_1_gamma_bytes = 0;
- args->batch_normalization_1_beta = batch_normalization_1_beta;
- args->batch_normalization_1_beta_bytes = 0;
- args->batch_normalization_1_mean = batch_normalization_1_mean;
- args->batch_normalization_1_mean_bytes = 0;
- args->batch_normalization_1_variance = batch_normalization_1_variance;
- args->batch_normalization_1_variance_bytes = 0;
- args->depthwise_conv2d_1_w = depthwise_conv2d_1_w;
- args->depthwise_conv2d_1_w_bytes = 0;
- args->batch_normalization_2_gamma = batch_normalization_2_gamma;
- args->batch_normalization_2_gamma_bytes = 0;
- args->batch_normalization_2_beta = batch_normalization_2_beta;
- args->batch_normalization_2_beta_bytes = 0;
- args->batch_normalization_2_mean = batch_normalization_2_mean;
- args->batch_normalization_2_mean_bytes = 0;
- args->batch_normalization_2_variance = batch_normalization_2_variance;
- args->batch_normalization_2_variance_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->batch_normalization_3_gamma = batch_normalization_3_gamma;
- args->batch_normalization_3_gamma_bytes = 0;
- args->batch_normalization_3_beta = batch_normalization_3_beta;
- args->batch_normalization_3_beta_bytes = 0;
- args->batch_normalization_3_mean = batch_normalization_3_mean;
- args->batch_normalization_3_mean_bytes = 0;
- args->batch_normalization_3_variance = batch_normalization_3_variance;
- args->batch_normalization_3_variance_bytes = 0;
- args->depthwise_conv2d_2_w = depthwise_conv2d_2_w;
- args->depthwise_conv2d_2_w_bytes = 0;
- args->batch_normalization_4_gamma = batch_normalization_4_gamma;
- args->batch_normalization_4_gamma_bytes = 0;
- args->batch_normalization_4_beta = batch_normalization_4_beta;
- args->batch_normalization_4_beta_bytes = 0;
- args->batch_normalization_4_mean = batch_normalization_4_mean;
- args->batch_normalization_4_mean_bytes = 0;
- args->batch_normalization_4_variance = batch_normalization_4_variance;
- args->batch_normalization_4_variance_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->batch_normalization_5_gamma = batch_normalization_5_gamma;
- args->batch_normalization_5_gamma_bytes = 0;
- args->batch_normalization_5_beta = batch_normalization_5_beta;
- args->batch_normalization_5_beta_bytes = 0;
- args->batch_normalization_5_mean = batch_normalization_5_mean;
- args->batch_normalization_5_mean_bytes = 0;
- args->batch_normalization_5_variance = batch_normalization_5_variance;
- args->batch_normalization_5_variance_bytes = 0;
- args->depthwise_conv2d_3_w = depthwise_conv2d_3_w;
- args->depthwise_conv2d_3_w_bytes = 0;
- args->batch_normalization_6_gamma = batch_normalization_6_gamma;
- args->batch_normalization_6_gamma_bytes = 0;
- args->batch_normalization_6_beta = batch_normalization_6_beta;
- args->batch_normalization_6_beta_bytes = 0;
- args->batch_normalization_6_mean = batch_normalization_6_mean;
- args->batch_normalization_6_mean_bytes = 0;
- args->batch_normalization_6_variance = batch_normalization_6_variance;
- args->batch_normalization_6_variance_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->batch_normalization_7_gamma = batch_normalization_7_gamma;
- args->batch_normalization_7_gamma_bytes = 0;
- args->batch_normalization_7_beta = batch_normalization_7_beta;
- args->batch_normalization_7_beta_bytes = 0;
- args->batch_normalization_7_mean = batch_normalization_7_mean;
- args->batch_normalization_7_mean_bytes = 0;
- args->batch_normalization_7_variance = batch_normalization_7_variance;
- args->batch_normalization_7_variance_bytes = 0;
- args->depthwise_conv2d_4_w = depthwise_conv2d_4_w;
- args->depthwise_conv2d_4_w_bytes = 0;
- args->batch_normalization_8_gamma = batch_normalization_8_gamma;
- args->batch_normalization_8_gamma_bytes = 0;
- args->batch_normalization_8_beta = batch_normalization_8_beta;
- args->batch_normalization_8_beta_bytes = 0;
- args->batch_normalization_8_mean = batch_normalization_8_mean;
- args->batch_normalization_8_mean_bytes = 0;
- args->batch_normalization_8_variance = batch_normalization_8_variance;
- args->batch_normalization_8_variance_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->batch_normalization_9_gamma = batch_normalization_9_gamma;
- args->batch_normalization_9_gamma_bytes = 0;
- args->batch_normalization_9_beta = batch_normalization_9_beta;
- args->batch_normalization_9_beta_bytes = 0;
- args->batch_normalization_9_mean = batch_normalization_9_mean;
- args->batch_normalization_9_mean_bytes = 0;
- args->batch_normalization_9_variance = batch_normalization_9_variance;
- args->batch_normalization_9_variance_bytes = 0;
- args->depthwise_conv2d_5_w = depthwise_conv2d_5_w;
- args->depthwise_conv2d_5_w_bytes = 0;
- args->batch_normalization_10_gamma = batch_normalization_10_gamma;
- args->batch_normalization_10_gamma_bytes = 0;
- args->batch_normalization_10_beta = batch_normalization_10_beta;
- args->batch_normalization_10_beta_bytes = 0;
- args->batch_normalization_10_mean = batch_normalization_10_mean;
- args->batch_normalization_10_mean_bytes = 0;
- args->batch_normalization_10_variance = batch_normalization_10_variance;
- args->batch_normalization_10_variance_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->batch_normalization_11_gamma = batch_normalization_11_gamma;
- args->batch_normalization_11_gamma_bytes = 0;
- args->batch_normalization_11_beta = batch_normalization_11_beta;
- args->batch_normalization_11_beta_bytes = 0;
- args->batch_normalization_11_mean = batch_normalization_11_mean;
- args->batch_normalization_11_mean_bytes = 0;
- args->batch_normalization_11_variance = batch_normalization_11_variance;
- args->batch_normalization_11_variance_bytes = 0;
- args->depthwise_conv2d_6_w = depthwise_conv2d_6_w;
- args->depthwise_conv2d_6_w_bytes = 0;
- args->batch_normalization_12_gamma = batch_normalization_12_gamma;
- args->batch_normalization_12_gamma_bytes = 0;
- args->batch_normalization_12_beta = batch_normalization_12_beta;
- args->batch_normalization_12_beta_bytes = 0;
- args->batch_normalization_12_mean = batch_normalization_12_mean;
- args->batch_normalization_12_mean_bytes = 0;
- args->batch_normalization_12_variance = batch_normalization_12_variance;
- args->batch_normalization_12_variance_bytes = 0;
- args->conv2d_7_w = conv2d_7_w;
- args->conv2d_7_w_bytes = 0;
- args->batch_normalization_13_gamma = batch_normalization_13_gamma;
- args->batch_normalization_13_gamma_bytes = 0;
- args->batch_normalization_13_beta = batch_normalization_13_beta;
- args->batch_normalization_13_beta_bytes = 0;
- args->batch_normalization_13_mean = batch_normalization_13_mean;
- args->batch_normalization_13_mean_bytes = 0;
- args->batch_normalization_13_variance = batch_normalization_13_variance;
- args->batch_normalization_13_variance_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 5000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/Makefile b/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/Makefile
deleted file mode 100644
index ec758b57a729162a7d05b3d2393b530352aca746..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/Makefile
+++ /dev/null
@@ -1,67 +0,0 @@
-# NOTE: $LLVM_SRC_ROOT and $CUDA_TOOLKIT_ROOT_DIR have to be set
-# HPVM_BUILD_DIR can be optionally set
-DNN_BENCHMARK_ROOT = $(LLVM_SRC_ROOT)/test/VISC/DNN_Benchmarks
-HPVM_BUILD_DIR ?= $(LLVM_SRC_ROOT)/../build
-
-CCLANG ?= $(HPVM_BUILD_DIR)/bin/clang++
-OPT = $(HPVM_BUILD_DIR)/bin/opt
-LLVM_DIS = $(HPVM_BUILD_DIR)/bin/llvm-dis
-LLVM_LINK = $(HPVM_BUILD_DIR)/bin/llvm-link
-LLVM_INCLUDE_DIR = $(LLVM_SRC_ROOT)/include
-
-SRC_DIR = src
-BUILD_DIR = build
-# NOTE: Change to the name of your benchmark
-APP = pipeline_gsme
-
-TENSOR_INCLUDE_DIR = $(DNN_BENCHMARK_ROOT)/common/include
-TENSOR_RT_INCLUDE_DIR = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/tensor_runtime/include
-CUSTOM_LIB_PATHS = $(LLVM_SRC_ROOT)/projects/hpvm-tensor-rt/lib/libtensor_runtime.a \
- $(LLVM_SRC_ROOT)/projects/gpu_profiler/lib/libgpu_profiler.a \
- $(LLVM_SRC_ROOT)/projects/soc_simulator/lib/libpromise_profiler.a
-
-CC_FLAGS = -g -I $(LLVM_INCLUDE_DIR) -I $(TENSOR_INCLUDE_DIR) -I $(TENSOR_RT_INCLUDE_DIR) -I $(CUDA_TOOLKIT_ROOT_DIR)/include -ffast-math -std=c++11
-CCFLAGS += -DDEVICE=CUDNN_TARGET
-LINKER_FLAGS = -L $(CUDA_TOOLKIT_ROOT_DIR)/lib64 -lstdc++fs -lpthread -lcudart -lcurand -lcudnn -lcublas -lcufft
-
-HPVM_LIB_DIR = $(HPVM_BUILD_DIR)/lib
-
-
-CONF_FILE_PATH=$(realpath data/tuner_confs.txt)
-# NOTE: Needs proper handling in the WRAPPER backend because Quant range not needed for IMAGE Benchmarks
-WRAPPER_API_QUANT_FILE_PATH=
-
-
-VISC_OPTFLAGS = -load $(HPVM_LIB_DIR)/LLVMBuildDFG.so -load $(HPVM_LIB_DIR)/LLVMInPlaceDFGAnalysis.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_WrapperAPI.so -load $(HPVM_LIB_DIR)/LLVMDFG2LLVM_X86.so -load $(HPVM_LIB_DIR)/LLVMFuseHPVMTensorNodes.so -load $(HPVM_LIB_DIR)/LLVMClearDFG.so -inplace -hpvm-fuse -dfg2llvm-wrapperapi -quantization-levels-filename=$(WRAPPER_API_QUANT_FILE_PATH) -configuration-inputs-filename=$(CONF_FILE_PATH) -dfg2llvm-x86 -clearDFG
-
-
-
-TARGET = $(BUILD_DIR)/$(APP).opt.bc direct
-SOURCES = $(SRC_DIR)/$(APP).cpp
-VISC_RT_PATH = $(LLVM_SRC_ROOT)/../build/projects/visc-rt/visc-rt.ll
-
-#OBJS = $(BUILD_DIR)/$(wildcabrd *.ll)
-.PRECIOUS: $(BUILD_DIR)/$(APP).ll $(BUILD_DIR)/$(APP).visc.ll
-default: $(BUILD_DIR) $(TARGET)
-
-
-$(BUILD_DIR)/%.ll: $(SRC_DIR)/%.cpp $(BUILD_DIR)
- $(CCLANG) $(CC_FLAGS) -emit-llvm src/$(APP).cpp -S -o $(BUILD_DIR)/$(APP).ll
-
-direct: $(SRC_DIR)/$(APP)_direct_call.cpp
- $(CCLANG) $(CC_FLAGS) src/$(APP)_direct_call.cpp $(CUSTOM_LIB_PATHS) -o $(BUILD_DIR)/$(APP)_direct_call $(LINKER_FLAGS)
-
-autotuner: $(SRC_DIR)/$(APP)_autotuner.cpp
- $(CCLANG) $(CC_FLAGS) src/$(APP)_autotuner.cpp $(CUSTOM_LIB_PATHS) -o $(BUILD_DIR)/$(APP)_autotuner $(LINKER_FLAGS)
-
-$(BUILD_DIR)/%.opt.bc: $(BUILD_DIR)/%.ll
- $(OPT) -load LLVMGenVISC.so -genvisc -globaldce $(BUILD_DIR)/$(APP).ll -S -o $(BUILD_DIR)/$(APP).visc.ll
- $(OPT) $(VISC_OPTFLAGS) $(BUILD_DIR)/$(APP).visc.ll -o $(BUILD_DIR)/$(APP)_wrapper.bc
- $(LLVM_LINK) $(BUILD_DIR)/$(APP)_wrapper.bc $(VISC_RT_PATH) -o $(BUILD_DIR)/$(APP)_wrapper_linked.bc
- $(CCLANG) $(BUILD_DIR)/$(APP)_wrapper_linked.bc $(CUSTOM_LIB_PATHS) $(PROMISE_PROFILER_LIB_PATH) -o $(BUILD_DIR)/$(APP)_final $(LINKER_FLAGS)
-
-$(BUILD_DIR):
- mkdir -p $@
-
-clean:
- rm -rf $(BUILD_DIR)
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/data/tuner_confs.txt b/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/data/tuner_confs.txt
deleted file mode 100644
index dfc18fe9970642f39144b16a986409ba39b0833a..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/data/tuner_confs.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-0.0
-+++++
-conf1 1.5 90 1.0 2.0
-1 gpu reduce fp32 1
-2 gpu map1 fp32 1
-3 gpu conv fp32 1
-4 gpu conv fp32 1
-5 gpu conv fp32 1
-6 gpu conv fp32 1
-7 gpu map2 fp32 1
------
\ No newline at end of file
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/src/pipeline_gsme.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/src/pipeline_gsme.cpp
deleted file mode 100644
index 7b4d78de4c081c1d6724132282025c590e8d76ea..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/pipeline_gsme/src/pipeline_gsme.cpp
+++ /dev/null
@@ -1,108 +0,0 @@
-#include "tensorUtils.h"
-#include "tensor_runtime.h"
-#include "visc.h"
-
-const size_t n_channels = 3;
-
-void *read_filter(const char *filter_prefix, const char *postfix, size_t sz) {
- void *t = readTrainedWeights(
- ((std::string)filter_prefix + postfix).c_str(), float_type,
- 1, 1, sz, sz);
- auto *host_data = (float *)((Tensor *)t)->host_data;
- float sum = 0;
- for (size_t i = 0; i < sz * sz; i++)
- sum += host_data[i];
- sum = abs(sum);
- if (sum < 1e-4)
- return t;
- for (size_t i = 0; i < sz * sz; i++)
- host_data[i] /= sum;
- return t;
-}
-
-Tensor *gaussianFilter(float sigma, size_t w, size_t h, size_t n_chan) {
- int64_t m = (w - 1) / 2, n = (h - 1) / 2;
- auto *data = new float[w * h];
- float sum = 0.0f;
- for (int64_t i = -m; i <= m; i++)
- for (int64_t j = -n; j <= n; j++) {
- size_t idx = (i + m) * h + (j + n);
- float exponent = -(i * i + j * j) / (2.0 * sigma * sigma);
- data[idx] = exp(exponent);
- sum += data[idx];
- }
- if (sum != 0.0f)
- for (size_t i = 0; i < w * h; i++)
- data[i] /= sum;
- return (Tensor *)createFilterFromData(CUDNN_DATA_FLOAT, data, w, h, n_chan);
-}
-
-void *main_procedure(const char *filter_prefix, void *input) {
- // std::string prefix("../model_params/pipeline/filters/");
- // void *gaussian_filter = gaussianFilter(1.4, 3, 3, 1);
- void *gaussian_filter = read_filter(filter_prefix, "GaussianFilter.bin", 9);
- void *outline_filter = read_filter(filter_prefix, "OutlineFilter.bin", 3);
- void *sharpen_filter = read_filter(filter_prefix, "SharpenFilter.bin", 3);
- void *emboss_filter = read_filter(filter_prefix, "EmbossFilter.bin", 5);
- void *emboss_bias = read_filter(filter_prefix, "EmbossBias.bin", 1);
- void *motionblur_filter =
- read_filter(filter_prefix, "MotionblurFilter.bin", 9);
-
- // 0. Grayscale
- auto *summed_image = wrapper_tensorReduce("1", input, 1, (int)MathOp::Add);
- auto *grayscale_image =
- wrapper_tensorMap1("2", (int)MathOp::Avg3, summed_image);
-
- void *gaussian_out = wrapper_ConvLayer(
- "3", grayscale_image, gaussian_filter, nullptr, 4, 4, 1, 1, 0, 0, -1, 0.0,
- 0.0);
- void *sharpen_out = wrapper_ConvLayer(
- "4", gaussian_out, sharpen_filter, nullptr, 1, 1, 1, 1, 0, 0, -1, 0.0,
- 0.0);
- // void *outline_out = wrapper_ConvLayer(
- // "7", grayscale_image, outline_filter, nullptr, 1, 1, 1, 1, 0, 0, -1, 0.0,
- // 0.0);
- void *motionblur_out = wrapper_ConvLayer(
- "5", sharpen_out, motionblur_filter, nullptr, 1, 1, 1, 1, 0, 0, -1, 0.0, 0.0);
- void *emboss_out = wrapper_ConvLayer(
- "6", motionblur_out, emboss_filter, nullptr, 1, 1, 1, 1, 0, 0, -1, 0.0, 0.0);
- void *emboss_bias_out =
- wrapper_tensorMap2("7", (int)MathOp::Add, emboss_out, emboss_bias);
-
- return emboss_bias_out;
-}
-
-const size_t batch_size = 100;
-
-int main(int argc, char *argv[]) {
- if (argc < 4)
- return 0;
- llvm_hpvm_initTensorRt(0);
- llvm_hpvm_initializeRuntimeController("data/tuner_confs.txt", "");
-
- size_t bstart = 0;
- startMemTracking();
- startProfiling();
- while (true) {
- Tensor *batch = readDataSet(argv[2], bstart, batch_size);
- if (batch == nullptr)
- break;
-
- auto *result = main_procedure(argv[1], batch);
- if (argc == 4) {
- saveDataSet(argv[3], (Tensor *)result, bstart);
- llvm_hpvm_imgInvokeRtControl(
- result, nullptr, bstart, bstart + batch_size);
- } else {
- saveDataSet(argv[3], (Tensor *)result, bstart, 10);
- auto *gold_output = readDataSet(argv[4], bstart, batch_size, 1);
- llvm_hpvm_imgInvokeRtControl(
- result, gold_output, bstart, bstart + batch_size);
- }
- bstart += batch_size;
- freeBatchMemory();
- clearTensorMap();
- }
- stopProfiling();
- llvm_hpvm_clearRuntimeController();
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet2_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet2_promise.cpp
deleted file mode 100644
index 769182c419182fd8d6155fa665354af5d31f1fe1..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet2_promise.cpp
+++ /dev/null
@@ -1,503 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* conv2d_6_b, size_t conv2d_6_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(15, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, conv2d_6_w, conv2d_6_b, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 8, 2, 0);
- __visc__bindIn(var_4, 9, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
- __visc__bindIn(var_17, 22, 2, 0);
- __visc__bindIn(var_17, 23, 3, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 24, 2, 0);
- __visc__bindIn(var_18, 25, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 26, 2, 0);
- __visc__bindIn(var_21, 27, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
- __visc__bindIn(var_22, 28, 2, 0);
- __visc__bindIn(var_22, 29, 3, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- __visc__bindOut(var_23, 0, 0, 0);
- __visc__bindOut(var_23, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* conv2d_6_b;
- size_t conv2d_6_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/alexnet2_cifar10/");
-
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,64,32,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,128,64,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,128,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,128,128,3,3);
- std::string conv2d_6_b_path = dir_prefix + std::string("conv2d_6_b.bin");
- void* conv2d_6_b = readTrainedWeights(conv2d_6_b_path.c_str(), 0,1,128,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,2048,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0,10000,3,32,32);
- uint8_t* labels = readLabels(labels_path.c_str(),10000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->conv2d_6_b = conv2d_6_b;
- args->conv2d_6_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 10000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet_imagenet_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet_imagenet_promise.cpp
deleted file mode 100644
index 662235143ae3ffb374608ec43b8fbcd57e43d4b1..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet_imagenet_promise.cpp
+++ /dev/null
@@ -1,562 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 4, 4);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 3, 3, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 3, 3, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 3, 3, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes,
- void* dense_3_w, size_t dense_3_w_bytes,
- void* dense_3_b, size_t dense_3_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(17, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, dense_3_w, dense_3_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 10, 2, 0);
- __visc__bindIn(var_8, 11, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 12, 2, 0);
- __visc__bindIn(var_9, 13, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 14, 2, 0);
- __visc__bindIn(var_11, 15, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 16, 2, 0);
- __visc__bindIn(var_12, 17, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 22, 2, 0);
- __visc__bindIn(var_18, 23, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
- __visc__bindIn(var_19, 24, 2, 0);
- __visc__bindIn(var_19, 25, 3, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 26, 2, 0);
- __visc__bindIn(var_21, 27, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
- __visc__bindIn(var_22, 28, 2, 0);
- __visc__bindIn(var_22, 29, 3, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 30, 2, 0);
- __visc__bindIn(var_24, 31, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 32, 2, 0);
- __visc__bindIn(var_25, 33, 3, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- __visc__bindOut(var_26, 0, 0, 0);
- __visc__bindOut(var_26, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
- void* dense_3_w;
- size_t dense_3_w_bytes;
- void* dense_3_b;
- size_t dense_3_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("/shared/hsharif3/alexnet_imagenet_tune/");
- std::string input_path = dir_prefix + std::string("test_input.bin");
- std::string labels_path = dir_prefix + std::string("test_labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,64,3,11,11);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,192,64,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,192,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,384,192,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,384,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,256,384,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,256,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,9216,4096);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,4096,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,4096,4096);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,4096,1,1);
- std::string dense_3_w_path = dir_prefix + std::string("dense_3_w.bin");
- void* dense_3_w = readTrainedWeights(dense_3_w_path.c_str(), 0,1,1,4096,1000);
- std::string dense_3_b_path = dir_prefix + std::string("dense_3_b.bin");
- void* dense_3_b = readTrainedWeights(dense_3_b_path.c_str(), 0,1,1000,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0, 1000,3,224,224);
- //uint32_t* labels = readLabels2(labels_path.c_str(),6000);
-
- uint32_t* labels = readLabels3(labels_path.c_str(), 1000);
-
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
- args->dense_3_w = dense_3_w;
- args->dense_3_w_bytes = 0;
- args->dense_3_b = dense_3_b;
- args->dense_3_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy3(labels, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet_promise.cpp
deleted file mode 100644
index a7a2a9efba0c1e7c0e815b594db772159d9aa4be..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/alexnet_promise.cpp
+++ /dev/null
@@ -1,450 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 5, 5, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(13, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 10, 2, 0);
- __visc__bindIn(var_8, 11, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 12, 2, 0);
- __visc__bindIn(var_9, 13, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 14, 2, 0);
- __visc__bindIn(var_11, 15, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 16, 2, 0);
- __visc__bindIn(var_12, 17, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 22, 2, 0);
- __visc__bindIn(var_18, 23, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
- __visc__bindIn(var_19, 24, 2, 0);
- __visc__bindIn(var_19, 25, 3, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- __visc__bindOut(var_20, 0, 0, 0);
- __visc__bindOut(var_20, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/alexnet_cifar10/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0,5000,3,32,32);
- std::string labels_path = dir_prefix + std::string("labels.bin");
- uint8_t* labels = readLabels(labels_path.c_str(),5000);
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,64,3,11,11);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,192,64,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,192,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,384,192,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,384,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,256,384,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,256,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,4096,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
-
-
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 5000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/lenet_mnist_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/lenet_mnist_promise.cpp
deleted file mode 100644
index e1cf6d2c217c19534ea4f9c3d97d55d8e00cb7cd..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/lenet_mnist_promise.cpp
+++ /dev/null
@@ -1,334 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 2, 2, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_tanh(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(9, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 6, 2, 0);
- __visc__bindIn(var_4, 7, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
- __visc__bindIn(var_5, 8, 2, 0);
- __visc__bindIn(var_5, 9, 3, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 10, 2, 0);
- __visc__bindIn(var_8, 11, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 12, 2, 0);
- __visc__bindIn(var_9, 13, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 14, 2, 0);
- __visc__bindIn(var_11, 15, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 16, 2, 0);
- __visc__bindIn(var_12, 17, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
-
- __visc__bindOut(var_14, 0, 0, 0);
- __visc__bindOut(var_14, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/lenet_mnist/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels32.bin");
-
- std::string conv2d_1_w_path = dir_prefix + std::string("conv1.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,1,5,5);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv1_bias.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,5,5);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2_bias.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("fc1.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,3136,1024);
- std::string dense_1_b_path = dir_prefix + std::string("fc1_bias.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,1024,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("fc2.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_2_b_path = dir_prefix + std::string("fc2_bias.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0, 5000,1,28,28);
-
- uint32_t* labels = readLabels3(labels_path.c_str(), 5000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy3(labels, result);
-
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/mobilenet_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/mobilenet_promise.cpp
deleted file mode 100644
index a1f9fec42ff8a94d2bdc4a65c0ddc6373e2bfc87..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/mobilenet_promise.cpp
+++ /dev/null
@@ -1,2401 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 32);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 64);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 128);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 128);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_27_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 256);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_28_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_29_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_30_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_31_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_32_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_33_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 256);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_34_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_35_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_36_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_37_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_38_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_39_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 512);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_40_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_41_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_42_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_43_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_44_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_45_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 512);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_46_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_47_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_48_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_49_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_50_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_51_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 512);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_52_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_53_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_54_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_55_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_56_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_57_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 512);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_58_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_59_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_60_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_61_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_62_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_63_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 512);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_64_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_65_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_66_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_67_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_68_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_69_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 2, 2, 1, 512);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_70_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_71_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_72_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_73_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_74_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_75_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_group_convolution(t1, t2, 1, 1, 1, 1, 1, 1024);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_76_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_77_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_78_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_79_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2, void* t3, size_t bytes_t3, void* t4, size_t bytes_t4, void* t5, size_t bytes_t5) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(5, t1, t2, t3, t4, t5, 0);
-
- void *r = __visc__tensor_batchnorm(t1, t2, t3, t4, t5, 0.001);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_80_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_81_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_mean(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_82_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_83_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_84_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* batch_normalization_1_gamma, size_t batch_normalization_1_gamma_bytes,
- void* batch_normalization_1_beta, size_t batch_normalization_1_beta_bytes,
- void* batch_normalization_1_mean, size_t batch_normalization_1_mean_bytes,
- void* batch_normalization_1_variance, size_t batch_normalization_1_variance_bytes,
- void* depthwise_conv2d_1_w, size_t depthwise_conv2d_1_w_bytes,
- void* batch_normalization_2_gamma, size_t batch_normalization_2_gamma_bytes,
- void* batch_normalization_2_beta, size_t batch_normalization_2_beta_bytes,
- void* batch_normalization_2_mean, size_t batch_normalization_2_mean_bytes,
- void* batch_normalization_2_variance, size_t batch_normalization_2_variance_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* batch_normalization_3_gamma, size_t batch_normalization_3_gamma_bytes,
- void* batch_normalization_3_beta, size_t batch_normalization_3_beta_bytes,
- void* batch_normalization_3_mean, size_t batch_normalization_3_mean_bytes,
- void* batch_normalization_3_variance, size_t batch_normalization_3_variance_bytes,
- void* depthwise_conv2d_2_w, size_t depthwise_conv2d_2_w_bytes,
- void* batch_normalization_4_gamma, size_t batch_normalization_4_gamma_bytes,
- void* batch_normalization_4_beta, size_t batch_normalization_4_beta_bytes,
- void* batch_normalization_4_mean, size_t batch_normalization_4_mean_bytes,
- void* batch_normalization_4_variance, size_t batch_normalization_4_variance_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* batch_normalization_5_gamma, size_t batch_normalization_5_gamma_bytes,
- void* batch_normalization_5_beta, size_t batch_normalization_5_beta_bytes,
- void* batch_normalization_5_mean, size_t batch_normalization_5_mean_bytes,
- void* batch_normalization_5_variance, size_t batch_normalization_5_variance_bytes,
- void* depthwise_conv2d_3_w, size_t depthwise_conv2d_3_w_bytes,
- void* batch_normalization_6_gamma, size_t batch_normalization_6_gamma_bytes,
- void* batch_normalization_6_beta, size_t batch_normalization_6_beta_bytes,
- void* batch_normalization_6_mean, size_t batch_normalization_6_mean_bytes,
- void* batch_normalization_6_variance, size_t batch_normalization_6_variance_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* batch_normalization_7_gamma, size_t batch_normalization_7_gamma_bytes,
- void* batch_normalization_7_beta, size_t batch_normalization_7_beta_bytes,
- void* batch_normalization_7_mean, size_t batch_normalization_7_mean_bytes,
- void* batch_normalization_7_variance, size_t batch_normalization_7_variance_bytes,
- void* depthwise_conv2d_4_w, size_t depthwise_conv2d_4_w_bytes,
- void* batch_normalization_8_gamma, size_t batch_normalization_8_gamma_bytes,
- void* batch_normalization_8_beta, size_t batch_normalization_8_beta_bytes,
- void* batch_normalization_8_mean, size_t batch_normalization_8_mean_bytes,
- void* batch_normalization_8_variance, size_t batch_normalization_8_variance_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* batch_normalization_9_gamma, size_t batch_normalization_9_gamma_bytes,
- void* batch_normalization_9_beta, size_t batch_normalization_9_beta_bytes,
- void* batch_normalization_9_mean, size_t batch_normalization_9_mean_bytes,
- void* batch_normalization_9_variance, size_t batch_normalization_9_variance_bytes,
- void* depthwise_conv2d_5_w, size_t depthwise_conv2d_5_w_bytes,
- void* batch_normalization_10_gamma, size_t batch_normalization_10_gamma_bytes,
- void* batch_normalization_10_beta, size_t batch_normalization_10_beta_bytes,
- void* batch_normalization_10_mean, size_t batch_normalization_10_mean_bytes,
- void* batch_normalization_10_variance, size_t batch_normalization_10_variance_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* batch_normalization_11_gamma, size_t batch_normalization_11_gamma_bytes,
- void* batch_normalization_11_beta, size_t batch_normalization_11_beta_bytes,
- void* batch_normalization_11_mean, size_t batch_normalization_11_mean_bytes,
- void* batch_normalization_11_variance, size_t batch_normalization_11_variance_bytes,
- void* depthwise_conv2d_6_w, size_t depthwise_conv2d_6_w_bytes,
- void* batch_normalization_12_gamma, size_t batch_normalization_12_gamma_bytes,
- void* batch_normalization_12_beta, size_t batch_normalization_12_beta_bytes,
- void* batch_normalization_12_mean, size_t batch_normalization_12_mean_bytes,
- void* batch_normalization_12_variance, size_t batch_normalization_12_variance_bytes,
- void* conv2d_7_w, size_t conv2d_7_w_bytes,
- void* batch_normalization_13_gamma, size_t batch_normalization_13_gamma_bytes,
- void* batch_normalization_13_beta, size_t batch_normalization_13_beta_bytes,
- void* batch_normalization_13_mean, size_t batch_normalization_13_mean_bytes,
- void* batch_normalization_13_variance, size_t batch_normalization_13_variance_bytes,
- void* depthwise_conv2d_7_w, size_t depthwise_conv2d_7_w_bytes,
- void* batch_normalization_14_gamma, size_t batch_normalization_14_gamma_bytes,
- void* batch_normalization_14_beta, size_t batch_normalization_14_beta_bytes,
- void* batch_normalization_14_mean, size_t batch_normalization_14_mean_bytes,
- void* batch_normalization_14_variance, size_t batch_normalization_14_variance_bytes,
- void* conv2d_8_w, size_t conv2d_8_w_bytes,
- void* batch_normalization_15_gamma, size_t batch_normalization_15_gamma_bytes,
- void* batch_normalization_15_beta, size_t batch_normalization_15_beta_bytes,
- void* batch_normalization_15_mean, size_t batch_normalization_15_mean_bytes,
- void* batch_normalization_15_variance, size_t batch_normalization_15_variance_bytes,
- void* depthwise_conv2d_8_w, size_t depthwise_conv2d_8_w_bytes,
- void* batch_normalization_16_gamma, size_t batch_normalization_16_gamma_bytes,
- void* batch_normalization_16_beta, size_t batch_normalization_16_beta_bytes,
- void* batch_normalization_16_mean, size_t batch_normalization_16_mean_bytes,
- void* batch_normalization_16_variance, size_t batch_normalization_16_variance_bytes,
- void* conv2d_9_w, size_t conv2d_9_w_bytes,
- void* batch_normalization_17_gamma, size_t batch_normalization_17_gamma_bytes,
- void* batch_normalization_17_beta, size_t batch_normalization_17_beta_bytes,
- void* batch_normalization_17_mean, size_t batch_normalization_17_mean_bytes,
- void* batch_normalization_17_variance, size_t batch_normalization_17_variance_bytes,
- void* depthwise_conv2d_9_w, size_t depthwise_conv2d_9_w_bytes,
- void* batch_normalization_18_gamma, size_t batch_normalization_18_gamma_bytes,
- void* batch_normalization_18_beta, size_t batch_normalization_18_beta_bytes,
- void* batch_normalization_18_mean, size_t batch_normalization_18_mean_bytes,
- void* batch_normalization_18_variance, size_t batch_normalization_18_variance_bytes,
- void* conv2d_10_w, size_t conv2d_10_w_bytes,
- void* batch_normalization_19_gamma, size_t batch_normalization_19_gamma_bytes,
- void* batch_normalization_19_beta, size_t batch_normalization_19_beta_bytes,
- void* batch_normalization_19_mean, size_t batch_normalization_19_mean_bytes,
- void* batch_normalization_19_variance, size_t batch_normalization_19_variance_bytes,
- void* depthwise_conv2d_10_w, size_t depthwise_conv2d_10_w_bytes,
- void* batch_normalization_20_gamma, size_t batch_normalization_20_gamma_bytes,
- void* batch_normalization_20_beta, size_t batch_normalization_20_beta_bytes,
- void* batch_normalization_20_mean, size_t batch_normalization_20_mean_bytes,
- void* batch_normalization_20_variance, size_t batch_normalization_20_variance_bytes,
- void* conv2d_11_w, size_t conv2d_11_w_bytes,
- void* batch_normalization_21_gamma, size_t batch_normalization_21_gamma_bytes,
- void* batch_normalization_21_beta, size_t batch_normalization_21_beta_bytes,
- void* batch_normalization_21_mean, size_t batch_normalization_21_mean_bytes,
- void* batch_normalization_21_variance, size_t batch_normalization_21_variance_bytes,
- void* depthwise_conv2d_11_w, size_t depthwise_conv2d_11_w_bytes,
- void* batch_normalization_22_gamma, size_t batch_normalization_22_gamma_bytes,
- void* batch_normalization_22_beta, size_t batch_normalization_22_beta_bytes,
- void* batch_normalization_22_mean, size_t batch_normalization_22_mean_bytes,
- void* batch_normalization_22_variance, size_t batch_normalization_22_variance_bytes,
- void* conv2d_12_w, size_t conv2d_12_w_bytes,
- void* batch_normalization_23_gamma, size_t batch_normalization_23_gamma_bytes,
- void* batch_normalization_23_beta, size_t batch_normalization_23_beta_bytes,
- void* batch_normalization_23_mean, size_t batch_normalization_23_mean_bytes,
- void* batch_normalization_23_variance, size_t batch_normalization_23_variance_bytes,
- void* depthwise_conv2d_12_w, size_t depthwise_conv2d_12_w_bytes,
- void* batch_normalization_24_gamma, size_t batch_normalization_24_gamma_bytes,
- void* batch_normalization_24_beta, size_t batch_normalization_24_beta_bytes,
- void* batch_normalization_24_mean, size_t batch_normalization_24_mean_bytes,
- void* batch_normalization_24_variance, size_t batch_normalization_24_variance_bytes,
- void* conv2d_13_w, size_t conv2d_13_w_bytes,
- void* batch_normalization_25_gamma, size_t batch_normalization_25_gamma_bytes,
- void* batch_normalization_25_beta, size_t batch_normalization_25_beta_bytes,
- void* batch_normalization_25_mean, size_t batch_normalization_25_mean_bytes,
- void* batch_normalization_25_variance, size_t batch_normalization_25_variance_bytes,
- void* depthwise_conv2d_13_w, size_t depthwise_conv2d_13_w_bytes,
- void* batch_normalization_26_gamma, size_t batch_normalization_26_gamma_bytes,
- void* batch_normalization_26_beta, size_t batch_normalization_26_beta_bytes,
- void* batch_normalization_26_mean, size_t batch_normalization_26_mean_bytes,
- void* batch_normalization_26_variance, size_t batch_normalization_26_variance_bytes,
- void* conv2d_14_w, size_t conv2d_14_w_bytes,
- void* batch_normalization_27_gamma, size_t batch_normalization_27_gamma_bytes,
- void* batch_normalization_27_beta, size_t batch_normalization_27_beta_bytes,
- void* batch_normalization_27_mean, size_t batch_normalization_27_mean_bytes,
- void* batch_normalization_27_variance, size_t batch_normalization_27_variance_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(138, input, conv2d_1_w, batch_normalization_1_gamma, batch_normalization_1_beta, batch_normalization_1_mean, batch_normalization_1_variance, depthwise_conv2d_1_w, batch_normalization_2_gamma, batch_normalization_2_beta, batch_normalization_2_mean, batch_normalization_2_variance, conv2d_2_w, batch_normalization_3_gamma, batch_normalization_3_beta, batch_normalization_3_mean, batch_normalization_3_variance, depthwise_conv2d_2_w, batch_normalization_4_gamma, batch_normalization_4_beta, batch_normalization_4_mean, batch_normalization_4_variance, conv2d_3_w, batch_normalization_5_gamma, batch_normalization_5_beta, batch_normalization_5_mean, batch_normalization_5_variance, depthwise_conv2d_3_w, batch_normalization_6_gamma, batch_normalization_6_beta, batch_normalization_6_mean, batch_normalization_6_variance, conv2d_4_w, batch_normalization_7_gamma, batch_normalization_7_beta, batch_normalization_7_mean, batch_normalization_7_variance, depthwise_conv2d_4_w, batch_normalization_8_gamma, batch_normalization_8_beta, batch_normalization_8_mean, batch_normalization_8_variance, conv2d_5_w, batch_normalization_9_gamma, batch_normalization_9_beta, batch_normalization_9_mean, batch_normalization_9_variance, depthwise_conv2d_5_w, batch_normalization_10_gamma, batch_normalization_10_beta, batch_normalization_10_mean, batch_normalization_10_variance, conv2d_6_w, batch_normalization_11_gamma, batch_normalization_11_beta, batch_normalization_11_mean, batch_normalization_11_variance, depthwise_conv2d_6_w, batch_normalization_12_gamma, batch_normalization_12_beta, batch_normalization_12_mean, batch_normalization_12_variance, conv2d_7_w, batch_normalization_13_gamma, batch_normalization_13_beta, batch_normalization_13_mean, batch_normalization_13_variance, depthwise_conv2d_7_w, batch_normalization_14_gamma, batch_normalization_14_beta, batch_normalization_14_mean, batch_normalization_14_variance, conv2d_8_w, batch_normalization_15_gamma, batch_normalization_15_beta, batch_normalization_15_mean, batch_normalization_15_variance, depthwise_conv2d_8_w, batch_normalization_16_gamma, batch_normalization_16_beta, batch_normalization_16_mean, batch_normalization_16_variance, conv2d_9_w, batch_normalization_17_gamma, batch_normalization_17_beta, batch_normalization_17_mean, batch_normalization_17_variance, depthwise_conv2d_9_w, batch_normalization_18_gamma, batch_normalization_18_beta, batch_normalization_18_mean, batch_normalization_18_variance, conv2d_10_w, batch_normalization_19_gamma, batch_normalization_19_beta, batch_normalization_19_mean, batch_normalization_19_variance, depthwise_conv2d_10_w, batch_normalization_20_gamma, batch_normalization_20_beta, batch_normalization_20_mean, batch_normalization_20_variance, conv2d_11_w, batch_normalization_21_gamma, batch_normalization_21_beta, batch_normalization_21_mean, batch_normalization_21_variance, depthwise_conv2d_11_w, batch_normalization_22_gamma, batch_normalization_22_beta, batch_normalization_22_mean, batch_normalization_22_variance, conv2d_12_w, batch_normalization_23_gamma, batch_normalization_23_beta, batch_normalization_23_mean, batch_normalization_23_variance, depthwise_conv2d_12_w, batch_normalization_24_gamma, batch_normalization_24_beta, batch_normalization_24_mean, batch_normalization_24_variance, conv2d_13_w, batch_normalization_25_gamma, batch_normalization_25_beta, batch_normalization_25_mean, batch_normalization_25_variance, depthwise_conv2d_13_w, batch_normalization_26_gamma, batch_normalization_26_beta, batch_normalization_26_mean, batch_normalization_26_variance, conv2d_14_w, batch_normalization_27_gamma, batch_normalization_27_beta, batch_normalization_27_mean, batch_normalization_27_variance, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
- __visc__bindIn(var_1, 6, 4, 0);
- __visc__bindIn(var_1, 7, 5, 0);
- __visc__bindIn(var_1, 8, 6, 0);
- __visc__bindIn(var_1, 9, 7, 0);
- __visc__bindIn(var_1, 10, 8, 0);
- __visc__bindIn(var_1, 11, 9, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 12, 2, 0);
- __visc__bindIn(var_3, 13, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 14, 2, 0);
- __visc__bindIn(var_4, 15, 3, 0);
- __visc__bindIn(var_4, 16, 4, 0);
- __visc__bindIn(var_4, 17, 5, 0);
- __visc__bindIn(var_4, 18, 6, 0);
- __visc__bindIn(var_4, 19, 7, 0);
- __visc__bindIn(var_4, 20, 8, 0);
- __visc__bindIn(var_4, 21, 9, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
- __visc__bindIn(var_6, 22, 2, 0);
- __visc__bindIn(var_6, 23, 3, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 24, 2, 0);
- __visc__bindIn(var_7, 25, 3, 0);
- __visc__bindIn(var_7, 26, 4, 0);
- __visc__bindIn(var_7, 27, 5, 0);
- __visc__bindIn(var_7, 28, 6, 0);
- __visc__bindIn(var_7, 29, 7, 0);
- __visc__bindIn(var_7, 30, 8, 0);
- __visc__bindIn(var_7, 31, 9, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
- __visc__bindIn(var_9, 32, 2, 0);
- __visc__bindIn(var_9, 33, 3, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 34, 2, 0);
- __visc__bindIn(var_10, 35, 3, 0);
- __visc__bindIn(var_10, 36, 4, 0);
- __visc__bindIn(var_10, 37, 5, 0);
- __visc__bindIn(var_10, 38, 6, 0);
- __visc__bindIn(var_10, 39, 7, 0);
- __visc__bindIn(var_10, 40, 8, 0);
- __visc__bindIn(var_10, 41, 9, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
- __visc__bindIn(var_12, 42, 2, 0);
- __visc__bindIn(var_12, 43, 3, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 44, 2, 0);
- __visc__bindIn(var_13, 45, 3, 0);
- __visc__bindIn(var_13, 46, 4, 0);
- __visc__bindIn(var_13, 47, 5, 0);
- __visc__bindIn(var_13, 48, 6, 0);
- __visc__bindIn(var_13, 49, 7, 0);
- __visc__bindIn(var_13, 50, 8, 0);
- __visc__bindIn(var_13, 51, 9, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 52, 2, 0);
- __visc__bindIn(var_15, 53, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
- __visc__bindIn(var_16, 54, 2, 0);
- __visc__bindIn(var_16, 55, 3, 0);
- __visc__bindIn(var_16, 56, 4, 0);
- __visc__bindIn(var_16, 57, 5, 0);
- __visc__bindIn(var_16, 58, 6, 0);
- __visc__bindIn(var_16, 59, 7, 0);
- __visc__bindIn(var_16, 60, 8, 0);
- __visc__bindIn(var_16, 61, 9, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 62, 2, 0);
- __visc__bindIn(var_18, 63, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
- __visc__bindIn(var_19, 64, 2, 0);
- __visc__bindIn(var_19, 65, 3, 0);
- __visc__bindIn(var_19, 66, 4, 0);
- __visc__bindIn(var_19, 67, 5, 0);
- __visc__bindIn(var_19, 68, 6, 0);
- __visc__bindIn(var_19, 69, 7, 0);
- __visc__bindIn(var_19, 70, 8, 0);
- __visc__bindIn(var_19, 71, 9, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 72, 2, 0);
- __visc__bindIn(var_21, 73, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
- __visc__bindIn(var_22, 74, 2, 0);
- __visc__bindIn(var_22, 75, 3, 0);
- __visc__bindIn(var_22, 76, 4, 0);
- __visc__bindIn(var_22, 77, 5, 0);
- __visc__bindIn(var_22, 78, 6, 0);
- __visc__bindIn(var_22, 79, 7, 0);
- __visc__bindIn(var_22, 80, 8, 0);
- __visc__bindIn(var_22, 81, 9, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 82, 2, 0);
- __visc__bindIn(var_24, 83, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 84, 2, 0);
- __visc__bindIn(var_25, 85, 3, 0);
- __visc__bindIn(var_25, 86, 4, 0);
- __visc__bindIn(var_25, 87, 5, 0);
- __visc__bindIn(var_25, 88, 6, 0);
- __visc__bindIn(var_25, 89, 7, 0);
- __visc__bindIn(var_25, 90, 8, 0);
- __visc__bindIn(var_25, 91, 9, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- void* var_27 = __visc__createNodeND(0, var_27_node);
-
- __visc__edge(var_26, var_27, 1, 0, 0, 0);
- __visc__edge(var_26, var_27, 1, 1, 1, 0);
- __visc__bindIn(var_27, 92, 2, 0);
- __visc__bindIn(var_27, 93, 3, 0);
-
- void* var_28 = __visc__createNodeND(0, var_28_node);
-
- __visc__edge(var_27, var_28, 1, 0, 0, 0);
- __visc__edge(var_27, var_28, 1, 1, 1, 0);
- __visc__bindIn(var_28, 94, 2, 0);
- __visc__bindIn(var_28, 95, 3, 0);
- __visc__bindIn(var_28, 96, 4, 0);
- __visc__bindIn(var_28, 97, 5, 0);
- __visc__bindIn(var_28, 98, 6, 0);
- __visc__bindIn(var_28, 99, 7, 0);
- __visc__bindIn(var_28, 100, 8, 0);
- __visc__bindIn(var_28, 101, 9, 0);
-
- void* var_29 = __visc__createNodeND(0, var_29_node);
-
- __visc__edge(var_28, var_29, 1, 0, 0, 0);
- __visc__edge(var_28, var_29, 1, 1, 1, 0);
-
- void* var_30 = __visc__createNodeND(0, var_30_node);
-
- __visc__edge(var_29, var_30, 1, 0, 0, 0);
- __visc__edge(var_29, var_30, 1, 1, 1, 0);
- __visc__bindIn(var_30, 102, 2, 0);
- __visc__bindIn(var_30, 103, 3, 0);
-
- void* var_31 = __visc__createNodeND(0, var_31_node);
-
- __visc__edge(var_30, var_31, 1, 0, 0, 0);
- __visc__edge(var_30, var_31, 1, 1, 1, 0);
- __visc__bindIn(var_31, 104, 2, 0);
- __visc__bindIn(var_31, 105, 3, 0);
- __visc__bindIn(var_31, 106, 4, 0);
- __visc__bindIn(var_31, 107, 5, 0);
- __visc__bindIn(var_31, 108, 6, 0);
- __visc__bindIn(var_31, 109, 7, 0);
- __visc__bindIn(var_31, 110, 8, 0);
- __visc__bindIn(var_31, 111, 9, 0);
-
- void* var_32 = __visc__createNodeND(0, var_32_node);
-
- __visc__edge(var_31, var_32, 1, 0, 0, 0);
- __visc__edge(var_31, var_32, 1, 1, 1, 0);
-
- void* var_33 = __visc__createNodeND(0, var_33_node);
-
- __visc__edge(var_32, var_33, 1, 0, 0, 0);
- __visc__edge(var_32, var_33, 1, 1, 1, 0);
- __visc__bindIn(var_33, 112, 2, 0);
- __visc__bindIn(var_33, 113, 3, 0);
-
- void* var_34 = __visc__createNodeND(0, var_34_node);
-
- __visc__edge(var_33, var_34, 1, 0, 0, 0);
- __visc__edge(var_33, var_34, 1, 1, 1, 0);
- __visc__bindIn(var_34, 114, 2, 0);
- __visc__bindIn(var_34, 115, 3, 0);
- __visc__bindIn(var_34, 116, 4, 0);
- __visc__bindIn(var_34, 117, 5, 0);
- __visc__bindIn(var_34, 118, 6, 0);
- __visc__bindIn(var_34, 119, 7, 0);
- __visc__bindIn(var_34, 120, 8, 0);
- __visc__bindIn(var_34, 121, 9, 0);
-
- void* var_35 = __visc__createNodeND(0, var_35_node);
-
- __visc__edge(var_34, var_35, 1, 0, 0, 0);
- __visc__edge(var_34, var_35, 1, 1, 1, 0);
-
- void* var_36 = __visc__createNodeND(0, var_36_node);
-
- __visc__edge(var_35, var_36, 1, 0, 0, 0);
- __visc__edge(var_35, var_36, 1, 1, 1, 0);
- __visc__bindIn(var_36, 122, 2, 0);
- __visc__bindIn(var_36, 123, 3, 0);
-
- void* var_37 = __visc__createNodeND(0, var_37_node);
-
- __visc__edge(var_36, var_37, 1, 0, 0, 0);
- __visc__edge(var_36, var_37, 1, 1, 1, 0);
- __visc__bindIn(var_37, 124, 2, 0);
- __visc__bindIn(var_37, 125, 3, 0);
- __visc__bindIn(var_37, 126, 4, 0);
- __visc__bindIn(var_37, 127, 5, 0);
- __visc__bindIn(var_37, 128, 6, 0);
- __visc__bindIn(var_37, 129, 7, 0);
- __visc__bindIn(var_37, 130, 8, 0);
- __visc__bindIn(var_37, 131, 9, 0);
-
- void* var_38 = __visc__createNodeND(0, var_38_node);
-
- __visc__edge(var_37, var_38, 1, 0, 0, 0);
- __visc__edge(var_37, var_38, 1, 1, 1, 0);
-
- void* var_39 = __visc__createNodeND(0, var_39_node);
-
- __visc__edge(var_38, var_39, 1, 0, 0, 0);
- __visc__edge(var_38, var_39, 1, 1, 1, 0);
- __visc__bindIn(var_39, 132, 2, 0);
- __visc__bindIn(var_39, 133, 3, 0);
-
- void* var_40 = __visc__createNodeND(0, var_40_node);
-
- __visc__edge(var_39, var_40, 1, 0, 0, 0);
- __visc__edge(var_39, var_40, 1, 1, 1, 0);
- __visc__bindIn(var_40, 134, 2, 0);
- __visc__bindIn(var_40, 135, 3, 0);
- __visc__bindIn(var_40, 136, 4, 0);
- __visc__bindIn(var_40, 137, 5, 0);
- __visc__bindIn(var_40, 138, 6, 0);
- __visc__bindIn(var_40, 139, 7, 0);
- __visc__bindIn(var_40, 140, 8, 0);
- __visc__bindIn(var_40, 141, 9, 0);
-
- void* var_41 = __visc__createNodeND(0, var_41_node);
-
- __visc__edge(var_40, var_41, 1, 0, 0, 0);
- __visc__edge(var_40, var_41, 1, 1, 1, 0);
-
- void* var_42 = __visc__createNodeND(0, var_42_node);
-
- __visc__edge(var_41, var_42, 1, 0, 0, 0);
- __visc__edge(var_41, var_42, 1, 1, 1, 0);
- __visc__bindIn(var_42, 142, 2, 0);
- __visc__bindIn(var_42, 143, 3, 0);
-
- void* var_43 = __visc__createNodeND(0, var_43_node);
-
- __visc__edge(var_42, var_43, 1, 0, 0, 0);
- __visc__edge(var_42, var_43, 1, 1, 1, 0);
- __visc__bindIn(var_43, 144, 2, 0);
- __visc__bindIn(var_43, 145, 3, 0);
- __visc__bindIn(var_43, 146, 4, 0);
- __visc__bindIn(var_43, 147, 5, 0);
- __visc__bindIn(var_43, 148, 6, 0);
- __visc__bindIn(var_43, 149, 7, 0);
- __visc__bindIn(var_43, 150, 8, 0);
- __visc__bindIn(var_43, 151, 9, 0);
-
- void* var_44 = __visc__createNodeND(0, var_44_node);
-
- __visc__edge(var_43, var_44, 1, 0, 0, 0);
- __visc__edge(var_43, var_44, 1, 1, 1, 0);
-
- void* var_45 = __visc__createNodeND(0, var_45_node);
-
- __visc__edge(var_44, var_45, 1, 0, 0, 0);
- __visc__edge(var_44, var_45, 1, 1, 1, 0);
- __visc__bindIn(var_45, 152, 2, 0);
- __visc__bindIn(var_45, 153, 3, 0);
-
- void* var_46 = __visc__createNodeND(0, var_46_node);
-
- __visc__edge(var_45, var_46, 1, 0, 0, 0);
- __visc__edge(var_45, var_46, 1, 1, 1, 0);
- __visc__bindIn(var_46, 154, 2, 0);
- __visc__bindIn(var_46, 155, 3, 0);
- __visc__bindIn(var_46, 156, 4, 0);
- __visc__bindIn(var_46, 157, 5, 0);
- __visc__bindIn(var_46, 158, 6, 0);
- __visc__bindIn(var_46, 159, 7, 0);
- __visc__bindIn(var_46, 160, 8, 0);
- __visc__bindIn(var_46, 161, 9, 0);
-
- void* var_47 = __visc__createNodeND(0, var_47_node);
-
- __visc__edge(var_46, var_47, 1, 0, 0, 0);
- __visc__edge(var_46, var_47, 1, 1, 1, 0);
-
- void* var_48 = __visc__createNodeND(0, var_48_node);
-
- __visc__edge(var_47, var_48, 1, 0, 0, 0);
- __visc__edge(var_47, var_48, 1, 1, 1, 0);
- __visc__bindIn(var_48, 162, 2, 0);
- __visc__bindIn(var_48, 163, 3, 0);
-
- void* var_49 = __visc__createNodeND(0, var_49_node);
-
- __visc__edge(var_48, var_49, 1, 0, 0, 0);
- __visc__edge(var_48, var_49, 1, 1, 1, 0);
- __visc__bindIn(var_49, 164, 2, 0);
- __visc__bindIn(var_49, 165, 3, 0);
- __visc__bindIn(var_49, 166, 4, 0);
- __visc__bindIn(var_49, 167, 5, 0);
- __visc__bindIn(var_49, 168, 6, 0);
- __visc__bindIn(var_49, 169, 7, 0);
- __visc__bindIn(var_49, 170, 8, 0);
- __visc__bindIn(var_49, 171, 9, 0);
-
- void* var_50 = __visc__createNodeND(0, var_50_node);
-
- __visc__edge(var_49, var_50, 1, 0, 0, 0);
- __visc__edge(var_49, var_50, 1, 1, 1, 0);
-
- void* var_51 = __visc__createNodeND(0, var_51_node);
-
- __visc__edge(var_50, var_51, 1, 0, 0, 0);
- __visc__edge(var_50, var_51, 1, 1, 1, 0);
- __visc__bindIn(var_51, 172, 2, 0);
- __visc__bindIn(var_51, 173, 3, 0);
-
- void* var_52 = __visc__createNodeND(0, var_52_node);
-
- __visc__edge(var_51, var_52, 1, 0, 0, 0);
- __visc__edge(var_51, var_52, 1, 1, 1, 0);
- __visc__bindIn(var_52, 174, 2, 0);
- __visc__bindIn(var_52, 175, 3, 0);
- __visc__bindIn(var_52, 176, 4, 0);
- __visc__bindIn(var_52, 177, 5, 0);
- __visc__bindIn(var_52, 178, 6, 0);
- __visc__bindIn(var_52, 179, 7, 0);
- __visc__bindIn(var_52, 180, 8, 0);
- __visc__bindIn(var_52, 181, 9, 0);
-
- void* var_53 = __visc__createNodeND(0, var_53_node);
-
- __visc__edge(var_52, var_53, 1, 0, 0, 0);
- __visc__edge(var_52, var_53, 1, 1, 1, 0);
-
- void* var_54 = __visc__createNodeND(0, var_54_node);
-
- __visc__edge(var_53, var_54, 1, 0, 0, 0);
- __visc__edge(var_53, var_54, 1, 1, 1, 0);
- __visc__bindIn(var_54, 182, 2, 0);
- __visc__bindIn(var_54, 183, 3, 0);
-
- void* var_55 = __visc__createNodeND(0, var_55_node);
-
- __visc__edge(var_54, var_55, 1, 0, 0, 0);
- __visc__edge(var_54, var_55, 1, 1, 1, 0);
- __visc__bindIn(var_55, 184, 2, 0);
- __visc__bindIn(var_55, 185, 3, 0);
- __visc__bindIn(var_55, 186, 4, 0);
- __visc__bindIn(var_55, 187, 5, 0);
- __visc__bindIn(var_55, 188, 6, 0);
- __visc__bindIn(var_55, 189, 7, 0);
- __visc__bindIn(var_55, 190, 8, 0);
- __visc__bindIn(var_55, 191, 9, 0);
-
- void* var_56 = __visc__createNodeND(0, var_56_node);
-
- __visc__edge(var_55, var_56, 1, 0, 0, 0);
- __visc__edge(var_55, var_56, 1, 1, 1, 0);
-
- void* var_57 = __visc__createNodeND(0, var_57_node);
-
- __visc__edge(var_56, var_57, 1, 0, 0, 0);
- __visc__edge(var_56, var_57, 1, 1, 1, 0);
- __visc__bindIn(var_57, 192, 2, 0);
- __visc__bindIn(var_57, 193, 3, 0);
-
- void* var_58 = __visc__createNodeND(0, var_58_node);
-
- __visc__edge(var_57, var_58, 1, 0, 0, 0);
- __visc__edge(var_57, var_58, 1, 1, 1, 0);
- __visc__bindIn(var_58, 194, 2, 0);
- __visc__bindIn(var_58, 195, 3, 0);
- __visc__bindIn(var_58, 196, 4, 0);
- __visc__bindIn(var_58, 197, 5, 0);
- __visc__bindIn(var_58, 198, 6, 0);
- __visc__bindIn(var_58, 199, 7, 0);
- __visc__bindIn(var_58, 200, 8, 0);
- __visc__bindIn(var_58, 201, 9, 0);
-
- void* var_59 = __visc__createNodeND(0, var_59_node);
-
- __visc__edge(var_58, var_59, 1, 0, 0, 0);
- __visc__edge(var_58, var_59, 1, 1, 1, 0);
-
- void* var_60 = __visc__createNodeND(0, var_60_node);
-
- __visc__edge(var_59, var_60, 1, 0, 0, 0);
- __visc__edge(var_59, var_60, 1, 1, 1, 0);
- __visc__bindIn(var_60, 202, 2, 0);
- __visc__bindIn(var_60, 203, 3, 0);
-
- void* var_61 = __visc__createNodeND(0, var_61_node);
-
- __visc__edge(var_60, var_61, 1, 0, 0, 0);
- __visc__edge(var_60, var_61, 1, 1, 1, 0);
- __visc__bindIn(var_61, 204, 2, 0);
- __visc__bindIn(var_61, 205, 3, 0);
- __visc__bindIn(var_61, 206, 4, 0);
- __visc__bindIn(var_61, 207, 5, 0);
- __visc__bindIn(var_61, 208, 6, 0);
- __visc__bindIn(var_61, 209, 7, 0);
- __visc__bindIn(var_61, 210, 8, 0);
- __visc__bindIn(var_61, 211, 9, 0);
-
- void* var_62 = __visc__createNodeND(0, var_62_node);
-
- __visc__edge(var_61, var_62, 1, 0, 0, 0);
- __visc__edge(var_61, var_62, 1, 1, 1, 0);
-
- void* var_63 = __visc__createNodeND(0, var_63_node);
-
- __visc__edge(var_62, var_63, 1, 0, 0, 0);
- __visc__edge(var_62, var_63, 1, 1, 1, 0);
- __visc__bindIn(var_63, 212, 2, 0);
- __visc__bindIn(var_63, 213, 3, 0);
-
- void* var_64 = __visc__createNodeND(0, var_64_node);
-
- __visc__edge(var_63, var_64, 1, 0, 0, 0);
- __visc__edge(var_63, var_64, 1, 1, 1, 0);
- __visc__bindIn(var_64, 214, 2, 0);
- __visc__bindIn(var_64, 215, 3, 0);
- __visc__bindIn(var_64, 216, 4, 0);
- __visc__bindIn(var_64, 217, 5, 0);
- __visc__bindIn(var_64, 218, 6, 0);
- __visc__bindIn(var_64, 219, 7, 0);
- __visc__bindIn(var_64, 220, 8, 0);
- __visc__bindIn(var_64, 221, 9, 0);
-
- void* var_65 = __visc__createNodeND(0, var_65_node);
-
- __visc__edge(var_64, var_65, 1, 0, 0, 0);
- __visc__edge(var_64, var_65, 1, 1, 1, 0);
-
- void* var_66 = __visc__createNodeND(0, var_66_node);
-
- __visc__edge(var_65, var_66, 1, 0, 0, 0);
- __visc__edge(var_65, var_66, 1, 1, 1, 0);
- __visc__bindIn(var_66, 222, 2, 0);
- __visc__bindIn(var_66, 223, 3, 0);
-
- void* var_67 = __visc__createNodeND(0, var_67_node);
-
- __visc__edge(var_66, var_67, 1, 0, 0, 0);
- __visc__edge(var_66, var_67, 1, 1, 1, 0);
- __visc__bindIn(var_67, 224, 2, 0);
- __visc__bindIn(var_67, 225, 3, 0);
- __visc__bindIn(var_67, 226, 4, 0);
- __visc__bindIn(var_67, 227, 5, 0);
- __visc__bindIn(var_67, 228, 6, 0);
- __visc__bindIn(var_67, 229, 7, 0);
- __visc__bindIn(var_67, 230, 8, 0);
- __visc__bindIn(var_67, 231, 9, 0);
-
- void* var_68 = __visc__createNodeND(0, var_68_node);
-
- __visc__edge(var_67, var_68, 1, 0, 0, 0);
- __visc__edge(var_67, var_68, 1, 1, 1, 0);
-
- void* var_69 = __visc__createNodeND(0, var_69_node);
-
- __visc__edge(var_68, var_69, 1, 0, 0, 0);
- __visc__edge(var_68, var_69, 1, 1, 1, 0);
- __visc__bindIn(var_69, 232, 2, 0);
- __visc__bindIn(var_69, 233, 3, 0);
-
- void* var_70 = __visc__createNodeND(0, var_70_node);
-
- __visc__edge(var_69, var_70, 1, 0, 0, 0);
- __visc__edge(var_69, var_70, 1, 1, 1, 0);
- __visc__bindIn(var_70, 234, 2, 0);
- __visc__bindIn(var_70, 235, 3, 0);
- __visc__bindIn(var_70, 236, 4, 0);
- __visc__bindIn(var_70, 237, 5, 0);
- __visc__bindIn(var_70, 238, 6, 0);
- __visc__bindIn(var_70, 239, 7, 0);
- __visc__bindIn(var_70, 240, 8, 0);
- __visc__bindIn(var_70, 241, 9, 0);
-
- void* var_71 = __visc__createNodeND(0, var_71_node);
-
- __visc__edge(var_70, var_71, 1, 0, 0, 0);
- __visc__edge(var_70, var_71, 1, 1, 1, 0);
-
- void* var_72 = __visc__createNodeND(0, var_72_node);
-
- __visc__edge(var_71, var_72, 1, 0, 0, 0);
- __visc__edge(var_71, var_72, 1, 1, 1, 0);
- __visc__bindIn(var_72, 242, 2, 0);
- __visc__bindIn(var_72, 243, 3, 0);
-
- void* var_73 = __visc__createNodeND(0, var_73_node);
-
- __visc__edge(var_72, var_73, 1, 0, 0, 0);
- __visc__edge(var_72, var_73, 1, 1, 1, 0);
- __visc__bindIn(var_73, 244, 2, 0);
- __visc__bindIn(var_73, 245, 3, 0);
- __visc__bindIn(var_73, 246, 4, 0);
- __visc__bindIn(var_73, 247, 5, 0);
- __visc__bindIn(var_73, 248, 6, 0);
- __visc__bindIn(var_73, 249, 7, 0);
- __visc__bindIn(var_73, 250, 8, 0);
- __visc__bindIn(var_73, 251, 9, 0);
-
- void* var_74 = __visc__createNodeND(0, var_74_node);
-
- __visc__edge(var_73, var_74, 1, 0, 0, 0);
- __visc__edge(var_73, var_74, 1, 1, 1, 0);
-
- void* var_75 = __visc__createNodeND(0, var_75_node);
-
- __visc__edge(var_74, var_75, 1, 0, 0, 0);
- __visc__edge(var_74, var_75, 1, 1, 1, 0);
- __visc__bindIn(var_75, 252, 2, 0);
- __visc__bindIn(var_75, 253, 3, 0);
-
- void* var_76 = __visc__createNodeND(0, var_76_node);
-
- __visc__edge(var_75, var_76, 1, 0, 0, 0);
- __visc__edge(var_75, var_76, 1, 1, 1, 0);
- __visc__bindIn(var_76, 254, 2, 0);
- __visc__bindIn(var_76, 255, 3, 0);
- __visc__bindIn(var_76, 256, 4, 0);
- __visc__bindIn(var_76, 257, 5, 0);
- __visc__bindIn(var_76, 258, 6, 0);
- __visc__bindIn(var_76, 259, 7, 0);
- __visc__bindIn(var_76, 260, 8, 0);
- __visc__bindIn(var_76, 261, 9, 0);
-
- void* var_77 = __visc__createNodeND(0, var_77_node);
-
- __visc__edge(var_76, var_77, 1, 0, 0, 0);
- __visc__edge(var_76, var_77, 1, 1, 1, 0);
-
- void* var_78 = __visc__createNodeND(0, var_78_node);
-
- __visc__edge(var_77, var_78, 1, 0, 0, 0);
- __visc__edge(var_77, var_78, 1, 1, 1, 0);
- __visc__bindIn(var_78, 262, 2, 0);
- __visc__bindIn(var_78, 263, 3, 0);
-
- void* var_79 = __visc__createNodeND(0, var_79_node);
-
- __visc__edge(var_78, var_79, 1, 0, 0, 0);
- __visc__edge(var_78, var_79, 1, 1, 1, 0);
- __visc__bindIn(var_79, 264, 2, 0);
- __visc__bindIn(var_79, 265, 3, 0);
- __visc__bindIn(var_79, 266, 4, 0);
- __visc__bindIn(var_79, 267, 5, 0);
- __visc__bindIn(var_79, 268, 6, 0);
- __visc__bindIn(var_79, 269, 7, 0);
- __visc__bindIn(var_79, 270, 8, 0);
- __visc__bindIn(var_79, 271, 9, 0);
-
- void* var_80 = __visc__createNodeND(0, var_80_node);
-
- __visc__edge(var_79, var_80, 1, 0, 0, 0);
- __visc__edge(var_79, var_80, 1, 1, 1, 0);
-
- void* var_81 = __visc__createNodeND(0, var_81_node);
-
- __visc__edge(var_80, var_81, 1, 0, 0, 0);
- __visc__edge(var_80, var_81, 1, 1, 1, 0);
-
- void* var_82 = __visc__createNodeND(0, var_82_node);
-
- __visc__edge(var_81, var_82, 1, 0, 0, 0);
- __visc__edge(var_81, var_82, 1, 1, 1, 0);
- __visc__bindIn(var_82, 272, 2, 0);
- __visc__bindIn(var_82, 273, 3, 0);
-
- void* var_83 = __visc__createNodeND(0, var_83_node);
-
- __visc__edge(var_82, var_83, 1, 0, 0, 0);
- __visc__edge(var_82, var_83, 1, 1, 1, 0);
- __visc__bindIn(var_83, 274, 2, 0);
- __visc__bindIn(var_83, 275, 3, 0);
-
- void* var_84 = __visc__createNodeND(0, var_84_node);
-
- __visc__edge(var_83, var_84, 1, 0, 0, 0);
- __visc__edge(var_83, var_84, 1, 1, 1, 0);
-
- __visc__bindOut(var_84, 0, 0, 0);
- __visc__bindOut(var_84, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* batch_normalization_1_gamma;
- size_t batch_normalization_1_gamma_bytes;
- void* batch_normalization_1_beta;
- size_t batch_normalization_1_beta_bytes;
- void* batch_normalization_1_mean;
- size_t batch_normalization_1_mean_bytes;
- void* batch_normalization_1_variance;
- size_t batch_normalization_1_variance_bytes;
- void* depthwise_conv2d_1_w;
- size_t depthwise_conv2d_1_w_bytes;
- void* batch_normalization_2_gamma;
- size_t batch_normalization_2_gamma_bytes;
- void* batch_normalization_2_beta;
- size_t batch_normalization_2_beta_bytes;
- void* batch_normalization_2_mean;
- size_t batch_normalization_2_mean_bytes;
- void* batch_normalization_2_variance;
- size_t batch_normalization_2_variance_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* batch_normalization_3_gamma;
- size_t batch_normalization_3_gamma_bytes;
- void* batch_normalization_3_beta;
- size_t batch_normalization_3_beta_bytes;
- void* batch_normalization_3_mean;
- size_t batch_normalization_3_mean_bytes;
- void* batch_normalization_3_variance;
- size_t batch_normalization_3_variance_bytes;
- void* depthwise_conv2d_2_w;
- size_t depthwise_conv2d_2_w_bytes;
- void* batch_normalization_4_gamma;
- size_t batch_normalization_4_gamma_bytes;
- void* batch_normalization_4_beta;
- size_t batch_normalization_4_beta_bytes;
- void* batch_normalization_4_mean;
- size_t batch_normalization_4_mean_bytes;
- void* batch_normalization_4_variance;
- size_t batch_normalization_4_variance_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* batch_normalization_5_gamma;
- size_t batch_normalization_5_gamma_bytes;
- void* batch_normalization_5_beta;
- size_t batch_normalization_5_beta_bytes;
- void* batch_normalization_5_mean;
- size_t batch_normalization_5_mean_bytes;
- void* batch_normalization_5_variance;
- size_t batch_normalization_5_variance_bytes;
- void* depthwise_conv2d_3_w;
- size_t depthwise_conv2d_3_w_bytes;
- void* batch_normalization_6_gamma;
- size_t batch_normalization_6_gamma_bytes;
- void* batch_normalization_6_beta;
- size_t batch_normalization_6_beta_bytes;
- void* batch_normalization_6_mean;
- size_t batch_normalization_6_mean_bytes;
- void* batch_normalization_6_variance;
- size_t batch_normalization_6_variance_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* batch_normalization_7_gamma;
- size_t batch_normalization_7_gamma_bytes;
- void* batch_normalization_7_beta;
- size_t batch_normalization_7_beta_bytes;
- void* batch_normalization_7_mean;
- size_t batch_normalization_7_mean_bytes;
- void* batch_normalization_7_variance;
- size_t batch_normalization_7_variance_bytes;
- void* depthwise_conv2d_4_w;
- size_t depthwise_conv2d_4_w_bytes;
- void* batch_normalization_8_gamma;
- size_t batch_normalization_8_gamma_bytes;
- void* batch_normalization_8_beta;
- size_t batch_normalization_8_beta_bytes;
- void* batch_normalization_8_mean;
- size_t batch_normalization_8_mean_bytes;
- void* batch_normalization_8_variance;
- size_t batch_normalization_8_variance_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* batch_normalization_9_gamma;
- size_t batch_normalization_9_gamma_bytes;
- void* batch_normalization_9_beta;
- size_t batch_normalization_9_beta_bytes;
- void* batch_normalization_9_mean;
- size_t batch_normalization_9_mean_bytes;
- void* batch_normalization_9_variance;
- size_t batch_normalization_9_variance_bytes;
- void* depthwise_conv2d_5_w;
- size_t depthwise_conv2d_5_w_bytes;
- void* batch_normalization_10_gamma;
- size_t batch_normalization_10_gamma_bytes;
- void* batch_normalization_10_beta;
- size_t batch_normalization_10_beta_bytes;
- void* batch_normalization_10_mean;
- size_t batch_normalization_10_mean_bytes;
- void* batch_normalization_10_variance;
- size_t batch_normalization_10_variance_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* batch_normalization_11_gamma;
- size_t batch_normalization_11_gamma_bytes;
- void* batch_normalization_11_beta;
- size_t batch_normalization_11_beta_bytes;
- void* batch_normalization_11_mean;
- size_t batch_normalization_11_mean_bytes;
- void* batch_normalization_11_variance;
- size_t batch_normalization_11_variance_bytes;
- void* depthwise_conv2d_6_w;
- size_t depthwise_conv2d_6_w_bytes;
- void* batch_normalization_12_gamma;
- size_t batch_normalization_12_gamma_bytes;
- void* batch_normalization_12_beta;
- size_t batch_normalization_12_beta_bytes;
- void* batch_normalization_12_mean;
- size_t batch_normalization_12_mean_bytes;
- void* batch_normalization_12_variance;
- size_t batch_normalization_12_variance_bytes;
- void* conv2d_7_w;
- size_t conv2d_7_w_bytes;
- void* batch_normalization_13_gamma;
- size_t batch_normalization_13_gamma_bytes;
- void* batch_normalization_13_beta;
- size_t batch_normalization_13_beta_bytes;
- void* batch_normalization_13_mean;
- size_t batch_normalization_13_mean_bytes;
- void* batch_normalization_13_variance;
- size_t batch_normalization_13_variance_bytes;
- void* depthwise_conv2d_7_w;
- size_t depthwise_conv2d_7_w_bytes;
- void* batch_normalization_14_gamma;
- size_t batch_normalization_14_gamma_bytes;
- void* batch_normalization_14_beta;
- size_t batch_normalization_14_beta_bytes;
- void* batch_normalization_14_mean;
- size_t batch_normalization_14_mean_bytes;
- void* batch_normalization_14_variance;
- size_t batch_normalization_14_variance_bytes;
- void* conv2d_8_w;
- size_t conv2d_8_w_bytes;
- void* batch_normalization_15_gamma;
- size_t batch_normalization_15_gamma_bytes;
- void* batch_normalization_15_beta;
- size_t batch_normalization_15_beta_bytes;
- void* batch_normalization_15_mean;
- size_t batch_normalization_15_mean_bytes;
- void* batch_normalization_15_variance;
- size_t batch_normalization_15_variance_bytes;
- void* depthwise_conv2d_8_w;
- size_t depthwise_conv2d_8_w_bytes;
- void* batch_normalization_16_gamma;
- size_t batch_normalization_16_gamma_bytes;
- void* batch_normalization_16_beta;
- size_t batch_normalization_16_beta_bytes;
- void* batch_normalization_16_mean;
- size_t batch_normalization_16_mean_bytes;
- void* batch_normalization_16_variance;
- size_t batch_normalization_16_variance_bytes;
- void* conv2d_9_w;
- size_t conv2d_9_w_bytes;
- void* batch_normalization_17_gamma;
- size_t batch_normalization_17_gamma_bytes;
- void* batch_normalization_17_beta;
- size_t batch_normalization_17_beta_bytes;
- void* batch_normalization_17_mean;
- size_t batch_normalization_17_mean_bytes;
- void* batch_normalization_17_variance;
- size_t batch_normalization_17_variance_bytes;
- void* depthwise_conv2d_9_w;
- size_t depthwise_conv2d_9_w_bytes;
- void* batch_normalization_18_gamma;
- size_t batch_normalization_18_gamma_bytes;
- void* batch_normalization_18_beta;
- size_t batch_normalization_18_beta_bytes;
- void* batch_normalization_18_mean;
- size_t batch_normalization_18_mean_bytes;
- void* batch_normalization_18_variance;
- size_t batch_normalization_18_variance_bytes;
- void* conv2d_10_w;
- size_t conv2d_10_w_bytes;
- void* batch_normalization_19_gamma;
- size_t batch_normalization_19_gamma_bytes;
- void* batch_normalization_19_beta;
- size_t batch_normalization_19_beta_bytes;
- void* batch_normalization_19_mean;
- size_t batch_normalization_19_mean_bytes;
- void* batch_normalization_19_variance;
- size_t batch_normalization_19_variance_bytes;
- void* depthwise_conv2d_10_w;
- size_t depthwise_conv2d_10_w_bytes;
- void* batch_normalization_20_gamma;
- size_t batch_normalization_20_gamma_bytes;
- void* batch_normalization_20_beta;
- size_t batch_normalization_20_beta_bytes;
- void* batch_normalization_20_mean;
- size_t batch_normalization_20_mean_bytes;
- void* batch_normalization_20_variance;
- size_t batch_normalization_20_variance_bytes;
- void* conv2d_11_w;
- size_t conv2d_11_w_bytes;
- void* batch_normalization_21_gamma;
- size_t batch_normalization_21_gamma_bytes;
- void* batch_normalization_21_beta;
- size_t batch_normalization_21_beta_bytes;
- void* batch_normalization_21_mean;
- size_t batch_normalization_21_mean_bytes;
- void* batch_normalization_21_variance;
- size_t batch_normalization_21_variance_bytes;
- void* depthwise_conv2d_11_w;
- size_t depthwise_conv2d_11_w_bytes;
- void* batch_normalization_22_gamma;
- size_t batch_normalization_22_gamma_bytes;
- void* batch_normalization_22_beta;
- size_t batch_normalization_22_beta_bytes;
- void* batch_normalization_22_mean;
- size_t batch_normalization_22_mean_bytes;
- void* batch_normalization_22_variance;
- size_t batch_normalization_22_variance_bytes;
- void* conv2d_12_w;
- size_t conv2d_12_w_bytes;
- void* batch_normalization_23_gamma;
- size_t batch_normalization_23_gamma_bytes;
- void* batch_normalization_23_beta;
- size_t batch_normalization_23_beta_bytes;
- void* batch_normalization_23_mean;
- size_t batch_normalization_23_mean_bytes;
- void* batch_normalization_23_variance;
- size_t batch_normalization_23_variance_bytes;
- void* depthwise_conv2d_12_w;
- size_t depthwise_conv2d_12_w_bytes;
- void* batch_normalization_24_gamma;
- size_t batch_normalization_24_gamma_bytes;
- void* batch_normalization_24_beta;
- size_t batch_normalization_24_beta_bytes;
- void* batch_normalization_24_mean;
- size_t batch_normalization_24_mean_bytes;
- void* batch_normalization_24_variance;
- size_t batch_normalization_24_variance_bytes;
- void* conv2d_13_w;
- size_t conv2d_13_w_bytes;
- void* batch_normalization_25_gamma;
- size_t batch_normalization_25_gamma_bytes;
- void* batch_normalization_25_beta;
- size_t batch_normalization_25_beta_bytes;
- void* batch_normalization_25_mean;
- size_t batch_normalization_25_mean_bytes;
- void* batch_normalization_25_variance;
- size_t batch_normalization_25_variance_bytes;
- void* depthwise_conv2d_13_w;
- size_t depthwise_conv2d_13_w_bytes;
- void* batch_normalization_26_gamma;
- size_t batch_normalization_26_gamma_bytes;
- void* batch_normalization_26_beta;
- size_t batch_normalization_26_beta_bytes;
- void* batch_normalization_26_mean;
- size_t batch_normalization_26_mean_bytes;
- void* batch_normalization_26_variance;
- size_t batch_normalization_26_variance_bytes;
- void* conv2d_14_w;
- size_t conv2d_14_w_bytes;
- void* batch_normalization_27_gamma;
- size_t batch_normalization_27_gamma_bytes;
- void* batch_normalization_27_beta;
- size_t batch_normalization_27_beta_bytes;
- void* batch_normalization_27_mean;
- size_t batch_normalization_27_mean_bytes;
- void* batch_normalization_27_variance;
- size_t batch_normalization_27_variance_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/mobilenet_quant/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,32,3,3,3);
- std::string batch_normalization_1_gamma_path = dir_prefix + std::string("batch_normalization_1_gamma.bin");
- void* batch_normalization_1_gamma = readTrainedWeights(batch_normalization_1_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_beta_path = dir_prefix + std::string("batch_normalization_1_beta.bin");
- void* batch_normalization_1_beta = readTrainedWeights(batch_normalization_1_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_mean_path = dir_prefix + std::string("batch_normalization_1_mean.bin");
- void* batch_normalization_1_mean = readTrainedWeights(batch_normalization_1_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_1_variance_path = dir_prefix + std::string("batch_normalization_1_variance.bin");
- void* batch_normalization_1_variance = readTrainedWeights(batch_normalization_1_variance_path.c_str(), 0,1,32,1,1);
- std::string depthwise_conv2d_1_w_path = dir_prefix + std::string("depthwise_conv2d_1_w.bin");
- void* depthwise_conv2d_1_w = readTrainedWeights(depthwise_conv2d_1_w_path.c_str(), 0,32,1,3,3);
- std::string batch_normalization_2_gamma_path = dir_prefix + std::string("batch_normalization_2_gamma.bin");
- void* batch_normalization_2_gamma = readTrainedWeights(batch_normalization_2_gamma_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_beta_path = dir_prefix + std::string("batch_normalization_2_beta.bin");
- void* batch_normalization_2_beta = readTrainedWeights(batch_normalization_2_beta_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_mean_path = dir_prefix + std::string("batch_normalization_2_mean.bin");
- void* batch_normalization_2_mean = readTrainedWeights(batch_normalization_2_mean_path.c_str(), 0,1,32,1,1);
- std::string batch_normalization_2_variance_path = dir_prefix + std::string("batch_normalization_2_variance.bin");
- void* batch_normalization_2_variance = readTrainedWeights(batch_normalization_2_variance_path.c_str(), 0,1,32,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,32,1,1);
- std::string batch_normalization_3_gamma_path = dir_prefix + std::string("batch_normalization_3_gamma.bin");
- void* batch_normalization_3_gamma = readTrainedWeights(batch_normalization_3_gamma_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_beta_path = dir_prefix + std::string("batch_normalization_3_beta.bin");
- void* batch_normalization_3_beta = readTrainedWeights(batch_normalization_3_beta_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_mean_path = dir_prefix + std::string("batch_normalization_3_mean.bin");
- void* batch_normalization_3_mean = readTrainedWeights(batch_normalization_3_mean_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_3_variance_path = dir_prefix + std::string("batch_normalization_3_variance.bin");
- void* batch_normalization_3_variance = readTrainedWeights(batch_normalization_3_variance_path.c_str(), 0,1,64,1,1);
- std::string depthwise_conv2d_2_w_path = dir_prefix + std::string("depthwise_conv2d_2_w.bin");
- void* depthwise_conv2d_2_w = readTrainedWeights(depthwise_conv2d_2_w_path.c_str(), 0,64,1,3,3);
- std::string batch_normalization_4_gamma_path = dir_prefix + std::string("batch_normalization_4_gamma.bin");
- void* batch_normalization_4_gamma = readTrainedWeights(batch_normalization_4_gamma_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_beta_path = dir_prefix + std::string("batch_normalization_4_beta.bin");
- void* batch_normalization_4_beta = readTrainedWeights(batch_normalization_4_beta_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_mean_path = dir_prefix + std::string("batch_normalization_4_mean.bin");
- void* batch_normalization_4_mean = readTrainedWeights(batch_normalization_4_mean_path.c_str(), 0,1,64,1,1);
- std::string batch_normalization_4_variance_path = dir_prefix + std::string("batch_normalization_4_variance.bin");
- void* batch_normalization_4_variance = readTrainedWeights(batch_normalization_4_variance_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,128,64,1,1);
- std::string batch_normalization_5_gamma_path = dir_prefix + std::string("batch_normalization_5_gamma.bin");
- void* batch_normalization_5_gamma = readTrainedWeights(batch_normalization_5_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_beta_path = dir_prefix + std::string("batch_normalization_5_beta.bin");
- void* batch_normalization_5_beta = readTrainedWeights(batch_normalization_5_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_mean_path = dir_prefix + std::string("batch_normalization_5_mean.bin");
- void* batch_normalization_5_mean = readTrainedWeights(batch_normalization_5_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_5_variance_path = dir_prefix + std::string("batch_normalization_5_variance.bin");
- void* batch_normalization_5_variance = readTrainedWeights(batch_normalization_5_variance_path.c_str(), 0,1,128,1,1);
- std::string depthwise_conv2d_3_w_path = dir_prefix + std::string("depthwise_conv2d_3_w.bin");
- void* depthwise_conv2d_3_w = readTrainedWeights(depthwise_conv2d_3_w_path.c_str(), 0,128,1,3,3);
- std::string batch_normalization_6_gamma_path = dir_prefix + std::string("batch_normalization_6_gamma.bin");
- void* batch_normalization_6_gamma = readTrainedWeights(batch_normalization_6_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_beta_path = dir_prefix + std::string("batch_normalization_6_beta.bin");
- void* batch_normalization_6_beta = readTrainedWeights(batch_normalization_6_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_mean_path = dir_prefix + std::string("batch_normalization_6_mean.bin");
- void* batch_normalization_6_mean = readTrainedWeights(batch_normalization_6_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_6_variance_path = dir_prefix + std::string("batch_normalization_6_variance.bin");
- void* batch_normalization_6_variance = readTrainedWeights(batch_normalization_6_variance_path.c_str(), 0,1,128,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,128,128,1,1);
- std::string batch_normalization_7_gamma_path = dir_prefix + std::string("batch_normalization_7_gamma.bin");
- void* batch_normalization_7_gamma = readTrainedWeights(batch_normalization_7_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_beta_path = dir_prefix + std::string("batch_normalization_7_beta.bin");
- void* batch_normalization_7_beta = readTrainedWeights(batch_normalization_7_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_mean_path = dir_prefix + std::string("batch_normalization_7_mean.bin");
- void* batch_normalization_7_mean = readTrainedWeights(batch_normalization_7_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_7_variance_path = dir_prefix + std::string("batch_normalization_7_variance.bin");
- void* batch_normalization_7_variance = readTrainedWeights(batch_normalization_7_variance_path.c_str(), 0,1,128,1,1);
- std::string depthwise_conv2d_4_w_path = dir_prefix + std::string("depthwise_conv2d_4_w.bin");
- void* depthwise_conv2d_4_w = readTrainedWeights(depthwise_conv2d_4_w_path.c_str(), 0,128,1,3,3);
- std::string batch_normalization_8_gamma_path = dir_prefix + std::string("batch_normalization_8_gamma.bin");
- void* batch_normalization_8_gamma = readTrainedWeights(batch_normalization_8_gamma_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_beta_path = dir_prefix + std::string("batch_normalization_8_beta.bin");
- void* batch_normalization_8_beta = readTrainedWeights(batch_normalization_8_beta_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_mean_path = dir_prefix + std::string("batch_normalization_8_mean.bin");
- void* batch_normalization_8_mean = readTrainedWeights(batch_normalization_8_mean_path.c_str(), 0,1,128,1,1);
- std::string batch_normalization_8_variance_path = dir_prefix + std::string("batch_normalization_8_variance.bin");
- void* batch_normalization_8_variance = readTrainedWeights(batch_normalization_8_variance_path.c_str(), 0,1,128,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,128,1,1);
- std::string batch_normalization_9_gamma_path = dir_prefix + std::string("batch_normalization_9_gamma.bin");
- void* batch_normalization_9_gamma = readTrainedWeights(batch_normalization_9_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_beta_path = dir_prefix + std::string("batch_normalization_9_beta.bin");
- void* batch_normalization_9_beta = readTrainedWeights(batch_normalization_9_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_mean_path = dir_prefix + std::string("batch_normalization_9_mean.bin");
- void* batch_normalization_9_mean = readTrainedWeights(batch_normalization_9_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_9_variance_path = dir_prefix + std::string("batch_normalization_9_variance.bin");
- void* batch_normalization_9_variance = readTrainedWeights(batch_normalization_9_variance_path.c_str(), 0,1,256,1,1);
- std::string depthwise_conv2d_5_w_path = dir_prefix + std::string("depthwise_conv2d_5_w.bin");
- void* depthwise_conv2d_5_w = readTrainedWeights(depthwise_conv2d_5_w_path.c_str(), 0,256,1,3,3);
- std::string batch_normalization_10_gamma_path = dir_prefix + std::string("batch_normalization_10_gamma.bin");
- void* batch_normalization_10_gamma = readTrainedWeights(batch_normalization_10_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_beta_path = dir_prefix + std::string("batch_normalization_10_beta.bin");
- void* batch_normalization_10_beta = readTrainedWeights(batch_normalization_10_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_mean_path = dir_prefix + std::string("batch_normalization_10_mean.bin");
- void* batch_normalization_10_mean = readTrainedWeights(batch_normalization_10_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_10_variance_path = dir_prefix + std::string("batch_normalization_10_variance.bin");
- void* batch_normalization_10_variance = readTrainedWeights(batch_normalization_10_variance_path.c_str(), 0,1,256,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,256,256,1,1);
- std::string batch_normalization_11_gamma_path = dir_prefix + std::string("batch_normalization_11_gamma.bin");
- void* batch_normalization_11_gamma = readTrainedWeights(batch_normalization_11_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_beta_path = dir_prefix + std::string("batch_normalization_11_beta.bin");
- void* batch_normalization_11_beta = readTrainedWeights(batch_normalization_11_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_mean_path = dir_prefix + std::string("batch_normalization_11_mean.bin");
- void* batch_normalization_11_mean = readTrainedWeights(batch_normalization_11_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_11_variance_path = dir_prefix + std::string("batch_normalization_11_variance.bin");
- void* batch_normalization_11_variance = readTrainedWeights(batch_normalization_11_variance_path.c_str(), 0,1,256,1,1);
- std::string depthwise_conv2d_6_w_path = dir_prefix + std::string("depthwise_conv2d_6_w.bin");
- void* depthwise_conv2d_6_w = readTrainedWeights(depthwise_conv2d_6_w_path.c_str(), 0,256,1,3,3);
- std::string batch_normalization_12_gamma_path = dir_prefix + std::string("batch_normalization_12_gamma.bin");
- void* batch_normalization_12_gamma = readTrainedWeights(batch_normalization_12_gamma_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_beta_path = dir_prefix + std::string("batch_normalization_12_beta.bin");
- void* batch_normalization_12_beta = readTrainedWeights(batch_normalization_12_beta_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_mean_path = dir_prefix + std::string("batch_normalization_12_mean.bin");
- void* batch_normalization_12_mean = readTrainedWeights(batch_normalization_12_mean_path.c_str(), 0,1,256,1,1);
- std::string batch_normalization_12_variance_path = dir_prefix + std::string("batch_normalization_12_variance.bin");
- void* batch_normalization_12_variance = readTrainedWeights(batch_normalization_12_variance_path.c_str(), 0,1,256,1,1);
- std::string conv2d_7_w_path = dir_prefix + std::string("conv2d_7_w.bin");
- void* conv2d_7_w = readTrainedWeights(conv2d_7_w_path.c_str(), 0,512,256,1,1);
- std::string batch_normalization_13_gamma_path = dir_prefix + std::string("batch_normalization_13_gamma.bin");
- void* batch_normalization_13_gamma = readTrainedWeights(batch_normalization_13_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_beta_path = dir_prefix + std::string("batch_normalization_13_beta.bin");
- void* batch_normalization_13_beta = readTrainedWeights(batch_normalization_13_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_mean_path = dir_prefix + std::string("batch_normalization_13_mean.bin");
- void* batch_normalization_13_mean = readTrainedWeights(batch_normalization_13_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_13_variance_path = dir_prefix + std::string("batch_normalization_13_variance.bin");
- void* batch_normalization_13_variance = readTrainedWeights(batch_normalization_13_variance_path.c_str(), 0,1,512,1,1);
- std::string depthwise_conv2d_7_w_path = dir_prefix + std::string("depthwise_conv2d_7_w.bin");
- void* depthwise_conv2d_7_w = readTrainedWeights(depthwise_conv2d_7_w_path.c_str(), 0,512,1,3,3);
- std::string batch_normalization_14_gamma_path = dir_prefix + std::string("batch_normalization_14_gamma.bin");
- void* batch_normalization_14_gamma = readTrainedWeights(batch_normalization_14_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_14_beta_path = dir_prefix + std::string("batch_normalization_14_beta.bin");
- void* batch_normalization_14_beta = readTrainedWeights(batch_normalization_14_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_14_mean_path = dir_prefix + std::string("batch_normalization_14_mean.bin");
- void* batch_normalization_14_mean = readTrainedWeights(batch_normalization_14_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_14_variance_path = dir_prefix + std::string("batch_normalization_14_variance.bin");
- void* batch_normalization_14_variance = readTrainedWeights(batch_normalization_14_variance_path.c_str(), 0,1,512,1,1);
- std::string conv2d_8_w_path = dir_prefix + std::string("conv2d_8_w.bin");
- void* conv2d_8_w = readTrainedWeights(conv2d_8_w_path.c_str(), 0,512,512,1,1);
- std::string batch_normalization_15_gamma_path = dir_prefix + std::string("batch_normalization_15_gamma.bin");
- void* batch_normalization_15_gamma = readTrainedWeights(batch_normalization_15_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_15_beta_path = dir_prefix + std::string("batch_normalization_15_beta.bin");
- void* batch_normalization_15_beta = readTrainedWeights(batch_normalization_15_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_15_mean_path = dir_prefix + std::string("batch_normalization_15_mean.bin");
- void* batch_normalization_15_mean = readTrainedWeights(batch_normalization_15_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_15_variance_path = dir_prefix + std::string("batch_normalization_15_variance.bin");
- void* batch_normalization_15_variance = readTrainedWeights(batch_normalization_15_variance_path.c_str(), 0,1,512,1,1);
- std::string depthwise_conv2d_8_w_path = dir_prefix + std::string("depthwise_conv2d_8_w.bin");
- void* depthwise_conv2d_8_w = readTrainedWeights(depthwise_conv2d_8_w_path.c_str(), 0,512,1,3,3);
- std::string batch_normalization_16_gamma_path = dir_prefix + std::string("batch_normalization_16_gamma.bin");
- void* batch_normalization_16_gamma = readTrainedWeights(batch_normalization_16_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_16_beta_path = dir_prefix + std::string("batch_normalization_16_beta.bin");
- void* batch_normalization_16_beta = readTrainedWeights(batch_normalization_16_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_16_mean_path = dir_prefix + std::string("batch_normalization_16_mean.bin");
- void* batch_normalization_16_mean = readTrainedWeights(batch_normalization_16_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_16_variance_path = dir_prefix + std::string("batch_normalization_16_variance.bin");
- void* batch_normalization_16_variance = readTrainedWeights(batch_normalization_16_variance_path.c_str(), 0,1,512,1,1);
- std::string conv2d_9_w_path = dir_prefix + std::string("conv2d_9_w.bin");
- void* conv2d_9_w = readTrainedWeights(conv2d_9_w_path.c_str(), 0,512,512,1,1);
- std::string batch_normalization_17_gamma_path = dir_prefix + std::string("batch_normalization_17_gamma.bin");
- void* batch_normalization_17_gamma = readTrainedWeights(batch_normalization_17_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_17_beta_path = dir_prefix + std::string("batch_normalization_17_beta.bin");
- void* batch_normalization_17_beta = readTrainedWeights(batch_normalization_17_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_17_mean_path = dir_prefix + std::string("batch_normalization_17_mean.bin");
- void* batch_normalization_17_mean = readTrainedWeights(batch_normalization_17_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_17_variance_path = dir_prefix + std::string("batch_normalization_17_variance.bin");
- void* batch_normalization_17_variance = readTrainedWeights(batch_normalization_17_variance_path.c_str(), 0,1,512,1,1);
- std::string depthwise_conv2d_9_w_path = dir_prefix + std::string("depthwise_conv2d_9_w.bin");
- void* depthwise_conv2d_9_w = readTrainedWeights(depthwise_conv2d_9_w_path.c_str(), 0,512,1,3,3);
- std::string batch_normalization_18_gamma_path = dir_prefix + std::string("batch_normalization_18_gamma.bin");
- void* batch_normalization_18_gamma = readTrainedWeights(batch_normalization_18_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_18_beta_path = dir_prefix + std::string("batch_normalization_18_beta.bin");
- void* batch_normalization_18_beta = readTrainedWeights(batch_normalization_18_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_18_mean_path = dir_prefix + std::string("batch_normalization_18_mean.bin");
- void* batch_normalization_18_mean = readTrainedWeights(batch_normalization_18_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_18_variance_path = dir_prefix + std::string("batch_normalization_18_variance.bin");
- void* batch_normalization_18_variance = readTrainedWeights(batch_normalization_18_variance_path.c_str(), 0,1,512,1,1);
- std::string conv2d_10_w_path = dir_prefix + std::string("conv2d_10_w.bin");
- void* conv2d_10_w = readTrainedWeights(conv2d_10_w_path.c_str(), 0,512,512,1,1);
- std::string batch_normalization_19_gamma_path = dir_prefix + std::string("batch_normalization_19_gamma.bin");
- void* batch_normalization_19_gamma = readTrainedWeights(batch_normalization_19_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_19_beta_path = dir_prefix + std::string("batch_normalization_19_beta.bin");
- void* batch_normalization_19_beta = readTrainedWeights(batch_normalization_19_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_19_mean_path = dir_prefix + std::string("batch_normalization_19_mean.bin");
- void* batch_normalization_19_mean = readTrainedWeights(batch_normalization_19_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_19_variance_path = dir_prefix + std::string("batch_normalization_19_variance.bin");
- void* batch_normalization_19_variance = readTrainedWeights(batch_normalization_19_variance_path.c_str(), 0,1,512,1,1);
- std::string depthwise_conv2d_10_w_path = dir_prefix + std::string("depthwise_conv2d_10_w.bin");
- void* depthwise_conv2d_10_w = readTrainedWeights(depthwise_conv2d_10_w_path.c_str(), 0,512,1,3,3);
- std::string batch_normalization_20_gamma_path = dir_prefix + std::string("batch_normalization_20_gamma.bin");
- void* batch_normalization_20_gamma = readTrainedWeights(batch_normalization_20_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_20_beta_path = dir_prefix + std::string("batch_normalization_20_beta.bin");
- void* batch_normalization_20_beta = readTrainedWeights(batch_normalization_20_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_20_mean_path = dir_prefix + std::string("batch_normalization_20_mean.bin");
- void* batch_normalization_20_mean = readTrainedWeights(batch_normalization_20_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_20_variance_path = dir_prefix + std::string("batch_normalization_20_variance.bin");
- void* batch_normalization_20_variance = readTrainedWeights(batch_normalization_20_variance_path.c_str(), 0,1,512,1,1);
- std::string conv2d_11_w_path = dir_prefix + std::string("conv2d_11_w.bin");
- void* conv2d_11_w = readTrainedWeights(conv2d_11_w_path.c_str(), 0,512,512,1,1);
- std::string batch_normalization_21_gamma_path = dir_prefix + std::string("batch_normalization_21_gamma.bin");
- void* batch_normalization_21_gamma = readTrainedWeights(batch_normalization_21_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_21_beta_path = dir_prefix + std::string("batch_normalization_21_beta.bin");
- void* batch_normalization_21_beta = readTrainedWeights(batch_normalization_21_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_21_mean_path = dir_prefix + std::string("batch_normalization_21_mean.bin");
- void* batch_normalization_21_mean = readTrainedWeights(batch_normalization_21_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_21_variance_path = dir_prefix + std::string("batch_normalization_21_variance.bin");
- void* batch_normalization_21_variance = readTrainedWeights(batch_normalization_21_variance_path.c_str(), 0,1,512,1,1);
- std::string depthwise_conv2d_11_w_path = dir_prefix + std::string("depthwise_conv2d_11_w.bin");
- void* depthwise_conv2d_11_w = readTrainedWeights(depthwise_conv2d_11_w_path.c_str(), 0,512,1,3,3);
- std::string batch_normalization_22_gamma_path = dir_prefix + std::string("batch_normalization_22_gamma.bin");
- void* batch_normalization_22_gamma = readTrainedWeights(batch_normalization_22_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_22_beta_path = dir_prefix + std::string("batch_normalization_22_beta.bin");
- void* batch_normalization_22_beta = readTrainedWeights(batch_normalization_22_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_22_mean_path = dir_prefix + std::string("batch_normalization_22_mean.bin");
- void* batch_normalization_22_mean = readTrainedWeights(batch_normalization_22_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_22_variance_path = dir_prefix + std::string("batch_normalization_22_variance.bin");
- void* batch_normalization_22_variance = readTrainedWeights(batch_normalization_22_variance_path.c_str(), 0,1,512,1,1);
- std::string conv2d_12_w_path = dir_prefix + std::string("conv2d_12_w.bin");
- void* conv2d_12_w = readTrainedWeights(conv2d_12_w_path.c_str(), 0,512,512,1,1);
- std::string batch_normalization_23_gamma_path = dir_prefix + std::string("batch_normalization_23_gamma.bin");
- void* batch_normalization_23_gamma = readTrainedWeights(batch_normalization_23_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_23_beta_path = dir_prefix + std::string("batch_normalization_23_beta.bin");
- void* batch_normalization_23_beta = readTrainedWeights(batch_normalization_23_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_23_mean_path = dir_prefix + std::string("batch_normalization_23_mean.bin");
- void* batch_normalization_23_mean = readTrainedWeights(batch_normalization_23_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_23_variance_path = dir_prefix + std::string("batch_normalization_23_variance.bin");
- void* batch_normalization_23_variance = readTrainedWeights(batch_normalization_23_variance_path.c_str(), 0,1,512,1,1);
- std::string depthwise_conv2d_12_w_path = dir_prefix + std::string("depthwise_conv2d_12_w.bin");
- void* depthwise_conv2d_12_w = readTrainedWeights(depthwise_conv2d_12_w_path.c_str(), 0,512,1,3,3);
- std::string batch_normalization_24_gamma_path = dir_prefix + std::string("batch_normalization_24_gamma.bin");
- void* batch_normalization_24_gamma = readTrainedWeights(batch_normalization_24_gamma_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_24_beta_path = dir_prefix + std::string("batch_normalization_24_beta.bin");
- void* batch_normalization_24_beta = readTrainedWeights(batch_normalization_24_beta_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_24_mean_path = dir_prefix + std::string("batch_normalization_24_mean.bin");
- void* batch_normalization_24_mean = readTrainedWeights(batch_normalization_24_mean_path.c_str(), 0,1,512,1,1);
- std::string batch_normalization_24_variance_path = dir_prefix + std::string("batch_normalization_24_variance.bin");
- void* batch_normalization_24_variance = readTrainedWeights(batch_normalization_24_variance_path.c_str(), 0,1,512,1,1);
- std::string conv2d_13_w_path = dir_prefix + std::string("conv2d_13_w.bin");
- void* conv2d_13_w = readTrainedWeights(conv2d_13_w_path.c_str(), 0,1024,512,1,1);
- std::string batch_normalization_25_gamma_path = dir_prefix + std::string("batch_normalization_25_gamma.bin");
- void* batch_normalization_25_gamma = readTrainedWeights(batch_normalization_25_gamma_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_25_beta_path = dir_prefix + std::string("batch_normalization_25_beta.bin");
- void* batch_normalization_25_beta = readTrainedWeights(batch_normalization_25_beta_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_25_mean_path = dir_prefix + std::string("batch_normalization_25_mean.bin");
- void* batch_normalization_25_mean = readTrainedWeights(batch_normalization_25_mean_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_25_variance_path = dir_prefix + std::string("batch_normalization_25_variance.bin");
- void* batch_normalization_25_variance = readTrainedWeights(batch_normalization_25_variance_path.c_str(), 0,1,1024,1,1);
- std::string depthwise_conv2d_13_w_path = dir_prefix + std::string("depthwise_conv2d_13_w.bin");
- void* depthwise_conv2d_13_w = readTrainedWeights(depthwise_conv2d_13_w_path.c_str(), 0,1024,1,3,3);
- std::string batch_normalization_26_gamma_path = dir_prefix + std::string("batch_normalization_26_gamma.bin");
- void* batch_normalization_26_gamma = readTrainedWeights(batch_normalization_26_gamma_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_26_beta_path = dir_prefix + std::string("batch_normalization_26_beta.bin");
- void* batch_normalization_26_beta = readTrainedWeights(batch_normalization_26_beta_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_26_mean_path = dir_prefix + std::string("batch_normalization_26_mean.bin");
- void* batch_normalization_26_mean = readTrainedWeights(batch_normalization_26_mean_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_26_variance_path = dir_prefix + std::string("batch_normalization_26_variance.bin");
- void* batch_normalization_26_variance = readTrainedWeights(batch_normalization_26_variance_path.c_str(), 0,1,1024,1,1);
- std::string conv2d_14_w_path = dir_prefix + std::string("conv2d_14_w.bin");
- void* conv2d_14_w = readTrainedWeights(conv2d_14_w_path.c_str(), 0,1024,1024,1,1);
- std::string batch_normalization_27_gamma_path = dir_prefix + std::string("batch_normalization_27_gamma.bin");
- void* batch_normalization_27_gamma = readTrainedWeights(batch_normalization_27_gamma_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_27_beta_path = dir_prefix + std::string("batch_normalization_27_beta.bin");
- void* batch_normalization_27_beta = readTrainedWeights(batch_normalization_27_beta_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_27_mean_path = dir_prefix + std::string("batch_normalization_27_mean.bin");
- void* batch_normalization_27_mean = readTrainedWeights(batch_normalization_27_mean_path.c_str(), 0,1,1024,1,1);
- std::string batch_normalization_27_variance_path = dir_prefix + std::string("batch_normalization_27_variance.bin");
- void* batch_normalization_27_variance = readTrainedWeights(batch_normalization_27_variance_path.c_str(), 0,1,1024,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,1024,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0, 5000,3,32,32);
- uint8_t* labels = readLabels(labels_path.c_str(), 5000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->batch_normalization_1_gamma = batch_normalization_1_gamma;
- args->batch_normalization_1_gamma_bytes = 0;
- args->batch_normalization_1_beta = batch_normalization_1_beta;
- args->batch_normalization_1_beta_bytes = 0;
- args->batch_normalization_1_mean = batch_normalization_1_mean;
- args->batch_normalization_1_mean_bytes = 0;
- args->batch_normalization_1_variance = batch_normalization_1_variance;
- args->batch_normalization_1_variance_bytes = 0;
- args->depthwise_conv2d_1_w = depthwise_conv2d_1_w;
- args->depthwise_conv2d_1_w_bytes = 0;
- args->batch_normalization_2_gamma = batch_normalization_2_gamma;
- args->batch_normalization_2_gamma_bytes = 0;
- args->batch_normalization_2_beta = batch_normalization_2_beta;
- args->batch_normalization_2_beta_bytes = 0;
- args->batch_normalization_2_mean = batch_normalization_2_mean;
- args->batch_normalization_2_mean_bytes = 0;
- args->batch_normalization_2_variance = batch_normalization_2_variance;
- args->batch_normalization_2_variance_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->batch_normalization_3_gamma = batch_normalization_3_gamma;
- args->batch_normalization_3_gamma_bytes = 0;
- args->batch_normalization_3_beta = batch_normalization_3_beta;
- args->batch_normalization_3_beta_bytes = 0;
- args->batch_normalization_3_mean = batch_normalization_3_mean;
- args->batch_normalization_3_mean_bytes = 0;
- args->batch_normalization_3_variance = batch_normalization_3_variance;
- args->batch_normalization_3_variance_bytes = 0;
- args->depthwise_conv2d_2_w = depthwise_conv2d_2_w;
- args->depthwise_conv2d_2_w_bytes = 0;
- args->batch_normalization_4_gamma = batch_normalization_4_gamma;
- args->batch_normalization_4_gamma_bytes = 0;
- args->batch_normalization_4_beta = batch_normalization_4_beta;
- args->batch_normalization_4_beta_bytes = 0;
- args->batch_normalization_4_mean = batch_normalization_4_mean;
- args->batch_normalization_4_mean_bytes = 0;
- args->batch_normalization_4_variance = batch_normalization_4_variance;
- args->batch_normalization_4_variance_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->batch_normalization_5_gamma = batch_normalization_5_gamma;
- args->batch_normalization_5_gamma_bytes = 0;
- args->batch_normalization_5_beta = batch_normalization_5_beta;
- args->batch_normalization_5_beta_bytes = 0;
- args->batch_normalization_5_mean = batch_normalization_5_mean;
- args->batch_normalization_5_mean_bytes = 0;
- args->batch_normalization_5_variance = batch_normalization_5_variance;
- args->batch_normalization_5_variance_bytes = 0;
- args->depthwise_conv2d_3_w = depthwise_conv2d_3_w;
- args->depthwise_conv2d_3_w_bytes = 0;
- args->batch_normalization_6_gamma = batch_normalization_6_gamma;
- args->batch_normalization_6_gamma_bytes = 0;
- args->batch_normalization_6_beta = batch_normalization_6_beta;
- args->batch_normalization_6_beta_bytes = 0;
- args->batch_normalization_6_mean = batch_normalization_6_mean;
- args->batch_normalization_6_mean_bytes = 0;
- args->batch_normalization_6_variance = batch_normalization_6_variance;
- args->batch_normalization_6_variance_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->batch_normalization_7_gamma = batch_normalization_7_gamma;
- args->batch_normalization_7_gamma_bytes = 0;
- args->batch_normalization_7_beta = batch_normalization_7_beta;
- args->batch_normalization_7_beta_bytes = 0;
- args->batch_normalization_7_mean = batch_normalization_7_mean;
- args->batch_normalization_7_mean_bytes = 0;
- args->batch_normalization_7_variance = batch_normalization_7_variance;
- args->batch_normalization_7_variance_bytes = 0;
- args->depthwise_conv2d_4_w = depthwise_conv2d_4_w;
- args->depthwise_conv2d_4_w_bytes = 0;
- args->batch_normalization_8_gamma = batch_normalization_8_gamma;
- args->batch_normalization_8_gamma_bytes = 0;
- args->batch_normalization_8_beta = batch_normalization_8_beta;
- args->batch_normalization_8_beta_bytes = 0;
- args->batch_normalization_8_mean = batch_normalization_8_mean;
- args->batch_normalization_8_mean_bytes = 0;
- args->batch_normalization_8_variance = batch_normalization_8_variance;
- args->batch_normalization_8_variance_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->batch_normalization_9_gamma = batch_normalization_9_gamma;
- args->batch_normalization_9_gamma_bytes = 0;
- args->batch_normalization_9_beta = batch_normalization_9_beta;
- args->batch_normalization_9_beta_bytes = 0;
- args->batch_normalization_9_mean = batch_normalization_9_mean;
- args->batch_normalization_9_mean_bytes = 0;
- args->batch_normalization_9_variance = batch_normalization_9_variance;
- args->batch_normalization_9_variance_bytes = 0;
- args->depthwise_conv2d_5_w = depthwise_conv2d_5_w;
- args->depthwise_conv2d_5_w_bytes = 0;
- args->batch_normalization_10_gamma = batch_normalization_10_gamma;
- args->batch_normalization_10_gamma_bytes = 0;
- args->batch_normalization_10_beta = batch_normalization_10_beta;
- args->batch_normalization_10_beta_bytes = 0;
- args->batch_normalization_10_mean = batch_normalization_10_mean;
- args->batch_normalization_10_mean_bytes = 0;
- args->batch_normalization_10_variance = batch_normalization_10_variance;
- args->batch_normalization_10_variance_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->batch_normalization_11_gamma = batch_normalization_11_gamma;
- args->batch_normalization_11_gamma_bytes = 0;
- args->batch_normalization_11_beta = batch_normalization_11_beta;
- args->batch_normalization_11_beta_bytes = 0;
- args->batch_normalization_11_mean = batch_normalization_11_mean;
- args->batch_normalization_11_mean_bytes = 0;
- args->batch_normalization_11_variance = batch_normalization_11_variance;
- args->batch_normalization_11_variance_bytes = 0;
- args->depthwise_conv2d_6_w = depthwise_conv2d_6_w;
- args->depthwise_conv2d_6_w_bytes = 0;
- args->batch_normalization_12_gamma = batch_normalization_12_gamma;
- args->batch_normalization_12_gamma_bytes = 0;
- args->batch_normalization_12_beta = batch_normalization_12_beta;
- args->batch_normalization_12_beta_bytes = 0;
- args->batch_normalization_12_mean = batch_normalization_12_mean;
- args->batch_normalization_12_mean_bytes = 0;
- args->batch_normalization_12_variance = batch_normalization_12_variance;
- args->batch_normalization_12_variance_bytes = 0;
- args->conv2d_7_w = conv2d_7_w;
- args->conv2d_7_w_bytes = 0;
- args->batch_normalization_13_gamma = batch_normalization_13_gamma;
- args->batch_normalization_13_gamma_bytes = 0;
- args->batch_normalization_13_beta = batch_normalization_13_beta;
- args->batch_normalization_13_beta_bytes = 0;
- args->batch_normalization_13_mean = batch_normalization_13_mean;
- args->batch_normalization_13_mean_bytes = 0;
- args->batch_normalization_13_variance = batch_normalization_13_variance;
- args->batch_normalization_13_variance_bytes = 0;
- args->depthwise_conv2d_7_w = depthwise_conv2d_7_w;
- args->depthwise_conv2d_7_w_bytes = 0;
- args->batch_normalization_14_gamma = batch_normalization_14_gamma;
- args->batch_normalization_14_gamma_bytes = 0;
- args->batch_normalization_14_beta = batch_normalization_14_beta;
- args->batch_normalization_14_beta_bytes = 0;
- args->batch_normalization_14_mean = batch_normalization_14_mean;
- args->batch_normalization_14_mean_bytes = 0;
- args->batch_normalization_14_variance = batch_normalization_14_variance;
- args->batch_normalization_14_variance_bytes = 0;
- args->conv2d_8_w = conv2d_8_w;
- args->conv2d_8_w_bytes = 0;
- args->batch_normalization_15_gamma = batch_normalization_15_gamma;
- args->batch_normalization_15_gamma_bytes = 0;
- args->batch_normalization_15_beta = batch_normalization_15_beta;
- args->batch_normalization_15_beta_bytes = 0;
- args->batch_normalization_15_mean = batch_normalization_15_mean;
- args->batch_normalization_15_mean_bytes = 0;
- args->batch_normalization_15_variance = batch_normalization_15_variance;
- args->batch_normalization_15_variance_bytes = 0;
- args->depthwise_conv2d_8_w = depthwise_conv2d_8_w;
- args->depthwise_conv2d_8_w_bytes = 0;
- args->batch_normalization_16_gamma = batch_normalization_16_gamma;
- args->batch_normalization_16_gamma_bytes = 0;
- args->batch_normalization_16_beta = batch_normalization_16_beta;
- args->batch_normalization_16_beta_bytes = 0;
- args->batch_normalization_16_mean = batch_normalization_16_mean;
- args->batch_normalization_16_mean_bytes = 0;
- args->batch_normalization_16_variance = batch_normalization_16_variance;
- args->batch_normalization_16_variance_bytes = 0;
- args->conv2d_9_w = conv2d_9_w;
- args->conv2d_9_w_bytes = 0;
- args->batch_normalization_17_gamma = batch_normalization_17_gamma;
- args->batch_normalization_17_gamma_bytes = 0;
- args->batch_normalization_17_beta = batch_normalization_17_beta;
- args->batch_normalization_17_beta_bytes = 0;
- args->batch_normalization_17_mean = batch_normalization_17_mean;
- args->batch_normalization_17_mean_bytes = 0;
- args->batch_normalization_17_variance = batch_normalization_17_variance;
- args->batch_normalization_17_variance_bytes = 0;
- args->depthwise_conv2d_9_w = depthwise_conv2d_9_w;
- args->depthwise_conv2d_9_w_bytes = 0;
- args->batch_normalization_18_gamma = batch_normalization_18_gamma;
- args->batch_normalization_18_gamma_bytes = 0;
- args->batch_normalization_18_beta = batch_normalization_18_beta;
- args->batch_normalization_18_beta_bytes = 0;
- args->batch_normalization_18_mean = batch_normalization_18_mean;
- args->batch_normalization_18_mean_bytes = 0;
- args->batch_normalization_18_variance = batch_normalization_18_variance;
- args->batch_normalization_18_variance_bytes = 0;
- args->conv2d_10_w = conv2d_10_w;
- args->conv2d_10_w_bytes = 0;
- args->batch_normalization_19_gamma = batch_normalization_19_gamma;
- args->batch_normalization_19_gamma_bytes = 0;
- args->batch_normalization_19_beta = batch_normalization_19_beta;
- args->batch_normalization_19_beta_bytes = 0;
- args->batch_normalization_19_mean = batch_normalization_19_mean;
- args->batch_normalization_19_mean_bytes = 0;
- args->batch_normalization_19_variance = batch_normalization_19_variance;
- args->batch_normalization_19_variance_bytes = 0;
- args->depthwise_conv2d_10_w = depthwise_conv2d_10_w;
- args->depthwise_conv2d_10_w_bytes = 0;
- args->batch_normalization_20_gamma = batch_normalization_20_gamma;
- args->batch_normalization_20_gamma_bytes = 0;
- args->batch_normalization_20_beta = batch_normalization_20_beta;
- args->batch_normalization_20_beta_bytes = 0;
- args->batch_normalization_20_mean = batch_normalization_20_mean;
- args->batch_normalization_20_mean_bytes = 0;
- args->batch_normalization_20_variance = batch_normalization_20_variance;
- args->batch_normalization_20_variance_bytes = 0;
- args->conv2d_11_w = conv2d_11_w;
- args->conv2d_11_w_bytes = 0;
- args->batch_normalization_21_gamma = batch_normalization_21_gamma;
- args->batch_normalization_21_gamma_bytes = 0;
- args->batch_normalization_21_beta = batch_normalization_21_beta;
- args->batch_normalization_21_beta_bytes = 0;
- args->batch_normalization_21_mean = batch_normalization_21_mean;
- args->batch_normalization_21_mean_bytes = 0;
- args->batch_normalization_21_variance = batch_normalization_21_variance;
- args->batch_normalization_21_variance_bytes = 0;
- args->depthwise_conv2d_11_w = depthwise_conv2d_11_w;
- args->depthwise_conv2d_11_w_bytes = 0;
- args->batch_normalization_22_gamma = batch_normalization_22_gamma;
- args->batch_normalization_22_gamma_bytes = 0;
- args->batch_normalization_22_beta = batch_normalization_22_beta;
- args->batch_normalization_22_beta_bytes = 0;
- args->batch_normalization_22_mean = batch_normalization_22_mean;
- args->batch_normalization_22_mean_bytes = 0;
- args->batch_normalization_22_variance = batch_normalization_22_variance;
- args->batch_normalization_22_variance_bytes = 0;
- args->conv2d_12_w = conv2d_12_w;
- args->conv2d_12_w_bytes = 0;
- args->batch_normalization_23_gamma = batch_normalization_23_gamma;
- args->batch_normalization_23_gamma_bytes = 0;
- args->batch_normalization_23_beta = batch_normalization_23_beta;
- args->batch_normalization_23_beta_bytes = 0;
- args->batch_normalization_23_mean = batch_normalization_23_mean;
- args->batch_normalization_23_mean_bytes = 0;
- args->batch_normalization_23_variance = batch_normalization_23_variance;
- args->batch_normalization_23_variance_bytes = 0;
- args->depthwise_conv2d_12_w = depthwise_conv2d_12_w;
- args->depthwise_conv2d_12_w_bytes = 0;
- args->batch_normalization_24_gamma = batch_normalization_24_gamma;
- args->batch_normalization_24_gamma_bytes = 0;
- args->batch_normalization_24_beta = batch_normalization_24_beta;
- args->batch_normalization_24_beta_bytes = 0;
- args->batch_normalization_24_mean = batch_normalization_24_mean;
- args->batch_normalization_24_mean_bytes = 0;
- args->batch_normalization_24_variance = batch_normalization_24_variance;
- args->batch_normalization_24_variance_bytes = 0;
- args->conv2d_13_w = conv2d_13_w;
- args->conv2d_13_w_bytes = 0;
- args->batch_normalization_25_gamma = batch_normalization_25_gamma;
- args->batch_normalization_25_gamma_bytes = 0;
- args->batch_normalization_25_beta = batch_normalization_25_beta;
- args->batch_normalization_25_beta_bytes = 0;
- args->batch_normalization_25_mean = batch_normalization_25_mean;
- args->batch_normalization_25_mean_bytes = 0;
- args->batch_normalization_25_variance = batch_normalization_25_variance;
- args->batch_normalization_25_variance_bytes = 0;
- args->depthwise_conv2d_13_w = depthwise_conv2d_13_w;
- args->depthwise_conv2d_13_w_bytes = 0;
- args->batch_normalization_26_gamma = batch_normalization_26_gamma;
- args->batch_normalization_26_gamma_bytes = 0;
- args->batch_normalization_26_beta = batch_normalization_26_beta;
- args->batch_normalization_26_beta_bytes = 0;
- args->batch_normalization_26_mean = batch_normalization_26_mean;
- args->batch_normalization_26_mean_bytes = 0;
- args->batch_normalization_26_variance = batch_normalization_26_variance;
- args->batch_normalization_26_variance_bytes = 0;
- args->conv2d_14_w = conv2d_14_w;
- args->conv2d_14_w_bytes = 0;
- args->batch_normalization_27_gamma = batch_normalization_27_gamma;
- args->batch_normalization_27_gamma_bytes = 0;
- args->batch_normalization_27_beta = batch_normalization_27_beta;
- args->batch_normalization_27_beta_bytes = 0;
- args->batch_normalization_27_mean = batch_normalization_27_mean;
- args->batch_normalization_27_mean_bytes = 0;
- args->batch_normalization_27_variance = batch_normalization_27_variance;
- args->batch_normalization_27_variance_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy2(labels, 5000, result);
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/resnet18_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/resnet18_promise.cpp
deleted file mode 100644
index 83d91ca50f30b27445f1ee1805927771be5f27ed..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/resnet18_promise.cpp
+++ /dev/null
@@ -1,1442 +0,0 @@
-
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_27_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_28_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_29_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_30_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_31_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_32_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_33_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_34_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_35_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_36_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_37_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_38_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_39_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_40_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_41_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_42_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_43_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_44_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_45_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_46_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_47_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_48_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_49_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_50_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_51_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_52_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_53_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_54_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_55_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_56_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_57_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_58_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_59_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_60_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_61_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_62_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_63_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_64_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_65_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_66_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_67_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_68_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_69_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_70_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_mean(t1, 8, 8, 0, 0, 8, 8);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_71_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_72_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_73_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* conv2d_6_b, size_t conv2d_6_b_bytes,
- void* conv2d_7_w, size_t conv2d_7_w_bytes,
- void* conv2d_7_b, size_t conv2d_7_b_bytes,
- void* conv2d_8_w, size_t conv2d_8_w_bytes,
- void* conv2d_8_b, size_t conv2d_8_b_bytes,
- void* conv2d_10_w, size_t conv2d_10_w_bytes,
- void* conv2d_10_b, size_t conv2d_10_b_bytes,
- void* conv2d_9_w, size_t conv2d_9_w_bytes,
- void* conv2d_9_b, size_t conv2d_9_b_bytes,
- void* conv2d_11_w, size_t conv2d_11_w_bytes,
- void* conv2d_11_b, size_t conv2d_11_b_bytes,
- void* conv2d_12_w, size_t conv2d_12_w_bytes,
- void* conv2d_12_b, size_t conv2d_12_b_bytes,
- void* conv2d_13_w, size_t conv2d_13_w_bytes,
- void* conv2d_13_b, size_t conv2d_13_b_bytes,
- void* conv2d_14_w, size_t conv2d_14_w_bytes,
- void* conv2d_14_b, size_t conv2d_14_b_bytes,
- void* conv2d_15_w, size_t conv2d_15_w_bytes,
- void* conv2d_15_b, size_t conv2d_15_b_bytes,
- void* conv2d_17_w, size_t conv2d_17_w_bytes,
- void* conv2d_17_b, size_t conv2d_17_b_bytes,
- void* conv2d_16_w, size_t conv2d_16_w_bytes,
- void* conv2d_16_b, size_t conv2d_16_b_bytes,
- void* conv2d_18_w, size_t conv2d_18_w_bytes,
- void* conv2d_18_b, size_t conv2d_18_b_bytes,
- void* conv2d_19_w, size_t conv2d_19_w_bytes,
- void* conv2d_19_b, size_t conv2d_19_b_bytes,
- void* conv2d_20_w, size_t conv2d_20_w_bytes,
- void* conv2d_20_b, size_t conv2d_20_b_bytes,
- void* conv2d_21_w, size_t conv2d_21_w_bytes,
- void* conv2d_21_b, size_t conv2d_21_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(45, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, conv2d_6_w, conv2d_6_b, conv2d_7_w, conv2d_7_b, conv2d_8_w, conv2d_8_b, conv2d_10_w, conv2d_10_b, conv2d_9_w, conv2d_9_b, conv2d_11_w, conv2d_11_b, conv2d_12_w, conv2d_12_b, conv2d_13_w, conv2d_13_b, conv2d_14_w, conv2d_14_b, conv2d_15_w, conv2d_15_b, conv2d_17_w, conv2d_17_b, conv2d_16_w, conv2d_16_b, conv2d_18_w, conv2d_18_b, conv2d_19_w, conv2d_19_b, conv2d_20_w, conv2d_20_b, conv2d_21_w, conv2d_21_b, dense_1_w, dense_1_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 8, 2, 0);
- __visc__bindIn(var_4, 9, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
- __visc__bindIn(var_6, 10, 2, 0);
- __visc__bindIn(var_6, 11, 3, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 12, 2, 0);
- __visc__bindIn(var_7, 13, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_2, var_8, 1, 0, 0, 0);
- __visc__edge(var_2, var_8, 1, 1, 1, 0);
- __visc__edge(var_7, var_8, 1, 0, 2, 0);
- __visc__edge(var_7, var_8, 1, 1, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
- __visc__bindIn(var_13, 18, 2, 0);
- __visc__bindIn(var_13, 19, 3, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 20, 2, 0);
- __visc__bindIn(var_14, 21, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_9, var_15, 1, 0, 0, 0);
- __visc__edge(var_9, var_15, 1, 1, 1, 0);
- __visc__edge(var_14, var_15, 1, 0, 2, 0);
- __visc__edge(var_14, var_15, 1, 1, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
- __visc__bindIn(var_17, 22, 2, 0);
- __visc__bindIn(var_17, 23, 3, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 24, 2, 0);
- __visc__bindIn(var_18, 25, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
- __visc__bindIn(var_20, 26, 2, 0);
- __visc__bindIn(var_20, 27, 3, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 28, 2, 0);
- __visc__bindIn(var_21, 29, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_16, var_22, 1, 0, 0, 0);
- __visc__edge(var_16, var_22, 1, 1, 1, 0);
- __visc__edge(var_21, var_22, 1, 0, 2, 0);
- __visc__edge(var_21, var_22, 1, 1, 3, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 30, 2, 0);
- __visc__bindIn(var_24, 31, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 32, 2, 0);
- __visc__bindIn(var_25, 33, 3, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- void* var_27 = __visc__createNodeND(0, var_27_node);
-
- __visc__edge(var_26, var_27, 1, 0, 0, 0);
- __visc__edge(var_26, var_27, 1, 1, 1, 0);
- __visc__bindIn(var_27, 38, 2, 0);
- __visc__bindIn(var_27, 39, 3, 0);
-
- void* var_28 = __visc__createNodeND(0, var_28_node);
-
- __visc__edge(var_27, var_28, 1, 0, 0, 0);
- __visc__edge(var_27, var_28, 1, 1, 1, 0);
- __visc__bindIn(var_28, 40, 2, 0);
- __visc__bindIn(var_28, 41, 3, 0);
-
- void* var_29 = __visc__createNodeND(0, var_29_node);
-
- __visc__edge(var_23, var_29, 1, 0, 0, 0);
- __visc__edge(var_23, var_29, 1, 1, 1, 0);
- __visc__bindIn(var_29, 34, 2, 0);
- __visc__bindIn(var_29, 35, 3, 0);
-
- void* var_30 = __visc__createNodeND(0, var_30_node);
-
- __visc__edge(var_29, var_30, 1, 0, 0, 0);
- __visc__edge(var_29, var_30, 1, 1, 1, 0);
- __visc__bindIn(var_30, 36, 2, 0);
- __visc__bindIn(var_30, 37, 3, 0);
-
- void* var_31 = __visc__createNodeND(0, var_31_node);
-
- __visc__edge(var_30, var_31, 1, 0, 0, 0);
- __visc__edge(var_30, var_31, 1, 1, 1, 0);
- __visc__edge(var_28, var_31, 1, 0, 2, 0);
- __visc__edge(var_28, var_31, 1, 1, 3, 0);
-
- void* var_32 = __visc__createNodeND(0, var_32_node);
-
- __visc__edge(var_31, var_32, 1, 0, 0, 0);
- __visc__edge(var_31, var_32, 1, 1, 1, 0);
-
- void* var_33 = __visc__createNodeND(0, var_33_node);
-
- __visc__edge(var_32, var_33, 1, 0, 0, 0);
- __visc__edge(var_32, var_33, 1, 1, 1, 0);
- __visc__bindIn(var_33, 42, 2, 0);
- __visc__bindIn(var_33, 43, 3, 0);
-
- void* var_34 = __visc__createNodeND(0, var_34_node);
-
- __visc__edge(var_33, var_34, 1, 0, 0, 0);
- __visc__edge(var_33, var_34, 1, 1, 1, 0);
- __visc__bindIn(var_34, 44, 2, 0);
- __visc__bindIn(var_34, 45, 3, 0);
-
- void* var_35 = __visc__createNodeND(0, var_35_node);
-
- __visc__edge(var_34, var_35, 1, 0, 0, 0);
- __visc__edge(var_34, var_35, 1, 1, 1, 0);
-
- void* var_36 = __visc__createNodeND(0, var_36_node);
-
- __visc__edge(var_35, var_36, 1, 0, 0, 0);
- __visc__edge(var_35, var_36, 1, 1, 1, 0);
- __visc__bindIn(var_36, 46, 2, 0);
- __visc__bindIn(var_36, 47, 3, 0);
-
- void* var_37 = __visc__createNodeND(0, var_37_node);
-
- __visc__edge(var_36, var_37, 1, 0, 0, 0);
- __visc__edge(var_36, var_37, 1, 1, 1, 0);
- __visc__bindIn(var_37, 48, 2, 0);
- __visc__bindIn(var_37, 49, 3, 0);
-
- void* var_38 = __visc__createNodeND(0, var_38_node);
-
- __visc__edge(var_32, var_38, 1, 0, 0, 0);
- __visc__edge(var_32, var_38, 1, 1, 1, 0);
- __visc__edge(var_37, var_38, 1, 0, 2, 0);
- __visc__edge(var_37, var_38, 1, 1, 3, 0);
-
- void* var_39 = __visc__createNodeND(0, var_39_node);
-
- __visc__edge(var_38, var_39, 1, 0, 0, 0);
- __visc__edge(var_38, var_39, 1, 1, 1, 0);
-
- void* var_40 = __visc__createNodeND(0, var_40_node);
-
- __visc__edge(var_39, var_40, 1, 0, 0, 0);
- __visc__edge(var_39, var_40, 1, 1, 1, 0);
- __visc__bindIn(var_40, 50, 2, 0);
- __visc__bindIn(var_40, 51, 3, 0);
-
- void* var_41 = __visc__createNodeND(0, var_41_node);
-
- __visc__edge(var_40, var_41, 1, 0, 0, 0);
- __visc__edge(var_40, var_41, 1, 1, 1, 0);
- __visc__bindIn(var_41, 52, 2, 0);
- __visc__bindIn(var_41, 53, 3, 0);
-
- void* var_42 = __visc__createNodeND(0, var_42_node);
-
- __visc__edge(var_41, var_42, 1, 0, 0, 0);
- __visc__edge(var_41, var_42, 1, 1, 1, 0);
-
- void* var_43 = __visc__createNodeND(0, var_43_node);
-
- __visc__edge(var_42, var_43, 1, 0, 0, 0);
- __visc__edge(var_42, var_43, 1, 1, 1, 0);
- __visc__bindIn(var_43, 54, 2, 0);
- __visc__bindIn(var_43, 55, 3, 0);
-
- void* var_44 = __visc__createNodeND(0, var_44_node);
-
- __visc__edge(var_43, var_44, 1, 0, 0, 0);
- __visc__edge(var_43, var_44, 1, 1, 1, 0);
- __visc__bindIn(var_44, 56, 2, 0);
- __visc__bindIn(var_44, 57, 3, 0);
-
- void* var_45 = __visc__createNodeND(0, var_45_node);
-
- __visc__edge(var_39, var_45, 1, 0, 0, 0);
- __visc__edge(var_39, var_45, 1, 1, 1, 0);
- __visc__edge(var_44, var_45, 1, 0, 2, 0);
- __visc__edge(var_44, var_45, 1, 1, 3, 0);
-
- void* var_46 = __visc__createNodeND(0, var_46_node);
-
- __visc__edge(var_45, var_46, 1, 0, 0, 0);
- __visc__edge(var_45, var_46, 1, 1, 1, 0);
-
- void* var_47 = __visc__createNodeND(0, var_47_node);
-
- __visc__edge(var_46, var_47, 1, 0, 0, 0);
- __visc__edge(var_46, var_47, 1, 1, 1, 0);
- __visc__bindIn(var_47, 58, 2, 0);
- __visc__bindIn(var_47, 59, 3, 0);
-
- void* var_48 = __visc__createNodeND(0, var_48_node);
-
- __visc__edge(var_47, var_48, 1, 0, 0, 0);
- __visc__edge(var_47, var_48, 1, 1, 1, 0);
- __visc__bindIn(var_48, 60, 2, 0);
- __visc__bindIn(var_48, 61, 3, 0);
-
- void* var_49 = __visc__createNodeND(0, var_49_node);
-
- __visc__edge(var_48, var_49, 1, 0, 0, 0);
- __visc__edge(var_48, var_49, 1, 1, 1, 0);
-
- void* var_50 = __visc__createNodeND(0, var_50_node);
-
- __visc__edge(var_49, var_50, 1, 0, 0, 0);
- __visc__edge(var_49, var_50, 1, 1, 1, 0);
- __visc__bindIn(var_50, 66, 2, 0);
- __visc__bindIn(var_50, 67, 3, 0);
-
- void* var_51 = __visc__createNodeND(0, var_51_node);
-
- __visc__edge(var_50, var_51, 1, 0, 0, 0);
- __visc__edge(var_50, var_51, 1, 1, 1, 0);
- __visc__bindIn(var_51, 68, 2, 0);
- __visc__bindIn(var_51, 69, 3, 0);
-
- void* var_52 = __visc__createNodeND(0, var_52_node);
-
- __visc__edge(var_46, var_52, 1, 0, 0, 0);
- __visc__edge(var_46, var_52, 1, 1, 1, 0);
- __visc__bindIn(var_52, 62, 2, 0);
- __visc__bindIn(var_52, 63, 3, 0);
-
- void* var_53 = __visc__createNodeND(0, var_53_node);
-
- __visc__edge(var_52, var_53, 1, 0, 0, 0);
- __visc__edge(var_52, var_53, 1, 1, 1, 0);
- __visc__bindIn(var_53, 64, 2, 0);
- __visc__bindIn(var_53, 65, 3, 0);
-
- void* var_54 = __visc__createNodeND(0, var_54_node);
-
- __visc__edge(var_53, var_54, 1, 0, 0, 0);
- __visc__edge(var_53, var_54, 1, 1, 1, 0);
- __visc__edge(var_51, var_54, 1, 0, 2, 0);
- __visc__edge(var_51, var_54, 1, 1, 3, 0);
-
- void* var_55 = __visc__createNodeND(0, var_55_node);
-
- __visc__edge(var_54, var_55, 1, 0, 0, 0);
- __visc__edge(var_54, var_55, 1, 1, 1, 0);
-
- void* var_56 = __visc__createNodeND(0, var_56_node);
-
- __visc__edge(var_55, var_56, 1, 0, 0, 0);
- __visc__edge(var_55, var_56, 1, 1, 1, 0);
- __visc__bindIn(var_56, 70, 2, 0);
- __visc__bindIn(var_56, 71, 3, 0);
-
- void* var_57 = __visc__createNodeND(0, var_57_node);
-
- __visc__edge(var_56, var_57, 1, 0, 0, 0);
- __visc__edge(var_56, var_57, 1, 1, 1, 0);
- __visc__bindIn(var_57, 72, 2, 0);
- __visc__bindIn(var_57, 73, 3, 0);
-
- void* var_58 = __visc__createNodeND(0, var_58_node);
-
- __visc__edge(var_57, var_58, 1, 0, 0, 0);
- __visc__edge(var_57, var_58, 1, 1, 1, 0);
-
- void* var_59 = __visc__createNodeND(0, var_59_node);
-
- __visc__edge(var_58, var_59, 1, 0, 0, 0);
- __visc__edge(var_58, var_59, 1, 1, 1, 0);
- __visc__bindIn(var_59, 74, 2, 0);
- __visc__bindIn(var_59, 75, 3, 0);
-
- void* var_60 = __visc__createNodeND(0, var_60_node);
-
- __visc__edge(var_59, var_60, 1, 0, 0, 0);
- __visc__edge(var_59, var_60, 1, 1, 1, 0);
- __visc__bindIn(var_60, 76, 2, 0);
- __visc__bindIn(var_60, 77, 3, 0);
-
- void* var_61 = __visc__createNodeND(0, var_61_node);
-
- __visc__edge(var_55, var_61, 1, 0, 0, 0);
- __visc__edge(var_55, var_61, 1, 1, 1, 0);
- __visc__edge(var_60, var_61, 1, 0, 2, 0);
- __visc__edge(var_60, var_61, 1, 1, 3, 0);
-
- void* var_62 = __visc__createNodeND(0, var_62_node);
-
- __visc__edge(var_61, var_62, 1, 0, 0, 0);
- __visc__edge(var_61, var_62, 1, 1, 1, 0);
-
- void* var_63 = __visc__createNodeND(0, var_63_node);
-
- __visc__edge(var_62, var_63, 1, 0, 0, 0);
- __visc__edge(var_62, var_63, 1, 1, 1, 0);
- __visc__bindIn(var_63, 78, 2, 0);
- __visc__bindIn(var_63, 79, 3, 0);
-
- void* var_64 = __visc__createNodeND(0, var_64_node);
-
- __visc__edge(var_63, var_64, 1, 0, 0, 0);
- __visc__edge(var_63, var_64, 1, 1, 1, 0);
- __visc__bindIn(var_64, 80, 2, 0);
- __visc__bindIn(var_64, 81, 3, 0);
-
- void* var_65 = __visc__createNodeND(0, var_65_node);
-
- __visc__edge(var_64, var_65, 1, 0, 0, 0);
- __visc__edge(var_64, var_65, 1, 1, 1, 0);
-
- void* var_66 = __visc__createNodeND(0, var_66_node);
-
- __visc__edge(var_65, var_66, 1, 0, 0, 0);
- __visc__edge(var_65, var_66, 1, 1, 1, 0);
- __visc__bindIn(var_66, 82, 2, 0);
- __visc__bindIn(var_66, 83, 3, 0);
-
- void* var_67 = __visc__createNodeND(0, var_67_node);
-
- __visc__edge(var_66, var_67, 1, 0, 0, 0);
- __visc__edge(var_66, var_67, 1, 1, 1, 0);
- __visc__bindIn(var_67, 84, 2, 0);
- __visc__bindIn(var_67, 85, 3, 0);
-
- void* var_68 = __visc__createNodeND(0, var_68_node);
-
- __visc__edge(var_62, var_68, 1, 0, 0, 0);
- __visc__edge(var_62, var_68, 1, 1, 1, 0);
- __visc__edge(var_67, var_68, 1, 0, 2, 0);
- __visc__edge(var_67, var_68, 1, 1, 3, 0);
-
- void* var_69 = __visc__createNodeND(0, var_69_node);
-
- __visc__edge(var_68, var_69, 1, 0, 0, 0);
- __visc__edge(var_68, var_69, 1, 1, 1, 0);
-
- void* var_70 = __visc__createNodeND(0, var_70_node);
-
- __visc__edge(var_69, var_70, 1, 0, 0, 0);
- __visc__edge(var_69, var_70, 1, 1, 1, 0);
-
- void* var_71 = __visc__createNodeND(0, var_71_node);
-
- __visc__edge(var_70, var_71, 1, 0, 0, 0);
- __visc__edge(var_70, var_71, 1, 1, 1, 0);
- __visc__bindIn(var_71, 86, 2, 0);
- __visc__bindIn(var_71, 87, 3, 0);
-
- void* var_72 = __visc__createNodeND(0, var_72_node);
-
- __visc__edge(var_71, var_72, 1, 0, 0, 0);
- __visc__edge(var_71, var_72, 1, 1, 1, 0);
- __visc__bindIn(var_72, 88, 2, 0);
- __visc__bindIn(var_72, 89, 3, 0);
-
- void* var_73 = __visc__createNodeND(0, var_73_node);
-
- __visc__edge(var_72, var_73, 1, 0, 0, 0);
- __visc__edge(var_72, var_73, 1, 1, 1, 0);
-
- __visc__bindOut(var_73, 0, 0, 0);
- __visc__bindOut(var_73, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* conv2d_6_b;
- size_t conv2d_6_b_bytes;
- void* conv2d_7_w;
- size_t conv2d_7_w_bytes;
- void* conv2d_7_b;
- size_t conv2d_7_b_bytes;
- void* conv2d_8_w;
- size_t conv2d_8_w_bytes;
- void* conv2d_8_b;
- size_t conv2d_8_b_bytes;
- void* conv2d_10_w;
- size_t conv2d_10_w_bytes;
- void* conv2d_10_b;
- size_t conv2d_10_b_bytes;
- void* conv2d_9_w;
- size_t conv2d_9_w_bytes;
- void* conv2d_9_b;
- size_t conv2d_9_b_bytes;
- void* conv2d_11_w;
- size_t conv2d_11_w_bytes;
- void* conv2d_11_b;
- size_t conv2d_11_b_bytes;
- void* conv2d_12_w;
- size_t conv2d_12_w_bytes;
- void* conv2d_12_b;
- size_t conv2d_12_b_bytes;
- void* conv2d_13_w;
- size_t conv2d_13_w_bytes;
- void* conv2d_13_b;
- size_t conv2d_13_b_bytes;
- void* conv2d_14_w;
- size_t conv2d_14_w_bytes;
- void* conv2d_14_b;
- size_t conv2d_14_b_bytes;
- void* conv2d_15_w;
- size_t conv2d_15_w_bytes;
- void* conv2d_15_b;
- size_t conv2d_15_b_bytes;
- void* conv2d_17_w;
- size_t conv2d_17_w_bytes;
- void* conv2d_17_b;
- size_t conv2d_17_b_bytes;
- void* conv2d_16_w;
- size_t conv2d_16_w_bytes;
- void* conv2d_16_b;
- size_t conv2d_16_b_bytes;
- void* conv2d_18_w;
- size_t conv2d_18_w_bytes;
- void* conv2d_18_b;
- size_t conv2d_18_b_bytes;
- void* conv2d_19_w;
- size_t conv2d_19_w_bytes;
- void* conv2d_19_b;
- size_t conv2d_19_b_bytes;
- void* conv2d_20_w;
- size_t conv2d_20_w_bytes;
- void* conv2d_20_b;
- size_t conv2d_20_b_bytes;
- void* conv2d_21_w;
- size_t conv2d_21_w_bytes;
- void* conv2d_21_b;
- size_t conv2d_21_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/resnet18_cifar10/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- void* input = readTrainedWeights(input_path.c_str(), 0,5000,3,32,32);
- std::string labels_path = dir_prefix + std::string("labels32.bin");
- uint32_t* labels = readLabels3(labels_path.c_str(),5000);
-
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,16,3,3,3);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,16,16,3,3);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,16,16,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,16,16,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,16,16,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,16,16,3,3);
- std::string conv2d_6_b_path = dir_prefix + std::string("conv2d_6_b.bin");
- void* conv2d_6_b = readTrainedWeights(conv2d_6_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_7_w_path = dir_prefix + std::string("conv2d_7_w.bin");
- void* conv2d_7_w = readTrainedWeights(conv2d_7_w_path.c_str(), 0,16,16,3,3);
- std::string conv2d_7_b_path = dir_prefix + std::string("conv2d_7_b.bin");
- void* conv2d_7_b = readTrainedWeights(conv2d_7_b_path.c_str(), 0,1,16,1,1);
- std::string conv2d_8_w_path = dir_prefix + std::string("conv2d_8_w.bin");
- void* conv2d_8_w = readTrainedWeights(conv2d_8_w_path.c_str(), 0,32,16,3,3);
- std::string conv2d_8_b_path = dir_prefix + std::string("conv2d_8_b.bin");
- void* conv2d_8_b = readTrainedWeights(conv2d_8_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_10_w_path = dir_prefix + std::string("conv2d_10_w.bin");
- void* conv2d_10_w = readTrainedWeights(conv2d_10_w_path.c_str(), 0,32,16,1,1);
- std::string conv2d_10_b_path = dir_prefix + std::string("conv2d_10_b.bin");
- void* conv2d_10_b = readTrainedWeights(conv2d_10_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_9_w_path = dir_prefix + std::string("conv2d_9_w.bin");
- void* conv2d_9_w = readTrainedWeights(conv2d_9_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_9_b_path = dir_prefix + std::string("conv2d_9_b.bin");
- void* conv2d_9_b = readTrainedWeights(conv2d_9_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_11_w_path = dir_prefix + std::string("conv2d_11_w.bin");
- void* conv2d_11_w = readTrainedWeights(conv2d_11_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_11_b_path = dir_prefix + std::string("conv2d_11_b.bin");
- void* conv2d_11_b = readTrainedWeights(conv2d_11_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_12_w_path = dir_prefix + std::string("conv2d_12_w.bin");
- void* conv2d_12_w = readTrainedWeights(conv2d_12_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_12_b_path = dir_prefix + std::string("conv2d_12_b.bin");
- void* conv2d_12_b = readTrainedWeights(conv2d_12_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_13_w_path = dir_prefix + std::string("conv2d_13_w.bin");
- void* conv2d_13_w = readTrainedWeights(conv2d_13_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_13_b_path = dir_prefix + std::string("conv2d_13_b.bin");
- void* conv2d_13_b = readTrainedWeights(conv2d_13_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_14_w_path = dir_prefix + std::string("conv2d_14_w.bin");
- void* conv2d_14_w = readTrainedWeights(conv2d_14_w_path.c_str(), 0,32,32,3,3);
- std::string conv2d_14_b_path = dir_prefix + std::string("conv2d_14_b.bin");
- void* conv2d_14_b = readTrainedWeights(conv2d_14_b_path.c_str(), 0,1,32,1,1);
- std::string conv2d_15_w_path = dir_prefix + std::string("conv2d_15_w.bin");
- void* conv2d_15_w = readTrainedWeights(conv2d_15_w_path.c_str(), 0,64,32,3,3);
- std::string conv2d_15_b_path = dir_prefix + std::string("conv2d_15_b.bin");
- void* conv2d_15_b = readTrainedWeights(conv2d_15_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_17_w_path = dir_prefix + std::string("conv2d_17_w.bin");
- void* conv2d_17_w = readTrainedWeights(conv2d_17_w_path.c_str(), 0,64,32,1,1);
- std::string conv2d_17_b_path = dir_prefix + std::string("conv2d_17_b.bin");
- void* conv2d_17_b = readTrainedWeights(conv2d_17_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_16_w_path = dir_prefix + std::string("conv2d_16_w.bin");
- void* conv2d_16_w = readTrainedWeights(conv2d_16_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_16_b_path = dir_prefix + std::string("conv2d_16_b.bin");
- void* conv2d_16_b = readTrainedWeights(conv2d_16_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_18_w_path = dir_prefix + std::string("conv2d_18_w.bin");
- void* conv2d_18_w = readTrainedWeights(conv2d_18_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_18_b_path = dir_prefix + std::string("conv2d_18_b.bin");
- void* conv2d_18_b = readTrainedWeights(conv2d_18_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_19_w_path = dir_prefix + std::string("conv2d_19_w.bin");
- void* conv2d_19_w = readTrainedWeights(conv2d_19_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_19_b_path = dir_prefix + std::string("conv2d_19_b.bin");
- void* conv2d_19_b = readTrainedWeights(conv2d_19_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_20_w_path = dir_prefix + std::string("conv2d_20_w.bin");
- void* conv2d_20_w = readTrainedWeights(conv2d_20_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_20_b_path = dir_prefix + std::string("conv2d_20_b.bin");
- void* conv2d_20_b = readTrainedWeights(conv2d_20_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_21_w_path = dir_prefix + std::string("conv2d_21_w.bin");
- void* conv2d_21_w = readTrainedWeights(conv2d_21_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_21_b_path = dir_prefix + std::string("conv2d_21_b.bin");
- void* conv2d_21_b = readTrainedWeights(conv2d_21_b_path.c_str(), 0,1,64,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,64,10);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,10,1,1);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->conv2d_6_b = conv2d_6_b;
- args->conv2d_6_b_bytes = 0;
- args->conv2d_7_w = conv2d_7_w;
- args->conv2d_7_w_bytes = 0;
- args->conv2d_7_b = conv2d_7_b;
- args->conv2d_7_b_bytes = 0;
- args->conv2d_8_w = conv2d_8_w;
- args->conv2d_8_w_bytes = 0;
- args->conv2d_8_b = conv2d_8_b;
- args->conv2d_8_b_bytes = 0;
- args->conv2d_10_w = conv2d_10_w;
- args->conv2d_10_w_bytes = 0;
- args->conv2d_10_b = conv2d_10_b;
- args->conv2d_10_b_bytes = 0;
- args->conv2d_9_w = conv2d_9_w;
- args->conv2d_9_w_bytes = 0;
- args->conv2d_9_b = conv2d_9_b;
- args->conv2d_9_b_bytes = 0;
- args->conv2d_11_w = conv2d_11_w;
- args->conv2d_11_w_bytes = 0;
- args->conv2d_11_b = conv2d_11_b;
- args->conv2d_11_b_bytes = 0;
- args->conv2d_12_w = conv2d_12_w;
- args->conv2d_12_w_bytes = 0;
- args->conv2d_12_b = conv2d_12_b;
- args->conv2d_12_b_bytes = 0;
- args->conv2d_13_w = conv2d_13_w;
- args->conv2d_13_w_bytes = 0;
- args->conv2d_13_b = conv2d_13_b;
- args->conv2d_13_b_bytes = 0;
- args->conv2d_14_w = conv2d_14_w;
- args->conv2d_14_w_bytes = 0;
- args->conv2d_14_b = conv2d_14_b;
- args->conv2d_14_b_bytes = 0;
- args->conv2d_15_w = conv2d_15_w;
- args->conv2d_15_w_bytes = 0;
- args->conv2d_15_b = conv2d_15_b;
- args->conv2d_15_b_bytes = 0;
- args->conv2d_17_w = conv2d_17_w;
- args->conv2d_17_w_bytes = 0;
- args->conv2d_17_b = conv2d_17_b;
- args->conv2d_17_b_bytes = 0;
- args->conv2d_16_w = conv2d_16_w;
- args->conv2d_16_w_bytes = 0;
- args->conv2d_16_b = conv2d_16_b;
- args->conv2d_16_b_bytes = 0;
- args->conv2d_18_w = conv2d_18_w;
- args->conv2d_18_w_bytes = 0;
- args->conv2d_18_b = conv2d_18_b;
- args->conv2d_18_b_bytes = 0;
- args->conv2d_19_w = conv2d_19_w;
- args->conv2d_19_w_bytes = 0;
- args->conv2d_19_b = conv2d_19_b;
- args->conv2d_19_b_bytes = 0;
- args->conv2d_20_w = conv2d_20_w;
- args->conv2d_20_w_bytes = 0;
- args->conv2d_20_b = conv2d_20_b;
- args->conv2d_20_b_bytes = 0;
- args->conv2d_21_w = conv2d_21_w;
- args->conv2d_21_w_bytes = 0;
- args->conv2d_21_b = conv2d_21_b;
- args->conv2d_21_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy3(labels, result);
-
- return 0;
-
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/vgg16_cifar100_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/vgg16_cifar100_promise.cpp
deleted file mode 100644
index 37e1e72b3d46ac3cacced12c17051acd8c539c12..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/vgg16_cifar100_promise.cpp
+++ /dev/null
@@ -1,985 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_27_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_28_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_29_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_30_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_31_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_32_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_33_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_34_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_35_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_36_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_37_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_38_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_39_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_40_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_41_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_42_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_43_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_44_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_45_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_46_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_47_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_48_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_49_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* conv2d_6_b, size_t conv2d_6_b_bytes,
- void* conv2d_7_w, size_t conv2d_7_w_bytes,
- void* conv2d_7_b, size_t conv2d_7_b_bytes,
- void* conv2d_8_w, size_t conv2d_8_w_bytes,
- void* conv2d_8_b, size_t conv2d_8_b_bytes,
- void* conv2d_9_w, size_t conv2d_9_w_bytes,
- void* conv2d_9_b, size_t conv2d_9_b_bytes,
- void* conv2d_10_w, size_t conv2d_10_w_bytes,
- void* conv2d_10_b, size_t conv2d_10_b_bytes,
- void* conv2d_11_w, size_t conv2d_11_w_bytes,
- void* conv2d_11_b, size_t conv2d_11_b_bytes,
- void* conv2d_12_w, size_t conv2d_12_w_bytes,
- void* conv2d_12_b, size_t conv2d_12_b_bytes,
- void* conv2d_13_w, size_t conv2d_13_w_bytes,
- void* conv2d_13_b, size_t conv2d_13_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(31, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, conv2d_6_w, conv2d_6_b, conv2d_7_w, conv2d_7_b, conv2d_8_w, conv2d_8_b, conv2d_9_w, conv2d_9_b, conv2d_10_w, conv2d_10_b, conv2d_11_w, conv2d_11_b, conv2d_12_w, conv2d_12_b, conv2d_13_w, conv2d_13_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 8, 2, 0);
- __visc__bindIn(var_4, 9, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
- __visc__bindIn(var_17, 22, 2, 0);
- __visc__bindIn(var_17, 23, 3, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 24, 2, 0);
- __visc__bindIn(var_18, 25, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
- __visc__bindIn(var_20, 26, 2, 0);
- __visc__bindIn(var_20, 27, 3, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 28, 2, 0);
- __visc__bindIn(var_21, 29, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 30, 2, 0);
- __visc__bindIn(var_24, 31, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 32, 2, 0);
- __visc__bindIn(var_25, 33, 3, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- void* var_27 = __visc__createNodeND(0, var_27_node);
-
- __visc__edge(var_26, var_27, 1, 0, 0, 0);
- __visc__edge(var_26, var_27, 1, 1, 1, 0);
- __visc__bindIn(var_27, 34, 2, 0);
- __visc__bindIn(var_27, 35, 3, 0);
-
- void* var_28 = __visc__createNodeND(0, var_28_node);
-
- __visc__edge(var_27, var_28, 1, 0, 0, 0);
- __visc__edge(var_27, var_28, 1, 1, 1, 0);
- __visc__bindIn(var_28, 36, 2, 0);
- __visc__bindIn(var_28, 37, 3, 0);
-
- void* var_29 = __visc__createNodeND(0, var_29_node);
-
- __visc__edge(var_28, var_29, 1, 0, 0, 0);
- __visc__edge(var_28, var_29, 1, 1, 1, 0);
-
- void* var_30 = __visc__createNodeND(0, var_30_node);
-
- __visc__edge(var_29, var_30, 1, 0, 0, 0);
- __visc__edge(var_29, var_30, 1, 1, 1, 0);
- __visc__bindIn(var_30, 38, 2, 0);
- __visc__bindIn(var_30, 39, 3, 0);
-
- void* var_31 = __visc__createNodeND(0, var_31_node);
-
- __visc__edge(var_30, var_31, 1, 0, 0, 0);
- __visc__edge(var_30, var_31, 1, 1, 1, 0);
- __visc__bindIn(var_31, 40, 2, 0);
- __visc__bindIn(var_31, 41, 3, 0);
-
- void* var_32 = __visc__createNodeND(0, var_32_node);
-
- __visc__edge(var_31, var_32, 1, 0, 0, 0);
- __visc__edge(var_31, var_32, 1, 1, 1, 0);
-
- void* var_33 = __visc__createNodeND(0, var_33_node);
-
- __visc__edge(var_32, var_33, 1, 0, 0, 0);
- __visc__edge(var_32, var_33, 1, 1, 1, 0);
-
- void* var_34 = __visc__createNodeND(0, var_34_node);
-
- __visc__edge(var_33, var_34, 1, 0, 0, 0);
- __visc__edge(var_33, var_34, 1, 1, 1, 0);
- __visc__bindIn(var_34, 42, 2, 0);
- __visc__bindIn(var_34, 43, 3, 0);
-
- void* var_35 = __visc__createNodeND(0, var_35_node);
-
- __visc__edge(var_34, var_35, 1, 0, 0, 0);
- __visc__edge(var_34, var_35, 1, 1, 1, 0);
- __visc__bindIn(var_35, 44, 2, 0);
- __visc__bindIn(var_35, 45, 3, 0);
-
- void* var_36 = __visc__createNodeND(0, var_36_node);
-
- __visc__edge(var_35, var_36, 1, 0, 0, 0);
- __visc__edge(var_35, var_36, 1, 1, 1, 0);
-
- void* var_37 = __visc__createNodeND(0, var_37_node);
-
- __visc__edge(var_36, var_37, 1, 0, 0, 0);
- __visc__edge(var_36, var_37, 1, 1, 1, 0);
- __visc__bindIn(var_37, 46, 2, 0);
- __visc__bindIn(var_37, 47, 3, 0);
-
- void* var_38 = __visc__createNodeND(0, var_38_node);
-
- __visc__edge(var_37, var_38, 1, 0, 0, 0);
- __visc__edge(var_37, var_38, 1, 1, 1, 0);
- __visc__bindIn(var_38, 48, 2, 0);
- __visc__bindIn(var_38, 49, 3, 0);
-
- void* var_39 = __visc__createNodeND(0, var_39_node);
-
- __visc__edge(var_38, var_39, 1, 0, 0, 0);
- __visc__edge(var_38, var_39, 1, 1, 1, 0);
-
- void* var_40 = __visc__createNodeND(0, var_40_node);
-
- __visc__edge(var_39, var_40, 1, 0, 0, 0);
- __visc__edge(var_39, var_40, 1, 1, 1, 0);
- __visc__bindIn(var_40, 50, 2, 0);
- __visc__bindIn(var_40, 51, 3, 0);
-
- void* var_41 = __visc__createNodeND(0, var_41_node);
-
- __visc__edge(var_40, var_41, 1, 0, 0, 0);
- __visc__edge(var_40, var_41, 1, 1, 1, 0);
- __visc__bindIn(var_41, 52, 2, 0);
- __visc__bindIn(var_41, 53, 3, 0);
-
- void* var_42 = __visc__createNodeND(0, var_42_node);
-
- __visc__edge(var_41, var_42, 1, 0, 0, 0);
- __visc__edge(var_41, var_42, 1, 1, 1, 0);
-
- void* var_43 = __visc__createNodeND(0, var_43_node);
-
- __visc__edge(var_42, var_43, 1, 0, 0, 0);
- __visc__edge(var_42, var_43, 1, 1, 1, 0);
-
- void* var_44 = __visc__createNodeND(0, var_44_node);
-
- __visc__edge(var_43, var_44, 1, 0, 0, 0);
- __visc__edge(var_43, var_44, 1, 1, 1, 0);
- __visc__bindIn(var_44, 54, 2, 0);
- __visc__bindIn(var_44, 55, 3, 0);
-
- void* var_45 = __visc__createNodeND(0, var_45_node);
-
- __visc__edge(var_44, var_45, 1, 0, 0, 0);
- __visc__edge(var_44, var_45, 1, 1, 1, 0);
- __visc__bindIn(var_45, 56, 2, 0);
- __visc__bindIn(var_45, 57, 3, 0);
-
- void* var_46 = __visc__createNodeND(0, var_46_node);
-
- __visc__edge(var_45, var_46, 1, 0, 0, 0);
- __visc__edge(var_45, var_46, 1, 1, 1, 0);
-
- void* var_47 = __visc__createNodeND(0, var_47_node);
-
- __visc__edge(var_46, var_47, 1, 0, 0, 0);
- __visc__edge(var_46, var_47, 1, 1, 1, 0);
- __visc__bindIn(var_47, 58, 2, 0);
- __visc__bindIn(var_47, 59, 3, 0);
-
- void* var_48 = __visc__createNodeND(0, var_48_node);
-
- __visc__edge(var_47, var_48, 1, 0, 0, 0);
- __visc__edge(var_47, var_48, 1, 1, 1, 0);
- __visc__bindIn(var_48, 60, 2, 0);
- __visc__bindIn(var_48, 61, 3, 0);
-
- void* var_49 = __visc__createNodeND(0, var_49_node);
-
- __visc__edge(var_48, var_49, 1, 0, 0, 0);
- __visc__edge(var_48, var_49, 1, 1, 1, 0);
-
- __visc__bindOut(var_49, 0, 0, 0);
- __visc__bindOut(var_49, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* conv2d_6_b;
- size_t conv2d_6_b_bytes;
- void* conv2d_7_w;
- size_t conv2d_7_w_bytes;
- void* conv2d_7_b;
- size_t conv2d_7_b_bytes;
- void* conv2d_8_w;
- size_t conv2d_8_w_bytes;
- void* conv2d_8_b;
- size_t conv2d_8_b_bytes;
- void* conv2d_9_w;
- size_t conv2d_9_w_bytes;
- void* conv2d_9_b;
- size_t conv2d_9_b_bytes;
- void* conv2d_10_w;
- size_t conv2d_10_w_bytes;
- void* conv2d_10_b;
- size_t conv2d_10_b_bytes;
- void* conv2d_11_w;
- size_t conv2d_11_w_bytes;
- void* conv2d_11_b;
- size_t conv2d_11_b_bytes;
- void* conv2d_12_w;
- size_t conv2d_12_w_bytes;
- void* conv2d_12_b;
- size_t conv2d_12_b_bytes;
- void* conv2d_13_w;
- size_t conv2d_13_w_bytes;
- void* conv2d_13_b;
- size_t conv2d_13_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/vgg16_cifar100/");
-
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels32.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,64,3,3,3);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,128,64,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,128,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,128,128,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,128,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,128,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_6_b_path = dir_prefix + std::string("conv2d_6_b.bin");
- void* conv2d_6_b = readTrainedWeights(conv2d_6_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_7_w_path = dir_prefix + std::string("conv2d_7_w.bin");
- void* conv2d_7_w = readTrainedWeights(conv2d_7_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_7_b_path = dir_prefix + std::string("conv2d_7_b.bin");
- void* conv2d_7_b = readTrainedWeights(conv2d_7_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_8_w_path = dir_prefix + std::string("conv2d_8_w.bin");
- void* conv2d_8_w = readTrainedWeights(conv2d_8_w_path.c_str(), 0,512,256,3,3);
- std::string conv2d_8_b_path = dir_prefix + std::string("conv2d_8_b.bin");
- void* conv2d_8_b = readTrainedWeights(conv2d_8_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_9_w_path = dir_prefix + std::string("conv2d_9_w.bin");
- void* conv2d_9_w = readTrainedWeights(conv2d_9_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_9_b_path = dir_prefix + std::string("conv2d_9_b.bin");
- void* conv2d_9_b = readTrainedWeights(conv2d_9_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_10_w_path = dir_prefix + std::string("conv2d_10_w.bin");
- void* conv2d_10_w = readTrainedWeights(conv2d_10_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_10_b_path = dir_prefix + std::string("conv2d_10_b.bin");
- void* conv2d_10_b = readTrainedWeights(conv2d_10_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_11_w_path = dir_prefix + std::string("conv2d_11_w.bin");
- void* conv2d_11_w = readTrainedWeights(conv2d_11_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_11_b_path = dir_prefix + std::string("conv2d_11_b.bin");
- void* conv2d_11_b = readTrainedWeights(conv2d_11_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_12_w_path = dir_prefix + std::string("conv2d_12_w.bin");
- void* conv2d_12_w = readTrainedWeights(conv2d_12_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_12_b_path = dir_prefix + std::string("conv2d_12_b.bin");
- void* conv2d_12_b = readTrainedWeights(conv2d_12_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_13_w_path = dir_prefix + std::string("conv2d_13_w.bin");
- void* conv2d_13_w = readTrainedWeights(conv2d_13_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_13_b_path = dir_prefix + std::string("conv2d_13_b.bin");
- void* conv2d_13_b = readTrainedWeights(conv2d_13_b_path.c_str(), 0,1,512,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,512,512);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,512,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,512,100);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,100,1,1);
-
- void* input = readTrainedWeights(input_path.c_str(), 0,2000,3,32,32);
- uint32_t* labels = readLabels3(labels_path.c_str(),2000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->conv2d_6_b = conv2d_6_b;
- args->conv2d_6_b_bytes = 0;
- args->conv2d_7_w = conv2d_7_w;
- args->conv2d_7_w_bytes = 0;
- args->conv2d_7_b = conv2d_7_b;
- args->conv2d_7_b_bytes = 0;
- args->conv2d_8_w = conv2d_8_w;
- args->conv2d_8_w_bytes = 0;
- args->conv2d_8_b = conv2d_8_b;
- args->conv2d_8_b_bytes = 0;
- args->conv2d_9_w = conv2d_9_w;
- args->conv2d_9_w_bytes = 0;
- args->conv2d_9_b = conv2d_9_b;
- args->conv2d_9_b_bytes = 0;
- args->conv2d_10_w = conv2d_10_w;
- args->conv2d_10_w_bytes = 0;
- args->conv2d_10_b = conv2d_10_b;
- args->conv2d_10_b_bytes = 0;
- args->conv2d_11_w = conv2d_11_w;
- args->conv2d_11_w_bytes = 0;
- args->conv2d_11_b = conv2d_11_b;
- args->conv2d_11_b_bytes = 0;
- args->conv2d_12_w = conv2d_12_w;
- args->conv2d_12_w_bytes = 0;
- args->conv2d_12_b = conv2d_12_b;
- args->conv2d_12_b_bytes = 0;
- args->conv2d_13_w = conv2d_13_w;
- args->conv2d_13_w_bytes = 0;
- args->conv2d_13_b = conv2d_13_b;
- args->conv2d_13_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy3(labels, result);
-
- return 0;
-}
diff --git a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/vgg16_cifar10_promise.cpp b/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/vgg16_cifar10_promise.cpp
deleted file mode 100644
index 32991f8fc4b2a7f1ca77eae9d81a6872c96b3089..0000000000000000000000000000000000000000
--- a/hpvm/test/dnn_benchmarks/benchmarks/legacy/promise_src/vgg16_cifar10_promise.cpp
+++ /dev/null
@@ -1,983 +0,0 @@
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <cstring>
-#include <visc.h>
-#include <tensorTypes.h>
-#include <tensorUtils.h>
-
-void var_0_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_1_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_2_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_3_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_4_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_5_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_6_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_7_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_8_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_9_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_10_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_11_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_12_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_13_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_14_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_15_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_16_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_17_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_18_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_19_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_20_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_21_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_22_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_23_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_24_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_25_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_26_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_27_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_28_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_29_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_30_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_31_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_32_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_33_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_34_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_35_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_36_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_37_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_38_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_39_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_40_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_convolution(t1, t2, 1, 1, 1, 1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_41_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_42_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_43_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_pool_max(t1, 2, 2, 0, 0, 2, 2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_44_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_45_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_46_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_relu(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_47_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_mul(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_48_node(void* t1, size_t bytes_t1, void* t2, size_t bytes_t2) {
- __visc__hint(visc::PROMISE_TARGET);
- __visc__attributes(2, t1, t2, 0);
-
- void *r = __visc__tensor_add(t1, t2);
- __visc__return(2, r, (size_t) 0);
-}
-
-void var_49_node(void* t1, size_t bytes_t1) {
- __visc__hint(visc::CUDNN_TARGET);
- __visc__attributes(1, t1, 0);
-
- void* r = __visc__tensor_softmax(t1);
- __visc__return(2, r, (size_t) 0);
-}
-
-void root(void* input, size_t input_bytes,
- void* conv2d_1_w, size_t conv2d_1_w_bytes,
- void* conv2d_1_b, size_t conv2d_1_b_bytes,
- void* conv2d_2_w, size_t conv2d_2_w_bytes,
- void* conv2d_2_b, size_t conv2d_2_b_bytes,
- void* conv2d_3_w, size_t conv2d_3_w_bytes,
- void* conv2d_3_b, size_t conv2d_3_b_bytes,
- void* conv2d_4_w, size_t conv2d_4_w_bytes,
- void* conv2d_4_b, size_t conv2d_4_b_bytes,
- void* conv2d_5_w, size_t conv2d_5_w_bytes,
- void* conv2d_5_b, size_t conv2d_5_b_bytes,
- void* conv2d_6_w, size_t conv2d_6_w_bytes,
- void* conv2d_6_b, size_t conv2d_6_b_bytes,
- void* conv2d_7_w, size_t conv2d_7_w_bytes,
- void* conv2d_7_b, size_t conv2d_7_b_bytes,
- void* conv2d_8_w, size_t conv2d_8_w_bytes,
- void* conv2d_8_b, size_t conv2d_8_b_bytes,
- void* conv2d_9_w, size_t conv2d_9_w_bytes,
- void* conv2d_9_b, size_t conv2d_9_b_bytes,
- void* conv2d_10_w, size_t conv2d_10_w_bytes,
- void* conv2d_10_b, size_t conv2d_10_b_bytes,
- void* conv2d_11_w, size_t conv2d_11_w_bytes,
- void* conv2d_11_b, size_t conv2d_11_b_bytes,
- void* conv2d_12_w, size_t conv2d_12_w_bytes,
- void* conv2d_12_b, size_t conv2d_12_b_bytes,
- void* conv2d_13_w, size_t conv2d_13_w_bytes,
- void* conv2d_13_b, size_t conv2d_13_b_bytes,
- void* dense_1_w, size_t dense_1_w_bytes,
- void* dense_1_b, size_t dense_1_b_bytes,
- void* dense_2_w, size_t dense_2_w_bytes,
- void* dense_2_b, size_t dense_2_b_bytes){
-
-
- __visc__hint(visc::CPU_TARGET);
- __visc__attributes(31, input, conv2d_1_w, conv2d_1_b, conv2d_2_w, conv2d_2_b, conv2d_3_w, conv2d_3_b, conv2d_4_w, conv2d_4_b, conv2d_5_w, conv2d_5_b, conv2d_6_w, conv2d_6_b, conv2d_7_w, conv2d_7_b, conv2d_8_w, conv2d_8_b, conv2d_9_w, conv2d_9_b, conv2d_10_w, conv2d_10_b, conv2d_11_w, conv2d_11_b, conv2d_12_w, conv2d_12_b, conv2d_13_w, conv2d_13_b, dense_1_w, dense_1_b, dense_2_w, dense_2_b, 0);
-
-
- void* var_0 = __visc__createNodeND(0, var_0_node);
-
- __visc__bindIn(var_0, 0, 0, 0);
- __visc__bindIn(var_0, 1, 1, 0);
- __visc__bindIn(var_0, 2, 2, 0);
- __visc__bindIn(var_0, 3, 3, 0);
-
- void* var_1 = __visc__createNodeND(0, var_1_node);
-
- __visc__edge(var_0, var_1, 1, 0, 0, 0);
- __visc__edge(var_0, var_1, 1, 1, 1, 0);
- __visc__bindIn(var_1, 4, 2, 0);
- __visc__bindIn(var_1, 5, 3, 0);
-
- void* var_2 = __visc__createNodeND(0, var_2_node);
-
- __visc__edge(var_1, var_2, 1, 0, 0, 0);
- __visc__edge(var_1, var_2, 1, 1, 1, 0);
-
- void* var_3 = __visc__createNodeND(0, var_3_node);
-
- __visc__edge(var_2, var_3, 1, 0, 0, 0);
- __visc__edge(var_2, var_3, 1, 1, 1, 0);
- __visc__bindIn(var_3, 6, 2, 0);
- __visc__bindIn(var_3, 7, 3, 0);
-
- void* var_4 = __visc__createNodeND(0, var_4_node);
-
- __visc__edge(var_3, var_4, 1, 0, 0, 0);
- __visc__edge(var_3, var_4, 1, 1, 1, 0);
- __visc__bindIn(var_4, 8, 2, 0);
- __visc__bindIn(var_4, 9, 3, 0);
-
- void* var_5 = __visc__createNodeND(0, var_5_node);
-
- __visc__edge(var_4, var_5, 1, 0, 0, 0);
- __visc__edge(var_4, var_5, 1, 1, 1, 0);
-
- void* var_6 = __visc__createNodeND(0, var_6_node);
-
- __visc__edge(var_5, var_6, 1, 0, 0, 0);
- __visc__edge(var_5, var_6, 1, 1, 1, 0);
-
- void* var_7 = __visc__createNodeND(0, var_7_node);
-
- __visc__edge(var_6, var_7, 1, 0, 0, 0);
- __visc__edge(var_6, var_7, 1, 1, 1, 0);
- __visc__bindIn(var_7, 10, 2, 0);
- __visc__bindIn(var_7, 11, 3, 0);
-
- void* var_8 = __visc__createNodeND(0, var_8_node);
-
- __visc__edge(var_7, var_8, 1, 0, 0, 0);
- __visc__edge(var_7, var_8, 1, 1, 1, 0);
- __visc__bindIn(var_8, 12, 2, 0);
- __visc__bindIn(var_8, 13, 3, 0);
-
- void* var_9 = __visc__createNodeND(0, var_9_node);
-
- __visc__edge(var_8, var_9, 1, 0, 0, 0);
- __visc__edge(var_8, var_9, 1, 1, 1, 0);
-
- void* var_10 = __visc__createNodeND(0, var_10_node);
-
- __visc__edge(var_9, var_10, 1, 0, 0, 0);
- __visc__edge(var_9, var_10, 1, 1, 1, 0);
- __visc__bindIn(var_10, 14, 2, 0);
- __visc__bindIn(var_10, 15, 3, 0);
-
- void* var_11 = __visc__createNodeND(0, var_11_node);
-
- __visc__edge(var_10, var_11, 1, 0, 0, 0);
- __visc__edge(var_10, var_11, 1, 1, 1, 0);
- __visc__bindIn(var_11, 16, 2, 0);
- __visc__bindIn(var_11, 17, 3, 0);
-
- void* var_12 = __visc__createNodeND(0, var_12_node);
-
- __visc__edge(var_11, var_12, 1, 0, 0, 0);
- __visc__edge(var_11, var_12, 1, 1, 1, 0);
-
- void* var_13 = __visc__createNodeND(0, var_13_node);
-
- __visc__edge(var_12, var_13, 1, 0, 0, 0);
- __visc__edge(var_12, var_13, 1, 1, 1, 0);
-
- void* var_14 = __visc__createNodeND(0, var_14_node);
-
- __visc__edge(var_13, var_14, 1, 0, 0, 0);
- __visc__edge(var_13, var_14, 1, 1, 1, 0);
- __visc__bindIn(var_14, 18, 2, 0);
- __visc__bindIn(var_14, 19, 3, 0);
-
- void* var_15 = __visc__createNodeND(0, var_15_node);
-
- __visc__edge(var_14, var_15, 1, 0, 0, 0);
- __visc__edge(var_14, var_15, 1, 1, 1, 0);
- __visc__bindIn(var_15, 20, 2, 0);
- __visc__bindIn(var_15, 21, 3, 0);
-
- void* var_16 = __visc__createNodeND(0, var_16_node);
-
- __visc__edge(var_15, var_16, 1, 0, 0, 0);
- __visc__edge(var_15, var_16, 1, 1, 1, 0);
-
- void* var_17 = __visc__createNodeND(0, var_17_node);
-
- __visc__edge(var_16, var_17, 1, 0, 0, 0);
- __visc__edge(var_16, var_17, 1, 1, 1, 0);
- __visc__bindIn(var_17, 22, 2, 0);
- __visc__bindIn(var_17, 23, 3, 0);
-
- void* var_18 = __visc__createNodeND(0, var_18_node);
-
- __visc__edge(var_17, var_18, 1, 0, 0, 0);
- __visc__edge(var_17, var_18, 1, 1, 1, 0);
- __visc__bindIn(var_18, 24, 2, 0);
- __visc__bindIn(var_18, 25, 3, 0);
-
- void* var_19 = __visc__createNodeND(0, var_19_node);
-
- __visc__edge(var_18, var_19, 1, 0, 0, 0);
- __visc__edge(var_18, var_19, 1, 1, 1, 0);
-
- void* var_20 = __visc__createNodeND(0, var_20_node);
-
- __visc__edge(var_19, var_20, 1, 0, 0, 0);
- __visc__edge(var_19, var_20, 1, 1, 1, 0);
- __visc__bindIn(var_20, 26, 2, 0);
- __visc__bindIn(var_20, 27, 3, 0);
-
- void* var_21 = __visc__createNodeND(0, var_21_node);
-
- __visc__edge(var_20, var_21, 1, 0, 0, 0);
- __visc__edge(var_20, var_21, 1, 1, 1, 0);
- __visc__bindIn(var_21, 28, 2, 0);
- __visc__bindIn(var_21, 29, 3, 0);
-
- void* var_22 = __visc__createNodeND(0, var_22_node);
-
- __visc__edge(var_21, var_22, 1, 0, 0, 0);
- __visc__edge(var_21, var_22, 1, 1, 1, 0);
-
- void* var_23 = __visc__createNodeND(0, var_23_node);
-
- __visc__edge(var_22, var_23, 1, 0, 0, 0);
- __visc__edge(var_22, var_23, 1, 1, 1, 0);
-
- void* var_24 = __visc__createNodeND(0, var_24_node);
-
- __visc__edge(var_23, var_24, 1, 0, 0, 0);
- __visc__edge(var_23, var_24, 1, 1, 1, 0);
- __visc__bindIn(var_24, 30, 2, 0);
- __visc__bindIn(var_24, 31, 3, 0);
-
- void* var_25 = __visc__createNodeND(0, var_25_node);
-
- __visc__edge(var_24, var_25, 1, 0, 0, 0);
- __visc__edge(var_24, var_25, 1, 1, 1, 0);
- __visc__bindIn(var_25, 32, 2, 0);
- __visc__bindIn(var_25, 33, 3, 0);
-
- void* var_26 = __visc__createNodeND(0, var_26_node);
-
- __visc__edge(var_25, var_26, 1, 0, 0, 0);
- __visc__edge(var_25, var_26, 1, 1, 1, 0);
-
- void* var_27 = __visc__createNodeND(0, var_27_node);
-
- __visc__edge(var_26, var_27, 1, 0, 0, 0);
- __visc__edge(var_26, var_27, 1, 1, 1, 0);
- __visc__bindIn(var_27, 34, 2, 0);
- __visc__bindIn(var_27, 35, 3, 0);
-
- void* var_28 = __visc__createNodeND(0, var_28_node);
-
- __visc__edge(var_27, var_28, 1, 0, 0, 0);
- __visc__edge(var_27, var_28, 1, 1, 1, 0);
- __visc__bindIn(var_28, 36, 2, 0);
- __visc__bindIn(var_28, 37, 3, 0);
-
- void* var_29 = __visc__createNodeND(0, var_29_node);
-
- __visc__edge(var_28, var_29, 1, 0, 0, 0);
- __visc__edge(var_28, var_29, 1, 1, 1, 0);
-
- void* var_30 = __visc__createNodeND(0, var_30_node);
-
- __visc__edge(var_29, var_30, 1, 0, 0, 0);
- __visc__edge(var_29, var_30, 1, 1, 1, 0);
- __visc__bindIn(var_30, 38, 2, 0);
- __visc__bindIn(var_30, 39, 3, 0);
-
- void* var_31 = __visc__createNodeND(0, var_31_node);
-
- __visc__edge(var_30, var_31, 1, 0, 0, 0);
- __visc__edge(var_30, var_31, 1, 1, 1, 0);
- __visc__bindIn(var_31, 40, 2, 0);
- __visc__bindIn(var_31, 41, 3, 0);
-
- void* var_32 = __visc__createNodeND(0, var_32_node);
-
- __visc__edge(var_31, var_32, 1, 0, 0, 0);
- __visc__edge(var_31, var_32, 1, 1, 1, 0);
-
- void* var_33 = __visc__createNodeND(0, var_33_node);
-
- __visc__edge(var_32, var_33, 1, 0, 0, 0);
- __visc__edge(var_32, var_33, 1, 1, 1, 0);
-
- void* var_34 = __visc__createNodeND(0, var_34_node);
-
- __visc__edge(var_33, var_34, 1, 0, 0, 0);
- __visc__edge(var_33, var_34, 1, 1, 1, 0);
- __visc__bindIn(var_34, 42, 2, 0);
- __visc__bindIn(var_34, 43, 3, 0);
-
- void* var_35 = __visc__createNodeND(0, var_35_node);
-
- __visc__edge(var_34, var_35, 1, 0, 0, 0);
- __visc__edge(var_34, var_35, 1, 1, 1, 0);
- __visc__bindIn(var_35, 44, 2, 0);
- __visc__bindIn(var_35, 45, 3, 0);
-
- void* var_36 = __visc__createNodeND(0, var_36_node);
-
- __visc__edge(var_35, var_36, 1, 0, 0, 0);
- __visc__edge(var_35, var_36, 1, 1, 1, 0);
-
- void* var_37 = __visc__createNodeND(0, var_37_node);
-
- __visc__edge(var_36, var_37, 1, 0, 0, 0);
- __visc__edge(var_36, var_37, 1, 1, 1, 0);
- __visc__bindIn(var_37, 46, 2, 0);
- __visc__bindIn(var_37, 47, 3, 0);
-
- void* var_38 = __visc__createNodeND(0, var_38_node);
-
- __visc__edge(var_37, var_38, 1, 0, 0, 0);
- __visc__edge(var_37, var_38, 1, 1, 1, 0);
- __visc__bindIn(var_38, 48, 2, 0);
- __visc__bindIn(var_38, 49, 3, 0);
-
- void* var_39 = __visc__createNodeND(0, var_39_node);
-
- __visc__edge(var_38, var_39, 1, 0, 0, 0);
- __visc__edge(var_38, var_39, 1, 1, 1, 0);
-
- void* var_40 = __visc__createNodeND(0, var_40_node);
-
- __visc__edge(var_39, var_40, 1, 0, 0, 0);
- __visc__edge(var_39, var_40, 1, 1, 1, 0);
- __visc__bindIn(var_40, 50, 2, 0);
- __visc__bindIn(var_40, 51, 3, 0);
-
- void* var_41 = __visc__createNodeND(0, var_41_node);
-
- __visc__edge(var_40, var_41, 1, 0, 0, 0);
- __visc__edge(var_40, var_41, 1, 1, 1, 0);
- __visc__bindIn(var_41, 52, 2, 0);
- __visc__bindIn(var_41, 53, 3, 0);
-
- void* var_42 = __visc__createNodeND(0, var_42_node);
-
- __visc__edge(var_41, var_42, 1, 0, 0, 0);
- __visc__edge(var_41, var_42, 1, 1, 1, 0);
-
- void* var_43 = __visc__createNodeND(0, var_43_node);
-
- __visc__edge(var_42, var_43, 1, 0, 0, 0);
- __visc__edge(var_42, var_43, 1, 1, 1, 0);
-
- void* var_44 = __visc__createNodeND(0, var_44_node);
-
- __visc__edge(var_43, var_44, 1, 0, 0, 0);
- __visc__edge(var_43, var_44, 1, 1, 1, 0);
- __visc__bindIn(var_44, 54, 2, 0);
- __visc__bindIn(var_44, 55, 3, 0);
-
- void* var_45 = __visc__createNodeND(0, var_45_node);
-
- __visc__edge(var_44, var_45, 1, 0, 0, 0);
- __visc__edge(var_44, var_45, 1, 1, 1, 0);
- __visc__bindIn(var_45, 56, 2, 0);
- __visc__bindIn(var_45, 57, 3, 0);
-
- void* var_46 = __visc__createNodeND(0, var_46_node);
-
- __visc__edge(var_45, var_46, 1, 0, 0, 0);
- __visc__edge(var_45, var_46, 1, 1, 1, 0);
-
- void* var_47 = __visc__createNodeND(0, var_47_node);
-
- __visc__edge(var_46, var_47, 1, 0, 0, 0);
- __visc__edge(var_46, var_47, 1, 1, 1, 0);
- __visc__bindIn(var_47, 58, 2, 0);
- __visc__bindIn(var_47, 59, 3, 0);
-
- void* var_48 = __visc__createNodeND(0, var_48_node);
-
- __visc__edge(var_47, var_48, 1, 0, 0, 0);
- __visc__edge(var_47, var_48, 1, 1, 1, 0);
- __visc__bindIn(var_48, 60, 2, 0);
- __visc__bindIn(var_48, 61, 3, 0);
-
- void* var_49 = __visc__createNodeND(0, var_49_node);
-
- __visc__edge(var_48, var_49, 1, 0, 0, 0);
- __visc__edge(var_48, var_49, 1, 1, 1, 0);
-
- __visc__bindOut(var_49, 0, 0, 0);
- __visc__bindOut(var_49, 1, 1, 0);
-
-}
-
-struct ret_t {
- void* tensor;
- size_t bytes;
-};
-
-typedef struct __attribute__((__packed__)) {
- void* input;
- size_t input_bytes;
- void* conv2d_1_w;
- size_t conv2d_1_w_bytes;
- void* conv2d_1_b;
- size_t conv2d_1_b_bytes;
- void* conv2d_2_w;
- size_t conv2d_2_w_bytes;
- void* conv2d_2_b;
- size_t conv2d_2_b_bytes;
- void* conv2d_3_w;
- size_t conv2d_3_w_bytes;
- void* conv2d_3_b;
- size_t conv2d_3_b_bytes;
- void* conv2d_4_w;
- size_t conv2d_4_w_bytes;
- void* conv2d_4_b;
- size_t conv2d_4_b_bytes;
- void* conv2d_5_w;
- size_t conv2d_5_w_bytes;
- void* conv2d_5_b;
- size_t conv2d_5_b_bytes;
- void* conv2d_6_w;
- size_t conv2d_6_w_bytes;
- void* conv2d_6_b;
- size_t conv2d_6_b_bytes;
- void* conv2d_7_w;
- size_t conv2d_7_w_bytes;
- void* conv2d_7_b;
- size_t conv2d_7_b_bytes;
- void* conv2d_8_w;
- size_t conv2d_8_w_bytes;
- void* conv2d_8_b;
- size_t conv2d_8_b_bytes;
- void* conv2d_9_w;
- size_t conv2d_9_w_bytes;
- void* conv2d_9_b;
- size_t conv2d_9_b_bytes;
- void* conv2d_10_w;
- size_t conv2d_10_w_bytes;
- void* conv2d_10_b;
- size_t conv2d_10_b_bytes;
- void* conv2d_11_w;
- size_t conv2d_11_w_bytes;
- void* conv2d_11_b;
- size_t conv2d_11_b_bytes;
- void* conv2d_12_w;
- size_t conv2d_12_w_bytes;
- void* conv2d_12_b;
- size_t conv2d_12_b_bytes;
- void* conv2d_13_w;
- size_t conv2d_13_w_bytes;
- void* conv2d_13_b;
- size_t conv2d_13_b_bytes;
- void* dense_1_w;
- size_t dense_1_w_bytes;
- void* dense_1_b;
- size_t dense_1_b_bytes;
- void* dense_2_w;
- size_t dense_2_w_bytes;
- void* dense_2_b;
- size_t dense_2_b_bytes;
-
- struct ret_t r;
-}
-RootIn;
-
-
-int main(){
-
- std::string dir_prefix = std::string("../../../../../../projects/hpvm-tensor-rt/model_params/vgg16_cifar10/");
- std::string input_path = dir_prefix + std::string("input.bin");
- std::string labels_path = dir_prefix + std::string("labels32.bin");
- std::string conv2d_1_w_path = dir_prefix + std::string("conv2d_1_w.bin");
- void* conv2d_1_w = readTrainedWeights(conv2d_1_w_path.c_str(), 0,64,3,3,3);
- std::string conv2d_1_b_path = dir_prefix + std::string("conv2d_1_b.bin");
- void* conv2d_1_b = readTrainedWeights(conv2d_1_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_2_w_path = dir_prefix + std::string("conv2d_2_w.bin");
- void* conv2d_2_w = readTrainedWeights(conv2d_2_w_path.c_str(), 0,64,64,3,3);
- std::string conv2d_2_b_path = dir_prefix + std::string("conv2d_2_b.bin");
- void* conv2d_2_b = readTrainedWeights(conv2d_2_b_path.c_str(), 0,1,64,1,1);
- std::string conv2d_3_w_path = dir_prefix + std::string("conv2d_3_w.bin");
- void* conv2d_3_w = readTrainedWeights(conv2d_3_w_path.c_str(), 0,128,64,3,3);
- std::string conv2d_3_b_path = dir_prefix + std::string("conv2d_3_b.bin");
- void* conv2d_3_b = readTrainedWeights(conv2d_3_b_path.c_str(), 0,1,128,1,1);
- std::string conv2d_4_w_path = dir_prefix + std::string("conv2d_4_w.bin");
- void* conv2d_4_w = readTrainedWeights(conv2d_4_w_path.c_str(), 0,128,128,3,3);
- std::string conv2d_4_b_path = dir_prefix + std::string("conv2d_4_b.bin");
- void* conv2d_4_b = readTrainedWeights(conv2d_4_b_path.c_str(), 0,1,128,1,1);
- std::string conv2d_5_w_path = dir_prefix + std::string("conv2d_5_w.bin");
- void* conv2d_5_w = readTrainedWeights(conv2d_5_w_path.c_str(), 0,256,128,3,3);
- std::string conv2d_5_b_path = dir_prefix + std::string("conv2d_5_b.bin");
- void* conv2d_5_b = readTrainedWeights(conv2d_5_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_6_w_path = dir_prefix + std::string("conv2d_6_w.bin");
- void* conv2d_6_w = readTrainedWeights(conv2d_6_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_6_b_path = dir_prefix + std::string("conv2d_6_b.bin");
- void* conv2d_6_b = readTrainedWeights(conv2d_6_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_7_w_path = dir_prefix + std::string("conv2d_7_w.bin");
- void* conv2d_7_w = readTrainedWeights(conv2d_7_w_path.c_str(), 0,256,256,3,3);
- std::string conv2d_7_b_path = dir_prefix + std::string("conv2d_7_b.bin");
- void* conv2d_7_b = readTrainedWeights(conv2d_7_b_path.c_str(), 0,1,256,1,1);
- std::string conv2d_8_w_path = dir_prefix + std::string("conv2d_8_w.bin");
- void* conv2d_8_w = readTrainedWeights(conv2d_8_w_path.c_str(), 0,512,256,3,3);
- std::string conv2d_8_b_path = dir_prefix + std::string("conv2d_8_b.bin");
- void* conv2d_8_b = readTrainedWeights(conv2d_8_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_9_w_path = dir_prefix + std::string("conv2d_9_w.bin");
- void* conv2d_9_w = readTrainedWeights(conv2d_9_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_9_b_path = dir_prefix + std::string("conv2d_9_b.bin");
- void* conv2d_9_b = readTrainedWeights(conv2d_9_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_10_w_path = dir_prefix + std::string("conv2d_10_w.bin");
- void* conv2d_10_w = readTrainedWeights(conv2d_10_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_10_b_path = dir_prefix + std::string("conv2d_10_b.bin");
- void* conv2d_10_b = readTrainedWeights(conv2d_10_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_11_w_path = dir_prefix + std::string("conv2d_11_w.bin");
- void* conv2d_11_w = readTrainedWeights(conv2d_11_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_11_b_path = dir_prefix + std::string("conv2d_11_b.bin");
- void* conv2d_11_b = readTrainedWeights(conv2d_11_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_12_w_path = dir_prefix + std::string("conv2d_12_w.bin");
- void* conv2d_12_w = readTrainedWeights(conv2d_12_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_12_b_path = dir_prefix + std::string("conv2d_12_b.bin");
- void* conv2d_12_b = readTrainedWeights(conv2d_12_b_path.c_str(), 0,1,512,1,1);
- std::string conv2d_13_w_path = dir_prefix + std::string("conv2d_13_w.bin");
- void* conv2d_13_w = readTrainedWeights(conv2d_13_w_path.c_str(), 0,512,512,3,3);
- std::string conv2d_13_b_path = dir_prefix + std::string("conv2d_13_b.bin");
- void* conv2d_13_b = readTrainedWeights(conv2d_13_b_path.c_str(), 0,1,512,1,1);
- std::string dense_1_w_path = dir_prefix + std::string("dense_1_w.bin");
- void* dense_1_w = readTrainedWeights(dense_1_w_path.c_str(), 0,1,1,512,512);
- std::string dense_1_b_path = dir_prefix + std::string("dense_1_b.bin");
- void* dense_1_b = readTrainedWeights(dense_1_b_path.c_str(), 0,1,512,1,1);
- std::string dense_2_w_path = dir_prefix + std::string("dense_2_w.bin");
- void* dense_2_w = readTrainedWeights(dense_2_w_path.c_str(), 0,1,1,512,10);
- std::string dense_2_b_path = dir_prefix + std::string("dense_2_b.bin");
- void* dense_2_b = readTrainedWeights(dense_2_b_path.c_str(), 0,1,10,1,1);
- void* input = readTrainedWeights(input_path.c_str(), 0,2000,3,32,32);
- uint32_t* labels = readLabels3(labels_path.c_str(),2000);
-
- __visc__init();
- RootIn* args = static_cast<RootIn*>(malloc(sizeof(RootIn)));
-
- args->input = input;
- args->input_bytes = 0;
- args->conv2d_1_w = conv2d_1_w;
- args->conv2d_1_w_bytes = 0;
- args->conv2d_1_b = conv2d_1_b;
- args->conv2d_1_b_bytes = 0;
- args->conv2d_2_w = conv2d_2_w;
- args->conv2d_2_w_bytes = 0;
- args->conv2d_2_b = conv2d_2_b;
- args->conv2d_2_b_bytes = 0;
- args->conv2d_3_w = conv2d_3_w;
- args->conv2d_3_w_bytes = 0;
- args->conv2d_3_b = conv2d_3_b;
- args->conv2d_3_b_bytes = 0;
- args->conv2d_4_w = conv2d_4_w;
- args->conv2d_4_w_bytes = 0;
- args->conv2d_4_b = conv2d_4_b;
- args->conv2d_4_b_bytes = 0;
- args->conv2d_5_w = conv2d_5_w;
- args->conv2d_5_w_bytes = 0;
- args->conv2d_5_b = conv2d_5_b;
- args->conv2d_5_b_bytes = 0;
- args->conv2d_6_w = conv2d_6_w;
- args->conv2d_6_w_bytes = 0;
- args->conv2d_6_b = conv2d_6_b;
- args->conv2d_6_b_bytes = 0;
- args->conv2d_7_w = conv2d_7_w;
- args->conv2d_7_w_bytes = 0;
- args->conv2d_7_b = conv2d_7_b;
- args->conv2d_7_b_bytes = 0;
- args->conv2d_8_w = conv2d_8_w;
- args->conv2d_8_w_bytes = 0;
- args->conv2d_8_b = conv2d_8_b;
- args->conv2d_8_b_bytes = 0;
- args->conv2d_9_w = conv2d_9_w;
- args->conv2d_9_w_bytes = 0;
- args->conv2d_9_b = conv2d_9_b;
- args->conv2d_9_b_bytes = 0;
- args->conv2d_10_w = conv2d_10_w;
- args->conv2d_10_w_bytes = 0;
- args->conv2d_10_b = conv2d_10_b;
- args->conv2d_10_b_bytes = 0;
- args->conv2d_11_w = conv2d_11_w;
- args->conv2d_11_w_bytes = 0;
- args->conv2d_11_b = conv2d_11_b;
- args->conv2d_11_b_bytes = 0;
- args->conv2d_12_w = conv2d_12_w;
- args->conv2d_12_w_bytes = 0;
- args->conv2d_12_b = conv2d_12_b;
- args->conv2d_12_b_bytes = 0;
- args->conv2d_13_w = conv2d_13_w;
- args->conv2d_13_w_bytes = 0;
- args->conv2d_13_b = conv2d_13_b;
- args->conv2d_13_b_bytes = 0;
- args->dense_1_w = dense_1_w;
- args->dense_1_w_bytes = 0;
- args->dense_1_b = dense_1_b;
- args->dense_1_b_bytes = 0;
- args->dense_2_w = dense_2_w;
- args->dense_2_w_bytes = 0;
- args->dense_2_b = dense_2_b;
- args->dense_2_b_bytes = 0;
-
- void* dfg = __visc__launch(0, root, (void*) args);
-
- __visc__wait(dfg);
-
- void *result = static_cast<RootIn*>(args)->input;
- hpvm_request_tensor(result, 0);
-
- __visc__cleanup();
- computeAccuracy3(labels, result);
-
- return 0;
-}